dt-bindings: mfd: qcom-spmi-pmic: add support for PMP8074
Subsystems (9)
PATCH v7 1/7 dt-bindings: mfd: qcom-spmi-pmic: add support for PMP8074
Document compatible for the PMP8074 PMIC.
---
Changes in v7:
* Fixup commit description
I planned to convert the bindings to dtschema, but there is already a patch to do so [1].
I will make a patch to add the compatible to dtschema once it gets accepted.
[1] https://lore.kernel.org/linux-arm-msm/[email protected]/
--- Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt +1 -0
@@ -46,6 +46,7 @@ Required properties: "qcom,pmi8998", "qcom,pmk8002", "qcom,pmk8350", + "qcom,pmp8074", "qcom,pmr735a", "qcom,smb2351", or generalized "qcom,spmi-pmic".
Signature · 1 line
2.36.1
PATCH v7 2/7 mfd: qcom-spmi-pmic: add support for PMP8074
Add support for PMP8074 PMIC which is a companion PMIC for the Qualcomm IPQ8074 SoC-s.
It shares the same subtype identifier as PM8901.
--- drivers/mfd/qcom-spmi-pmic.c | 1 + 1 file changed, 1 insertion(+)
drivers/mfd/qcom-spmi-pmic.c +1 -0
@@ -60,6 +60,7 @@ static const struct of_device_id pmic_spmi_id_table[] = { { .compatible = "qcom,pmi8994", .data = N_USIDS(2) }, { .compatible = "qcom,pmi8998", .data = N_USIDS(2) }, { .compatible = "qcom,pmk8002", .data = N_USIDS(2) }, + { .compatible = "qcom,pmp8074", .data = N_USIDS(2) }, { .compatible = "qcom,smb2351", .data = N_USIDS(2) }, { .compatible = "qcom,spmi-pmic", .data = N_USIDS(1) }, { }
Signature · 1 line
2.36.1
PATCH v7 3/7 dt-bindings: pinctrl: qcom,pmic-gpio: add PMP8074
In reply to Robert MarkoDocument the compatible for PMP8074 which has 12 GPIO-s with holes at GPIO1 and GPIO12.
--- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 3 +++ 1 file changed, 3 insertions(+)
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +3 -0
@@ -52,6 +52,7 @@ properties: - qcom,pmi8998-gpio - qcom,pmk8350-gpio - qcom,pmm8155au-gpio + - qcom,pmp8074-gpio - qcom,pmr735a-gpio - qcom,pmr735b-gpio - qcom,pms405-gpio
@@ -233,6 +234,7 @@ allOf: - qcom,pm8150b-gpio - qcom,pm8150l-gpio - qcom,pmc8180c-gpio + - qcom,pmp8074-gpio - qcom,pms405-gpio then: properties:
@@ -415,6 +417,7 @@ $defs: - gpio1-gpio10 for pmi8994 - gpio1-gpio4 for pmk8350 - gpio1-gpio10 for pmm8155au + - gpio1-gpio12 for pmp8074 (holes on gpio1 and gpio12) - gpio1-gpio4 for pmr735a - gpio1-gpio4 for pmr735b - gpio1-gpio12 for pms405 (holes on gpio1, gpio9
Signature · 1 line
2.36.1
Re: [PATCH v7 3/7] dt-bindings: pinctrl: qcom,pmic-gpio: add PMP8074
Quoted 5 lines · Robert Marko
Document the compatible for PMP8074 which has 12 GPIO-s with holes at GPIO1 and GPIO12.
Signed-off-by Robert Marko <[email protected]>
Patch applied to the pinctrl tree.
Yours,
Linus Walleij
Re: [PATCH v7 3/7] dt-bindings: pinctrl: qcom,pmic-gpio: add PMP8074
Quoted 10 lines · Linus Walleij
Quoted 5 lines · Robert Marko
Document the compatible for PMP8074 which has 12 GPIO-s with holes at GPIO1 and GPIO12.
Signed-off-by Robert Marko <[email protected]>Patch applied to the pinctrl tree.
Hi Linus,
Dont want to bother you, but I am not seeing this and the GPIO patch in the pinctrl tree.
Regards,
Robert
Quoted 3 lines
Yours,
Linus Walleij
Re: [PATCH v7 3/7] dt-bindings: pinctrl: qcom,pmic-gpio: add PMP8074
Quoted 6 lines · Robert Marko
Quoted 5 lines · Linus Walleij
Quoted 3 lines · Robert Marko
Document the compatible for PMP8074 which has 12 GPIO-s with holes at GPIO1 and GPIO12.
Quoted 8 lines
Quoted 4 lines
Quoted 2 lines
Signed-off-by Robert Marko <[email protected]>Patch applied to the pinctrl tree.
Hi Linus,
Dont want to bother you, but I am not seeing this and the GPIO patch in the pinctrl tree.
It was stuck in test loops.
I will push it out soon.
Yours,
Linus Walleij
PATCH v7 4/7 pinctrl: qcom-pmic-gpio: add support for PMP8074
In reply to Robert MarkoPMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12.
--- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 2 ++ 1 file changed, 2 insertions(+)
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +2 -0
@@ -1180,6 +1180,8 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 }, { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 }, + /* pmp8074 has 12 GPIOs with holes on 1 and 12 */ + { .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 }, { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
Signature · 1 line
2.36.1
Re: [PATCH v7 4/7] pinctrl: qcom-pmic-gpio: add support for PMP8074
Quoted 3 lines · Robert Marko
PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12.
Signed-off-by Robert Marko <[email protected]>
Patch applied to the pinctrl tree.
Yours,
Linus Walleij
PATCH v7 5/7 iio: adc: qcom-spmi-adc5: add ADC5_VREF_VADC to rev2 ADC5
In reply to Robert MarkoAdd support for ADC5_VREF_VADC channel to rev2 ADC5 channel list. This channel measures the VADC reference LDO output.
--- drivers/iio/adc/qcom-spmi-adc5.c | 2 ++ 1 file changed, 2 insertions(+)
drivers/iio/adc/qcom-spmi-adc5.c +2 -0
@@ -589,6 +589,8 @@ static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = { SCALE_HW_CALIB_DEFAULT) [ADC5_1P25VREF ] =ADC5_CHAN_VOLT ("vref_1p25" ,0 ,SCALE_HW_CALIB_DEFAULT ) + [ADC5_VREF_VADC ] =ADC5_CHAN_VOLT ("vref_vadc" ,0 , +SCALE_HW_CALIB_DEFAULT ) [ADC5_VPH_PWR ] =ADC5_CHAN_VOLT ("vph_pwr" ,1 ,SCALE_HW_CALIB_DEFAULT ) [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,
Signature · 1 line
2.36.1
PATCH v7 6/7 arm64: dts: qcom: add PMP8074 DTSI
In reply to Robert MarkoPMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is controlled via SPMI.
Add DTSI for it providing GPIO, regulator, RTC and VADC support.
RTC is disabled by default as there is no built-in battery so it will loose time unless board vendor added a battery, so make it optional.
---
Changes in v7:
* Dual license with BSD-3-Clause
* Use "-" instead of underscores in node names
Changes in v6:
* Add RTC and GPIO nodes
Changes in v5:
* Remove #address-cells and #size-cells as they are not required for regulator subnodes
--- arch/arm64/boot/dts/qcom/pmp8074.dtsi | 125 ++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmp8074.dtsi
arch/arm64/boot/dts/qcom/pmp8074.dtsi new file +125 -0
@@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause + +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/iio/qcom,spmi-vadc.h> + +&spmi_bus { + pmic@0 { + compatible = "qcom,pmp8074", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmp8074_adc: adc@3100 { + compatible = "qcom,spmi-adc-rev2"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + ref-gnd@0 { + reg = <ADC5_REF_GND>; + qcom,pre-scaling = <1 1>; + }; + + vref-1p25@1 { + reg = <ADC5_1P25VREF>; + qcom,pre-scaling = <1 1>; + }; + + vref-vadc@2 { + reg = <ADC5_VREF_VADC>; + qcom,pre-scaling = <1 1>; + }; + + pmic_die: die-temp@6 { + reg = <ADC5_DIE_TEMP>; + qcom,pre-scaling = <1 1>; + }; + + xo_therm: xo-temp@76 { + reg = <ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1: thermistor1@77 { + reg = <ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2: thermistor2@78 { + reg = <ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm3: thermistor3@79 { + reg = <ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + vph-pwr@131 { + reg = <ADC5_VPH_PWR>; + qcom,pre-scaling = <1 3>; + }; + }; + + pmp8074_rtc: rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + allow-set-time; + status = "disabled"; + }; + + pmp8074_gpios: gpio@c000 { + compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmp8074_gpios 0 0 12>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pmp8074", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + + regulators { + compatible = "qcom,pmp8074-regulators"; + + s3: s3 { + regulator-name = "vdd_s3"; + regulator-min-microvolt = <592000>; + regulator-max-microvolt = <1064000>; + regulator-always-on; + regulator-boot-on; + }; + + s4: s4 { + regulator-name = "vdd_s4"; + regulator-min-microvolt = <712000>; + regulator-max-microvolt = <992000>; + regulator-always-on; + regulator-boot-on; + }; + + l11: l11 { + regulator-name = "l11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +};
Signature · 1 line
2.36.1
PATCH v7 7/7 arm64: dts: qcom: ipq8074-hk01: add VQMMC supply
In reply to Robert MarkoSince now we have control over the PMP8074 PMIC providing various system voltages including L11 which provides the SDIO/eMMC I/O voltage set it as the SDHCI VQMMC supply.
This allows SDHCI controller to switch to 1.8V I/O mode and support high speed modes like HS200 and HS400.
--- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 ++ 1 file changed, 2 insertions(+)
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +2 -0
@@ -3,6 +3,7 @@ /* Copyright (c) 2017, The Linux Foundation. All rights reserved. */ #include "ipq8074.dtsi" +#include "pmp8074.dtsi" / { #address-cells = <0x2>;
@@ -87,6 +88,7 @@ nand@0 { &sdhc_1 { status = "okay"; + vqmmc-supply = <&l11>; }; &qusb_phy_0 {
Signature · 1 line
2.36.1