spi: npcm-fiu: add Arbel NPCM8XX support

PATCH In review Tomer Maimon 2 participants 5 messages Jul 18, 2022 – Jul 20, 2022

Subsystems (3)

Device tree bindings SPI Arm/nuvoton npcm architecture

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Tomer Maimon

author maintainer

2022-07-18 08:12 UTC #0 lore raw

cover spi: npcm-fiu: add Arbel NPCM8XX support

This patch set adds Arbel NPCM8XX Flash Interface Unit (FIU) support to FIU NPCM driver and modify direct read dummy configuration.

NPCM8XX FIU supports four controllers.

The NPCM FIU driver tested on NPCM845 evaluation board.

Tomer Maimon (3):
spi: npcm-fiu: Modify direct read dummy configuration
dt-binding: spi: Add npcm845 compatible to npcm-fiu document
spi: npcm-fiu: Add NPCM8XX support

 .../bindings/spi/nuvoton,npcm-fiu.txt         | 13 ++++++++-
 drivers/spi/spi-npcm-fiu.c                    | 28 +++++++++++++++++--
 2 files changed, 38 insertions(+), 3 deletions(-)

Signature · 1 line

2.33.0

Tomer Maimon

author maintainer

2022-07-18 08:12 UTC #1 lore raw

PATCH 1/3 spi: npcm-fiu: Modify direct read dummy configuration

Modify NPCM BMC FIU direct read dummy configuration that according spi-mem direct read function.

Signed-off-by Tomer Maimon <[email protected]>

---
 drivers/spi/spi-npcm-fiu.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

drivers/spi/spi-npcm-fiu.c +1 -2

index ba67dbed9fb8..d5b4fe7b9b62 100644
@@ -252,8 +252,7 @@ static void npcm_fiu_set_drd(struct npcm_fiu_spi *fiu,
 	fiu->drd_op.addr.buswidth = op->addr.buswidth;
 	regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
 			   NPCM_FIU_DRD_CFG_DBW,
-			   ((op->dummy.nbytes * ilog2(op->addr.buswidth)) / BITS_PER_BYTE)
-			   << NPCM_FIU_DRD_DBW_SHIFT);
+			   op->dummy.nbytes << NPCM_FIU_DRD_DBW_SHIFT);
 	fiu->drd_op.dummy.nbytes = op->dummy.nbytes;
 	regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
 			   NPCM_FIU_DRD_CFG_RDCMD, op->cmd.opcode);

Signature · 1 line

2.33.0

Tomer Maimon

author maintainer

2022-07-18 08:12 UTC #2 lore raw

PATCH 2/3 dt-binding: spi: Add npcm845 compatible to npcm-fiu document

In reply to Tomer Maimon

Add a compatible string and description for Nuvoton BMC NPCM845 FIU.

Signed-off-by Tomer Maimon <[email protected]>

---
 .../devicetree/bindings/spi/nuvoton,npcm-fiu.txt    | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt +12 -1

index a388005842ad..c63ce4cc0a80 100644
@@ -6,8 +6,13 @@ The NPCM7XX supports three FIU modules,
 FIU0 and FIUx supports two chip selects,
 FIU3 support four chip select.
 
+The NPCM8XX supports four FIU modules,
+FIU0 and FIUx supports two chip selects,
+FIU1 and FIU3 supports four chip selects.
+
 Required properties:
-  - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
+  - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC
+			     "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC
   - #address-cells : should be 1.
   - #size-cells : should be 0.
   - reg : the first contains the register location and length,

@@ -30,6 +35,12 @@ Aliases:
   		fiu1 represent fiu 3 controller
   		fiu2 represent fiu x controller
 
+  In the NPCM8XX BMC:
+  		fiu0 represent fiu 0 controller
+  		fiu1 represent fiu 1 controller
+  		fiu2 represent fiu 3 controller
+  		fiu3 represent fiu x controller
+
 Example:
 fiu3: spi@c00000000 {
 	compatible = "nuvoton,npcm750-fiu";

Signature · 1 line

2.33.0

Tomer Maimon

author maintainer

2022-07-18 08:12 UTC #3 lore raw

PATCH 3/3 spi: npcm-fiu: Add NPCM8XX support

In reply to Tomer Maimon

Adding FIU NPCM8XX support to NPCM FIU driver.
NPCM8XX FIU supports four controllers.

As part of adding NPCM8XX support:
- Add NPCM8XX specific compatible string.
- Using an internal burst configuration register instead of a GCR register.
- Support FIU1 controller.

Signed-off-by Tomer Maimon <[email protected]>

---
 drivers/spi/spi-npcm-fiu.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

drivers/spi/spi-npcm-fiu.c +25 -0

index d5b4fe7b9b62..49f6424e35af 100644
@@ -36,6 +36,7 @@
 #define NPCM_FIU_UMA_DR1		0x34
 #define NPCM_FIU_UMA_DR2		0x38
 #define NPCM_FIU_UMA_DR3		0x3C
+#define NPCM_FIU_CFG			0x78
 #define NPCM_FIU_MAX_REG_LIMIT		0x80
 
 /* FIU Direct Read Configuration Register */

@@ -151,6 +152,9 @@
 #define NPCM_FIU_UMA_DR3_RB13		GENMASK(15, 8)
 #define NPCM_FIU_UMA_DR3_RB12		GENMASK(7, 0)
 
+/* FIU Configuration Register */
+#define NPCM_FIU_CFG_FIU_FIX		BIT(31)
+
 /* FIU Read Mode */
 enum {
 	DRD_SINGLE_WIRE_MODE	= 0,

@@ -187,6 +191,7 @@ enum {
 	FIU0 = 0,
 	FIU3,
 	FIUX,
+	FIU1,
 };
 
 struct npcm_fiu_info {

@@ -214,6 +219,21 @@ static const struct fiu_data npcm7xx_fiu_data = {
 	.fiu_max = 3,
 };
 
+static const struct npcm_fiu_info npxm8xx_fiu_info[] = {
+	{.name = "FIU0", .fiu_id = FIU0,
+		.max_map_size = MAP_SIZE_128MB, .max_cs = 2},
+	{.name = "FIU3", .fiu_id = FIU3,
+		.max_map_size = MAP_SIZE_128MB, .max_cs = 4},
+	{.name = "FIUX", .fiu_id = FIUX,
+		.max_map_size = MAP_SIZE_16MB, .max_cs = 2},
+	{.name = "FIU1", .fiu_id = FIU1,
+		.max_map_size = MAP_SIZE_16MB, .max_cs = 4} };
+
+static const struct fiu_data npxm8xx_fiu_data = {
+	.npcm_fiu_data_info = npxm8xx_fiu_info,
+	.fiu_max = 4,
+};
+
 struct npcm_fiu_spi;
 
 struct npcm_fiu_chip {

@@ -624,6 +644,10 @@ static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
 		regmap_update_bits(gcr_regmap, NPCM7XX_INTCR3_OFFSET,
 				   NPCM7XX_INTCR3_FIU_FIX,
 				   NPCM7XX_INTCR3_FIU_FIX);
+	} else {
+		regmap_update_bits(fiu->regmap, NPCM_FIU_CFG,
+				   NPCM_FIU_CFG_FIU_FIX,
+				   NPCM_FIU_CFG_FIU_FIX);
 	}
 
 	if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) {

@@ -664,6 +688,7 @@ static const struct spi_controller_mem_ops npcm_fiu_mem_ops = {
 
 static const struct of_device_id npcm_fiu_dt_ids[] = {
 	{ .compatible = "nuvoton,npcm750-fiu", .data = &npcm7xx_fiu_data  },
+	{ .compatible = "nuvoton,npcm845-fiu", .data = &npxm8xx_fiu_data  },
 	{ /* sentinel */ }
 };

Signature · 1 line

2.33.0

Mark Brown

maintainer

2022-07-20 18:07 UTC #4 lore raw

In reply to Tomer Maimon

Quoted 8 lines · Tomer Maimon

This patch set adds Arbel NPCM8XX Flash Interface Unit (FIU) support to FIU NPCM driver and modify direct read dummy configuration.
NPCM8XX FIU supports four controllers.
The NPCM FIU driver tested on NPCM845 evaluation board.
[...]

Applied to

https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/3] spi: npcm-fiu: Modify direct read dummy configuration

      commit: 7c3193f7890a03fc1b5b979f3f8dc8750ef47b13
[2/3] dt-binding: spi: Add npcm845 compatible to npcm-fiu document
      commit: d50fef8ae939c2b50431fe6a11457e7ff85aea55
[3/3] spi: npcm-fiu: Add NPCM8XX support
      commit: 650b014facca5238e25399f28da1e59747bddb99

All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark