Configure dmtimers for am65

PATCH Superseded Tony Lindgren 2 participants 6 messages Aug 30, 2022 – Sep 1, 2022

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Device tree bindings Arm/Texas Instruments K3 architecture

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Tony Lindgren

author

2022-08-30 07:09 UTC #0 lore raw

v2 cover Configure dmtimers for am65

Hi all,

Here's v2 series for adding the dmtimers for am65. The device tree binding and related driver related changes have been already merged.

Regards,

Tony

Changes since v1:

- Update to use the mux clock and configure it for 25 mHz source clock with assigned-clocks

- Update patch descriptions

Tony Lindgren (2):
arm64: dts: ti: k3-am65: Configure pinctrl for timer IO pads
arm64: dts: ti: k3-am65: Add general purpose timers for am65

 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 150 +++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  |  59 +++++++++
 2 files changed, 209 insertions(+)

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Tony Lindgren

author

2022-08-30 07:09 UTC #1 lore raw

PATCH v2 1/2 arm64: dts: ti: k3-am65: Configure pinctrl for timer IO pads

Compared to the earlier TI SoCs, am65 has an additional level of dedicated multiplexing registers for the timer IO pads.

There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers.

There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output.

The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the CASCADE_EN bit is documented in TRM "12.8.3.1 Timers Overview".

For chaining timers, the timer IO control registers also have a CASCADE_EN input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit muxes the previous timer output, or possibly and external TIMER_IO pad source, to the input clock of the selected timer instance for odd numered timers. For the even numbered timers, the CASCADE_EN bit does not do anything. The timer cascade input routing options are shown in TRM "Figure 12-3632. Timers Overview". For handling beyond multiplexing, the driver support for timer cascading should be likely be handled via the clock framework.

Cc Keerthy <[email protected]>

Cc Nishanth Menon <[email protected]>

Cc Vignesh Raghavendra <[email protected]>

Signed-off-by Tony Lindgren <[email protected]>

---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 18 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)

arch/arm64/boot/dts/ti/k3-am65-main.dtsi +18 -0

@@ -130,6 +130,24 @@ rng: rng@4e10000 {
 		};
 	};
 
+	/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+	main_timerio_input: pinctrl@104200 {
+		compatible = "pinctrl-single";
+		reg = <0x0 0x104200 0x0 0x30>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x0000001ff>;
+	};
+
+	/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+	main_timerio_output: pinctrl@104280 {
+		compatible = "pinctrl-single";
+		reg = <0x0 0x104280 0x0 0x20>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x0000000f>;
+	};
+
 	main_pmx0: pinctrl@11c000 {
 		compatible = "pinctrl-single";
 		reg = <0x0 0x11c000 0x0 0x2e4>;

arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +18 -0

@@ -20,6 +20,24 @@ phy_gmii_sel: phy@4040 {
 		};
 	};
 
+	/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+	mcu_timerio_input: pinctrl@40f04200 {
+		compatible = "pinctrl-single";
+		reg = <0x0 0x40f04200 0x0 0x10>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x00000101>;
+	};
+
+	/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+	mcu_timerio_output: pinctrl@40f04280 {
+		compatible = "pinctrl-single";
+		reg = <0x0 0x40f04280 0x0 0x8>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x00000003>;
+	};
+
 	mcu_uart0: serial@40a00000 {
 		compatible = "ti,am654-uart";
 			reg = <0x00 0x40a00000 0x00 0x100>;

Signature · 1 line

2.37.1

Tony Lindgren

author

2022-08-30 07:09 UTC #2 lore raw

PATCH v2 2/2 arm64: dts: ti: k3-am65: Add general purpose timers for am65

In reply to Tony Lindgren

There are 12 general purpose timers on am65 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional four timers in the MCU domain that do not have interrupts routable for Linux.

We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module.

Compared to am64, the timer clocks are different on am65. And the MCU timers are at a different IO address. Then j72 adds more timers compared to am65 with a total of 30 timers. And the j72 clocks are different.

To avoid duplication for dtsi files, eventually we may want to consider adding timer specific shared dtsi files with the timer clocks mapped using SoC specific files in include/dt-bindings/clock. But let's get am65 timers usable first.

Cc Keerthy <[email protected]>

Cc Nishanth Menon <[email protected]>

Cc Vignesh Raghavendra <[email protected]>

Signed-off-by Tony Lindgren <[email protected]>

---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 132 +++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  |  41 +++++++
 2 files changed, 173 insertions(+)

arch/arm64/boot/dts/ti/k3-am65-main.dtsi +132 -0

@@ -271,6 +271,138 @@ main_spi4: spi@2140000 {
 		#size-cells = <0>;
 	};
 
+	main_timer0: timer@2400000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2400000 0x00 0x400>;
+		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 23 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 23 0>;
+		assigned-clock-parents = <&k3_clks 23 1>;
+		ti,timer-pwm;
+	};
+
+	main_timer1: timer@2410000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2410000 0x00 0x400>;
+		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 24 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 24 0>;
+		assigned-clock-parents = <&k3_clks 24 1>;
+		ti,timer-pwm;
+	};
+
+	main_timer2: timer@2420000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2420000 0x00 0x400>;
+		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 27 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 27 0>;
+		assigned-clock-parents = <&k3_clks 27 1>;
+		ti,timer-pwm;
+	};
+
+	main_timer3: timer@2430000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2430000 0x00 0x400>;
+		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 28 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 28 0>;
+		assigned-clock-parents = <&k3_clks 28 1>;
+		ti,timer-pwm;
+	};
+
+	main_timer4: timer@2440000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2440000 0x00 0x400>;
+		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 29 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 29 0>;
+		assigned-clock-parents = <&k3_clks 29 1>;
+		ti,timer-pwm;
+	};
+
+	main_timer5: timer@2450000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2450000 0x00 0x400>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 30 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 30 0>;
+		assigned-clock-parents = <&k3_clks 30 1>;
+		ti,timer-pwm;
+	};
+
+	main_timer6: timer@2460000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2460000 0x00 0x400>;
+		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 31 0>;
+		assigned-clocks = <&k3_clks 31 0>;
+		assigned-clock-parents = <&k3_clks 31 1>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer7: timer@2470000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2470000 0x00 0x400>;
+		interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 32 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 32 0>;
+		assigned-clock-parents = <&k3_clks 32 1>;
+		ti,timer-pwm;
+	};
+
+	main_timer8: timer@2480000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2480000 0x00 0x400>;
+		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 33 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 33 0>;
+		assigned-clock-parents = <&k3_clks 33 1>;
+		ti,timer-pwm;
+	};
+
+	main_timer9: timer@2490000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2490000 0x00 0x400>;
+		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 34 0>;
+		clock-names = "fck";
+		ti,timer-pwm;
+		assigned-clocks = <&k3_clks 34 0>;
+		assigned-clock-parents = <&k3_clks 34 1>;
+	};
+
+	main_timer10: timer@24a0000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x24a0000 0x00 0x400>;
+		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 25 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 25 0>;
+		assigned-clock-parents = <&k3_clks 25 1>;
+		ti,timer-pwm;
+	};
+
+	main_timer11: timer@24b0000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x24b0000 0x00 0x400>;
+		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 26 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 26 0>;
+		assigned-clock-parents = <&k3_clks 26 1>;
+		ti,timer-pwm;
+	};
+
 	sdhci0: mmc@4f80000 {
 		compatible = "ti,am654-sdhci-5.1";
 		reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;

arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +41 -0

47 lines not on this page · raw message

Signature · 1 line

2.37.1

Tony Lindgren

author

2022-08-31 05:05 UTC #3 lore raw

Re: [PATCH v2 2/2] arm64: dts: ti: k3-am65: Add general purpose timers for am65

Quoted 7 lines · Tony Lindgren

arch/arm64/boot/dts/ti/k3-am65-main.dtsi +0 -0
@@ -271,6 +271,138 @@ main_spi4: spi@2140000 {
 		#size-cells = <0>;
 	};
 

arch/arm64/boot/dts/ti/k3-am65-main.dtsi main_spi4: spi@2140000 { · line 283

Quoted 10 lines

arch/arm64/boot/dts/ti/k3-am65-main.dtsi +10 -0

+	main_timer0: timer@2400000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2400000 0x00 0x400>;
+		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 23 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 23 0>;
+		assigned-clock-parents = <&k3_clks 23 1>;
+		ti,timer-pwm;
+	};

Oops the power-domains are missing for the timers. This should have power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>.

Can we tag all the timers with TI_SCI_PD_EXCLUSIVE, or do some always need to be TI_SCI_PD_SHARED?

Regards,

Tony

Vignesh Raghavendra

maintainer

2022-09-01 10:37 UTC #4 lore raw

Re: [PATCH v2 2/2] arm64: dts: ti: k3-am65: Add general purpose timers for am65

Quoted 22 lines · Tony Lindgren

Quoted 7 lines · Tony Lindgren
arch/arm64/boot/dts/ti/k3-am65-main.dtsi +0 -0
@@ -271,6 +271,138 @@ main_spi4: spi@2140000 {
 		#size-cells = <0>;
 	};
 
arch/arm64/boot/dts/ti/k3-am65-main.dtsi main_spi4: spi@2140000 { · line 283
Quoted 10 lines
arch/arm64/boot/dts/ti/k3-am65-main.dtsi +10 -0
+	main_timer0: timer@2400000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2400000 0x00 0x400>;
+		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 23 0>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 23 0>;
+		assigned-clock-parents = <&k3_clks 23 1>;
+		ti,timer-pwm;
+	};
Oops the power-domains are missing for the timers. This should have power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>.

Quoted 3 lines

Can we tag all the timers with TI_SCI_PD_EXCLUSIVE, or do some always need to be TI_SCI_PD_SHARED?

Please tag TI_SCI_PD_EXCLUSIVE for main domain timers. Individual boards can override based on need basis

Signature · 2 lines

Regards
Vignesh

Tony Lindgren

author

2022-08-30 07:22 UTC #5 lore raw

In reply to Tony Lindgren

Quoted 2 lines · Tony Lindgren

Here's v2 series for adding the dmtimers for am65. The device tree binding and related driver related changes have been already merged.

FYI, something like the patch below can be used to configure the main timer0 for PWM. It uses TIMERIO0 for output, and muxes TIMERIO0 pad to a k3-am654-base-board header pin.

Just for reference only, not for merging, as the k3-am654-base-board header usage may vary.

Regards,

Tony

arch/arm64/boot/dts/ti/k3-am654-base-board.dts +22 -0

@@ -86,6 +86,14 @@ switch-6 {
 		};
 	};
 
+	main_pwm0: dmtimer-main-pwm-0 {
+		pinctrl-0 = <&main_timer0_outsel_pins_default>, <&main_timer0_pins_default>;
+		pinctrl-names = "default";
+		compatible = "ti,omap-dmtimer-pwm";
+		#pwm-cells = <3>;
+		ti,timers = <&main_timer0>;
+	};
+
 	evm_12v0: fixedregulator-evm12v0 {
 		/* main supply */
 		compatible = "regulator-fixed";

@@ -119,6 +127,13 @@ vdd_mmc1_sd: fixedregulator-sd {
 	};
 };
 
+&main_timerio_output {
+	main_timer0_outsel_pins_default: main-timer0-outsel-pins-default {
+		/* CTRLMMR_TIMERIO0_CTRL 0x00104280 OUT_SEL.TIMERIO0 */
+		pinctrl-single,pins = <0 0>;
+	};
+};
+
 &wkup_pmx0 {
 	wkup_i2c0_pins_default: wkup-i2c0-pins-default {
 		pinctrl-single,pins = <

@@ -264,6 +279,13 @@ ecap0_pins_default: ecap0-pins-default {
 			AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
 		>;
 	};
+
+	main_timer0_pins_default: main-timer0-pins-default {
+		pinctrl-single,pins = <
+			/* CTRLMMR_PADCONFIG192 0x0011c300 TIMER_IO0 */
+			AM65X_IOPAD(0x0018, PIN_OUTPUT, 0)
+		>;
+	};
 };
 
 &wkup_uart0 {

Signature · 1 line

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