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rt2x00: set SoC wmac clock register

PATCH Superseded Daniel Golle 2 participants 2 messages Sep 16, 2022 – Sep 17, 2022 Ralink RT2X00 wireless LAN driver

v1 of 3 Superseded Latest is v3 →

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Daniel Golle

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PATCH 14/15 rt2x00: set SoC wmac clock register

Instead of using the default value 33 (pci), set US_CYC_CNT init based on Programming guide:
If available, set chipset bus clock with fallback to cpu clock/3.

Reported-by Serge Vasilugin <[email protected]>
Signed-off-by Daniel Golle <[email protected]>
---
 .../net/wireless/ralink/rt2x00/rt2800lib.c    | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)
drivers/net/wireless/ralink/rt2x00/rt2800lib.c +21 -0
index cc2f9101201cec..1da51536e73802 100644
@@ -6196,6 +6196,27 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
 		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
 		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
 		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
+	} else if (rt2x00_is_soc(rt2x00dev)) {
+		struct clk *clk = clk_get_sys("bus", NULL);
+		int rate;
+
+		if (IS_ERR(clk)) {
+			clk = clk_get_sys("cpu", NULL);
+
+			if (IS_ERR(clk)) {
+				rate = 125;
+			} else {
+				rate = clk_get_rate(clk) / 3000000;
+				clk_put(clk);
+			}
+		} else {
+			rate = clk_get_rate(clk) / 1000000;
+			clk_put(clk);
+		}
+
+		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
+		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, rate);
+		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
 	}
 
 	reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
Signature · 1 line
2.37.3