arm64: dts: qcom: ipq6018: fix NAND node name

PATCH Applied Robert Marko 4 participants 7 messages Sep 27, 2022 – Oct 18, 2022

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Robert Marko

author

2022-09-27 20:13 UTC #0 lore raw

PATCH 1/2 arm64: dts: qcom: ipq6018: fix NAND node name

Per schema it should be nand-controller@79b0000 instead of nand@79b0000. Fix it to match nand-controller.yaml requirements.

Signed-off-by Robert Marko <[email protected]>

---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm64/boot/dts/qcom/ipq6018.dtsi +1 -1

index a7c7ca980a71..57978a8ab498 100644
@@ -348,7 +348,7 @@ qpic_bam: dma-controller@7984000 {
 			status = "disabled";
 		};
 
-		qpic_nand: nand@79b0000 {
+		qpic_nand: nand-controller@79b0000 {
 			compatible = "qcom,ipq6018-nand";
 			reg = <0x0 0x079b0000 0x0 0x10000>;
 			#address-cells = <1>;

Signature · 1 line

2.37.3

Robert Marko

author

2022-09-27 20:13 UTC #1 lore raw

PATCH 2/2 arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node

The ARM timer is usually considered not part of SoC node, just like other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:

arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml

Signed-off-by Robert Marko <[email protected]>

---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

arch/arm64/boot/dts/qcom/ipq6018.dtsi +8 -8

index 57978a8ab498..428e99e127c3 100644
@@ -511,14 +511,6 @@ a53pll: clock@b116000 {
 			clock-names = "xo";
 		};
 
-		timer {
-			compatible = "arm,armv8-timer";
-			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-		};
-
 		timer@b120000 {
 			#address-cells = <1>;
 			#size-cells = <1>;

@@ -770,6 +762,14 @@ dwc_0: usb@8a00000 {
 		};
 	};
 
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
 	wcss: wcss-smp2p {
 		compatible = "qcom,smp2p";
 		qcom,smem = <435>, <428>;

Signature · 1 line

2.37.3

Neil Armstrong

Reviewed-by on v1 2/2

2022-09-28 07:47 UTC #2 lore raw

Re: [PATCH 2/2] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node

Quoted 35 lines · Robert Marko

The ARM timer is usually considered not part of SoC node, just like other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml
Signed-off-by Robert Marko <[email protected]>
---
  arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++--------
  1 file changed, 8 insertions(+), 8 deletions(-)
arch/arm64/boot/dts/qcom/ipq6018.dtsi +1 -8
index 57978a8ab498..428e99e127c3 100644
@@ -511,14 +511,6 @@ a53pll: clock@b116000 {
  			clock-names = "xo";
  		};
 
-		timer {
-			compatible = "arm,armv8-timer";
-			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-		};
-
  		timer@b120000 {
  			#address-cells = <1>;
  			#size-cells = <1>;
@@ -770,6 +762,14 @@ dwc_0: usb@8a00000 {
  		};
  	};
 
+	timer {

arch/arm64/boot/dts/qcom/ipq6018.dtsi dwc_0: usb@8a00000 { · line 775

Quoted 10 lines

arch/arm64/boot/dts/qcom/ipq6018.dtsi +7 -0

+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
  	wcss: wcss-smp2p {
  		compatible = "qcom,smp2p";
  		qcom,smem = <435>, <428>;

Reviewed-by Neil Armstrong <[email protected]>

Krzysztof Kozlowski

Reviewed-by on v1 2/2

2022-09-28 08:02 UTC #3 lore raw

Re: [PATCH 2/2] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node

In reply to Robert Marko

Quoted 9 lines · Robert Marko

The ARM timer is usually considered not part of SoC node, just like other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml
Signed-off-by Robert Marko <[email protected]>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++--------

Reviewed-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

Neil Armstrong

Reviewed-by on v1 1/2

2022-09-28 07:47 UTC #4 lore raw

In reply to Robert Marko

Quoted 13 lines · Robert Marko

Per schema it should be nand-controller@79b0000 instead of nand@79b0000. Fix it to match nand-controller.yaml requirements.
Signed-off-by Robert Marko <[email protected]>
---
  arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/qcom/ipq6018.dtsi +0 -0
index a7c7ca980a71..57978a8ab498 100644

arch/arm64/boot/dts/qcom/ipq6018.dtsi qpic_bam: dma-controller@7984000 { · line 354

Quoted 8 lines

arch/arm64/boot/dts/qcom/ipq6018.dtsi +1 -1

@@ -348,7 +348,7 @@ qpic_bam: dma-controller@7984000 {
  			status = "disabled";
  		};
 
-		qpic_nand: nand@79b0000 {
+		qpic_nand: nand-controller@79b0000 {
  			compatible = "qcom,ipq6018-nand";
  			reg = <0x0 0x079b0000 0x0 0x10000>;
  			#address-cells = <1>;

Reviewed-by Neil Armstrong <[email protected]>

Krzysztof Kozlowski

Reviewed-by on v1 1/2

2022-09-28 08:03 UTC #5 lore raw

In reply to Robert Marko

Quoted 4 lines · Robert Marko

Per schema it should be nand-controller@79b0000 instead of nand@79b0000. Fix it to match nand-controller.yaml requirements.
Signed-off-by Robert Marko <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

Bjorn Andersson

maintainer Applied

2022-10-18 03:22 UTC #6 lore raw

Re: (subset) [PATCH 1/2] arm64: dts: qcom: ipq6018: fix NAND node name

In reply to Robert Marko

Quoted 4 lines · Robert Marko

Per schema it should be nand-controller@79b0000 instead of nand@79b0000. Fix it to match nand-controller.yaml requirements.

Applied, thanks!

[1/2] arm64: dts: qcom: ipq6018: fix NAND node name

      commit: 8857b0ab6a562c473c5bded0efda9390b82a84d4
[2/2] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node
      commit: feeef118fda562cf9081edef8ad464d89db070f4

Best regards,

Signature · 1 line

Bjorn Andersson <[email protected]>