SDM670 Pin Control Driver

PATCH Superseded Richard Acayan 3 participants 10 messages Oct 1, 2022 – Oct 4, 2022

Subsystems (6)

Device tree bindings Arm Qualcomm mailing list GPIO Pin control +2 more subsystems

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Richard Acayan

author

2022-10-01 21:07 UTC #0 lore raw

v6 cover SDM670 Pin Control Driver

Changes since v5:
- remove function requirement in schema
- change "-state$" regex to double quotes in schema
- drop quotes from qcom-tlmm-state ref in dt schema

Changes since v4:
- accumulate review tag
- use --cover-letter
- this is effectively a resend

Changes since v3:
- constrain gpio-reserved-ranges to 1-75 items
- proper indentation in dt-bindings example (actually tagged this time instead of an outdated commit)
- remove unnecessary commit reference
- rename complement_fw_reserved_gpios -> complement_fw_gpio_ranges

Changes since v2:
- remove quotes from pinctrl.yaml# in dt-bindings
- constrain gpio-reserved-ranges to 1-76 items (includes ufs_reset)
- indentation in dt-bindings example
- cite downstream kernel source
- remove MODULE_AUTHOR (most imported pinctrl drivers don't have this)

Changes since v1:
- add a field in msm_pinctrl_soc_data to accomodate the needs of the driver and device dts
- apply changes made to existing tlmm dt documentation
- add reserved gpios array
- rename device tree compat string to qcom,sdm670-tlmm
- remove dependency on ACPI
- move MODULE_DEVICE_TABLE macro call up
- add missing pins (fixes most of the debugfs problems)
- move qup0_pins down
- add whitespace between UFS_RESET macro and pins array

This patch series adds the driver for the Qualcomm Snapdragon 670 TLMM (Top-Level Mode Multiplexer) and introduces a new field so that SDM670- related device trees can reserve their own gpios.

Richard Acayan (3):
dt-bindings: pinctrl: qcom: add sdm670 pinctrl
pinctrl: qcom: add support for complementary reserved gpios
pinctrl: qcom: add sdm670 pinctrl

 .../bindings/pinctrl/qcom,sdm670-tlmm.yaml    |  129 ++
 drivers/pinctrl/qcom/Kconfig                  |    9 +
 drivers/pinctrl/qcom/Makefile                 |    1 +
 drivers/pinctrl/qcom/pinctrl-msm.c            |    5 +-
 drivers/pinctrl/qcom/pinctrl-msm.h            |    4 +
 drivers/pinctrl/qcom/pinctrl-sdm670.c         | 1373 +++++++++++++++++
 6 files changed, 1519 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml
 create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm670.c

Signature · 1 line

2.37.3

Richard Acayan

author

2022-10-01 21:07 UTC #1 lore raw

PATCH v6 1/3 dt-bindings: pinctrl: qcom: add sdm670 pinctrl

There is a new driver for the Snapdragon 670 TLMM (Top-Level Mode Multiplexer). Document it.

Adapted from qcom,sm6350-pinctrl.yaml.

Signed-off-by Richard Acayan <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

---
 .../bindings/pinctrl/qcom,sdm670-tlmm.yaml    | 129 ++++++++++++++++++
 1 file changed, 129 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml

Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml new file +129 -0

new file mode 100644
index 000000000000..e2f563ae6bbf
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SDM670 TLMM block
+
+maintainers:
+  - Richard Acayan <[email protected]>
+
+description: |
+  This binding describes the Top Level Mode Multiplexer (TLMM) block found
+  in the SDM670 platform.
+
+allOf:
+  - $ref: pinctrl.yaml#
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,sdm670-tlmm
+
+  reg:
+    maxItems: 1
+
+  interrupts: true
+  interrupt-controller: true
+  '#interrupt-cells': true
+  gpio-controller: true
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 75
+
+  '#gpio-cells': true
+  gpio-ranges: true
+  wakeup-parent: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+patternProperties:
+  "-state$":
+    oneOf:
+      - $ref: "#/$defs/qcom-sdm670-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-sdm670-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-sdm670-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in this
+          subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
+            - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
+                      sdc2_clk, sdc2_cmd, sdc2_data ]
+        minItems: 1
+        maxItems: 36
+
+      function:
+        description:
+          Specify the alternative function to be configured for the specified
+          pins.
+
+        enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
+                atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
+                atest_usb22, atest_usb23, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
+                cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, dbg_out, ddr_bist,
+                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
+                gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, ldo_update,
+                lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
+                mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
+                pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss, qlink_enable,
+                qlink_request, qua_mi2s, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2,
+                qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sdc4_clk,
+                sdc4_cmd, sdc4_data, sd_write, sec_mi2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2,
+                tgu_ch3, tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, tsif2_clk,
+                tsif2_data, tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
+                uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1,
+                vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data, ]
+
+
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      drive-strength: true
+      input-enable: true
+      output-high: true
+      output-low: true
+
+    required:
+      - pins
+
+    additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    pinctrl@3400000 {
+        compatible = "qcom,sdm670-tlmm";
+        reg = <0x03400000 0x300000>;
+        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        gpio-ranges = <&tlmm 0 0 151>;
+
+        qup-i2c9-state {
+            pins = "gpio6", "gpio7";
+            function = "qup9";
+        };
+    };
+...

Signature · 1 line

2.37.3

Bjorn Andersson

maintainer Reviewed-by on v6 1/3

2022-10-04 00:25 UTC #2 lore raw

Re: [PATCH v6 1/3] dt-bindings: pinctrl: qcom: add sdm670 pinctrl

Quoted 7 lines · Richard Acayan

There is a new driver for the Snapdragon 670 TLMM (Top-Level Mode Multiplexer). Document it.
Adapted from qcom,sm6350-pinctrl.yaml.
Signed-off-by Richard Acayan <[email protected]>
Reviewed-by Krzysztof Kozlowski <[email protected]>

Reviewed-by Bjorn Andersson <[email protected]>

Quoted 143 lines

---
 .../bindings/pinctrl/qcom,sdm670-tlmm.yaml    | 129 ++++++++++++++++++
 1 file changed, 129 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml

Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml new file +129 -0

new file mode 100644
index 000000000000..e2f563ae6bbf
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SDM670 TLMM block
+
+maintainers:
+  - Richard Acayan <[email protected]>
+
+description: |
+  This binding describes the Top Level Mode Multiplexer (TLMM) block found
+  in the SDM670 platform.
+
+allOf:
+  - $ref: pinctrl.yaml#
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,sdm670-tlmm
+
+  reg:
+    maxItems: 1
+
+  interrupts: true
+  interrupt-controller: true
+  '#interrupt-cells': true
+  gpio-controller: true
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 75
+
+  '#gpio-cells': true
+  gpio-ranges: true
+  wakeup-parent: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+patternProperties:
+  "-state$":
+    oneOf:
+      - $ref: "#/$defs/qcom-sdm670-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-sdm670-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-sdm670-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in this
+          subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
+            - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
+                      sdc2_clk, sdc2_cmd, sdc2_data ]
+        minItems: 1
+        maxItems: 36
+
+      function:
+        description:
+          Specify the alternative function to be configured for the specified
+          pins.
+
+        enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
+                atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
+                atest_usb22, atest_usb23, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
+                cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, dbg_out, ddr_bist,
+                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
+                gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, ldo_update,
+                lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
+                mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
+                pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss, qlink_enable,
+                qlink_request, qua_mi2s, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2,
+                qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sdc4_clk,
+                sdc4_cmd, sdc4_data, sd_write, sec_mi2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2,
+                tgu_ch3, tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, tsif2_clk,
+                tsif2_data, tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
+                uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1,
+                vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data, ]
+
+
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      drive-strength: true
+      input-enable: true
+      output-high: true
+      output-low: true
+
+    required:
+      - pins
+
+    additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    pinctrl@3400000 {
+        compatible = "qcom,sdm670-tlmm";
+        reg = <0x03400000 0x300000>;
+        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        gpio-ranges = <&tlmm 0 0 151>;
+
+        qup-i2c9-state {
+            pins = "gpio6", "gpio7";
+            function = "qup9";
+        };
+    };
+...

Signature · 1 line

2.37.3

Richard Acayan

author

2022-10-01 21:07 UTC #3 lore raw

PATCH v6 2/3 pinctrl: qcom: add support for complementary reserved gpios

In reply to Richard Acayan

The driver-provided list of reserved gpios normally overrides any valid ranges provided by the firmware (device tree and ACPI). When the driver defines dummy pingroups by itself, it should mark these as invalid but should not prevent the firmware from specifying more reserved gpios. Let pinctrl drivers indicate that the reserved gpios list complements instead of overrides other lists from firmware.

Signed-off-by Richard Acayan <[email protected]>

---
 drivers/pinctrl/qcom/pinctrl-msm.c | 5 +++--
 drivers/pinctrl/qcom/pinctrl-msm.h | 4 ++++
 2 files changed, 7 insertions(+), 2 deletions(-)

drivers/pinctrl/qcom/pinctrl-msm.c +3 -2

index a2abfe987ab1..cea1d2af8c88 100644
@@ -687,9 +687,10 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
 	const int *reserved = pctrl->soc->reserved_gpios;
 	u16 *tmp;
 
-	/* Driver provided reserved list overrides DT and ACPI */
+	/* Driver provided reserved list overrides DT and ACPI by default */
 	if (reserved) {
-		bitmap_fill(valid_mask, ngpios);
+		if (!pctrl->soc->complement_fw_gpio_ranges)
+			bitmap_fill(valid_mask, ngpios);
 		for (i = 0; reserved[i] >= 0; i++) {
 			if (i >= ngpios || reserved[i] >= ngpios) {
 				dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");

drivers/pinctrl/qcom/pinctrl-msm.h +4 -0

index dd0d949f7a9e..734fe7b2a472 100644
@@ -128,6 +128,9 @@ struct msm_gpio_wakeirq_map {
  *              function number for eGPIO and any time we see that function
  *              number used we'll treat it as a request to mux away from
  *              our TLMM towards another owner.
+ * @complement_fw_gpio_ranges: If true, the reserved gpios list from the
+ *                             driver will not override the reserved gpios
+ *                             list from the firmware.
  */
 struct msm_pinctrl_soc_data {
 	const struct pinctrl_pin_desc *pins;

@@ -146,6 +149,7 @@ struct msm_pinctrl_soc_data {
 	bool wakeirq_dual_edge_errata;
 	unsigned int gpio_func;
 	unsigned int egpio_func;
+	bool complement_fw_gpio_ranges;
 };
 
 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;

Signature · 1 line

2.37.3

Bjorn Andersson

maintainer

2022-10-04 00:17 UTC #4 lore raw

Re: [PATCH v6 2/3] pinctrl: qcom: add support for complementary reserved gpios

Quoted 18 lines · Richard Acayan

The driver-provided list of reserved gpios normally overrides any valid ranges provided by the firmware (device tree and ACPI). When the driver defines dummy pingroups by itself, it should mark these as invalid but should not prevent the firmware from specifying more reserved gpios. Let pinctrl drivers indicate that the reserved gpios list complements instead of overrides other lists from firmware.
Signed-off-by Richard Acayan <[email protected]>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 5 +++--
 drivers/pinctrl/qcom/pinctrl-msm.h | 4 ++++
 2 files changed, 7 insertions(+), 2 deletions(-)
drivers/pinctrl/qcom/pinctrl-msm.c +0 -0
index a2abfe987ab1..cea1d2af8c88 100644

drivers/pinctrl/qcom/pinctrl-msm.c static int msm_gpio_init_valid_mask(struct gpio_chip *gc, · line 692

Quoted 8 lines

drivers/pinctrl/qcom/pinctrl-msm.c +2 -2

@@ -687,9 +687,10 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
 	const int *reserved = pctrl->soc->reserved_gpios;
 	u16 *tmp;
 
-	/* Driver provided reserved list overrides DT and ACPI */
+	/* Driver provided reserved list overrides DT and ACPI by default */
 	if (reserved) {
-		bitmap_fill(valid_mask, ngpios);
+		if (!pctrl->soc->complement_fw_gpio_ranges)

reserved_gpios is only defined for ACPI drivers and afaict there's nothing in the ACPI path that would modify the valid_mask after the bitmap is being filled in gpiochip_allocate_mask().

If that's the case it seems reasonable that we can just drop the bitmap_fill() here. But perhaps I'm missing something?

Regards,
Bjorn

Quoted 29 lines

drivers/pinctrl/qcom/pinctrl-msm.c +1 -0

+			bitmap_fill(valid_mask, ngpios);
 		for (i = 0; reserved[i] >= 0; i++) {
 			if (i >= ngpios || reserved[i] >= ngpios) {
 				dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");

drivers/pinctrl/qcom/pinctrl-msm.h +4 -0

index dd0d949f7a9e..734fe7b2a472 100644
@@ -128,6 +128,9 @@ struct msm_gpio_wakeirq_map {
  *              function number for eGPIO and any time we see that function
  *              number used we'll treat it as a request to mux away from
  *              our TLMM towards another owner.
+ * @complement_fw_gpio_ranges: If true, the reserved gpios list from the
+ *                             driver will not override the reserved gpios
+ *                             list from the firmware.
  */
 struct msm_pinctrl_soc_data {
 	const struct pinctrl_pin_desc *pins;

@@ -146,6 +149,7 @@ struct msm_pinctrl_soc_data {
 	bool wakeirq_dual_edge_errata;
 	unsigned int gpio_func;
 	unsigned int egpio_func;
+	bool complement_fw_gpio_ranges;
 };
 
 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;

Signature · 1 line

2.37.3

Richard Acayan

author

2022-10-04 00:52 UTC #5 lore raw

Re: [PATCH v6 2/3] pinctrl: qcom: add support for complementary reserved gpios

Quoted 32 lines · Richard Acayan

Quoted 18 lines
The driver-provided list of reserved gpios normally overrides any valid ranges provided by the firmware (device tree and ACPI). When the driver defines dummy pingroups by itself, it should mark these as invalid but should not prevent the firmware from specifying more reserved gpios. Let pinctrl drivers indicate that the reserved gpios list complements instead of overrides other lists from firmware.
Signed-off-by Richard Acayan <[email protected]>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 5 +++--
 drivers/pinctrl/qcom/pinctrl-msm.h | 4 ++++
 2 files changed, 7 insertions(+), 2 deletions(-)
drivers/pinctrl/qcom/pinctrl-msm.c +0 -0
index a2abfe987ab1..cea1d2af8c88 100644
drivers/pinctrl/qcom/pinctrl-msm.c static int msm_gpio_init_valid_mask(struct gpio_chip *gc, · line 692
Quoted 8 lines
drivers/pinctrl/qcom/pinctrl-msm.c +2 -2
@@ -687,9 +687,10 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
 	const int *reserved = pctrl->soc->reserved_gpios;
 	u16 *tmp;
 
-	/* Driver provided reserved list overrides DT and ACPI */
+	/* Driver provided reserved list overrides DT and ACPI by default */
 	if (reserved) {
-		bitmap_fill(valid_mask, ngpios);
+		if (!pctrl->soc->complement_fw_gpio_ranges)
reserved_gpios is only defined for ACPI drivers and afaict there's nothing in the ACPI path that would modify the valid_mask after the bitmap is being filled in gpiochip_allocate_mask().

Quoted 2 lines

If that's the case it seems reasonable that we can just drop the bitmap_fill() here. But perhaps I'm missing something?

This was me trying to be as uninvasive to existing drivers as I could. I just assumed that it was important because it was there already and the comment suggested that it was what the original developer wanted.

When looking at it a bit closer, the bitmap_fill() call in gpiochip_alloc_valid_mask() wasn't present at the original commit that added this line. I'm guessing this means it's safe to remove, but just in case (for the next version):

Cc Lee Jones <[email protected]>

Quoted 33 lines

Regards,
Bjorn

Quoted 29 lines

drivers/pinctrl/qcom/pinctrl-msm.c +1 -0

+			bitmap_fill(valid_mask, ngpios);
 		for (i = 0; reserved[i] >= 0; i++) {
 			if (i >= ngpios || reserved[i] >= ngpios) {
 				dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");

drivers/pinctrl/qcom/pinctrl-msm.h +4 -0

index dd0d949f7a9e..734fe7b2a472 100644
@@ -128,6 +128,9 @@ struct msm_gpio_wakeirq_map {
  *              function number for eGPIO and any time we see that function
  *              number used we'll treat it as a request to mux away from
  *              our TLMM towards another owner.
+ * @complement_fw_gpio_ranges: If true, the reserved gpios list from the
+ *                             driver will not override the reserved gpios
+ *                             list from the firmware.
  */
 struct msm_pinctrl_soc_data {
 	const struct pinctrl_pin_desc *pins;

@@ -146,6 +149,7 @@ struct msm_pinctrl_soc_data {
 	bool wakeirq_dual_edge_errata;
 	unsigned int gpio_func;
 	unsigned int egpio_func;
+	bool complement_fw_gpio_ranges;
 };
 
 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;

Signature · 1 line

2.37.3

Richard Acayan

author

2022-10-01 21:07 UTC #6 lore raw

PATCH v6 3/3 pinctrl: qcom: add sdm670 pinctrl

In reply to Richard Acayan

The Snapdragon 670 has a Top-Level Mode Multiplexer (TLMM) for various features. Add a driver to support it.

Link https://android.googlesource.com/kernel/msm/+/de5a12173c7fa6d65bedee9ad36af55b2dbfeb36%5E%21/#F6

Link https://android.googlesource.com/kernel/msm/+/04f083156d9b9f3bfcf204c1c6da88632fbb3863%5E%21/#F22

Link https://android.googlesource.com/kernel/msm/+/54837652e3400ecc63ccc78b2193faf4f349a32e%5E%21/#F0

Link https://android.googlesource.com/kernel/msm/+/f0409b07174ceca217f8b7fd255418feff06092d%5E%21/#F0

Signed-off-by Richard Acayan <[email protected]>

---
 drivers/pinctrl/qcom/Kconfig          |    9 +
 drivers/pinctrl/qcom/Makefile         |    1 +
 drivers/pinctrl/qcom/pinctrl-sdm670.c | 1373 +++++++++++++++++++++++++
 3 files changed, 1383 insertions(+)
 create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm670.c

drivers/pinctrl/qcom/Kconfig +9 -0

index 2961b5eb8e10..62187c5597d4 100644
@@ -283,6 +283,15 @@ config PINCTRL_SDM660
 	 Qualcomm Technologies Inc TLMM block found on the Qualcomm
 	 Technologies Inc SDM660 platform.
 
+config PINCTRL_SDM670
+	tristate "Qualcomm Technologies Inc SDM670 pin controller driver"
+	depends on OF
+	depends on PINCTRL_MSM
+	help
+	 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+	 Qualcomm Technologies Inc TLMM block found on the Qualcomm
+	 Technologies Inc SDM670 platform.
+
 config PINCTRL_SDM845
 	tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
 	depends on (OF || ACPI)

drivers/pinctrl/qcom/Makefile +1 -0

index 8269a1db8794..a5c40f552e5c 100644
@@ -33,6 +33,7 @@ obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o
 obj-$(CONFIG_PINCTRL_SC8180X)	+= pinctrl-sc8180x.o
 obj-$(CONFIG_PINCTRL_SC8280XP)	+= pinctrl-sc8280xp.o
 obj-$(CONFIG_PINCTRL_SDM660)   += pinctrl-sdm660.o
+obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o
 obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
 obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
 obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o

drivers/pinctrl/qcom/pinctrl-sdm670.c new file +1373 -0

1,373 lines not on this page · raw message

Signature · 1 line

2.37.3

Bjorn Andersson

maintainer Reviewed-by on v6 3/3

2022-10-04 00:23 UTC #7 lore raw

Re: [PATCH v6 3/3] pinctrl: qcom: add sdm670 pinctrl

Quoted 8 lines · Richard Acayan

The Snapdragon 670 has a Top-Level Mode Multiplexer (TLMM) for various features. Add a driver to support it.
Link https://android.googlesource.com/kernel/msm/+/de5a12173c7fa6d65bedee9ad36af55b2dbfeb36%5E%21/#F6
Link https://android.googlesource.com/kernel/msm/+/04f083156d9b9f3bfcf204c1c6da88632fbb3863%5E%21/#F22
Link https://android.googlesource.com/kernel/msm/+/54837652e3400ecc63ccc78b2193faf4f349a32e%5E%21/#F0
Link https://android.googlesource.com/kernel/msm/+/f0409b07174ceca217f8b7fd255418feff06092d%5E%21/#F0
Signed-off-by Richard Acayan <[email protected]>

Pending the question about overriding reserved_gpios, the rest of this patch looks good.

Reviewed-by Bjorn Andersson <[email protected]>

Regards,
Bjorn

Richard Acayan

author

2022-10-04 01:00 UTC #8 lore raw

Re: [PATCH v6 3/3] pinctrl: qcom: add sdm670 pinctrl

Quoted 12 lines · Richard Acayan

Quoted 8 lines
The Snapdragon 670 has a Top-Level Mode Multiplexer (TLMM) for various features. Add a driver to support it.
Link https://android.googlesource.com/kernel/msm/+/de5a12173c7fa6d65bedee9ad36af55b2dbfeb36%5E%21/#F6
Link https://android.googlesource.com/kernel/msm/+/04f083156d9b9f3bfcf204c1c6da88632fbb3863%5E%21/#F22
Link https://android.googlesource.com/kernel/msm/+/54837652e3400ecc63ccc78b2193faf4f349a32e%5E%21/#F0
Link https://android.googlesource.com/kernel/msm/+/f0409b07174ceca217f8b7fd255418feff06092d%5E%21/#F0
Signed-off-by Richard Acayan <[email protected]>
Pending the question about overriding reserved_gpios, the rest of this patch looks good.

Except for these somewhat inconsistent lines:

	static const char * const qdss_groups[] = {
		"gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
		"gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
		"gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
		"gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
		"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
		"gpio123", "gpio124",
	};

	static const char * const phase_flag_groups[] = {
		"gpio29",
		"gpio30",
		"gpio52",
		"gpio53",
		"gpio54",
		"gpio55",
		"gpio56",
		"gpio57",
		"gpio75",
		"gpio76",
		"gpio77",
		"gpio89",
		"gpio90",
		"gpio96",
		"gpio99",
		"gpio100",
		"gpio101",
		"gpio137",
		"gpio138",
		"gpio139",
		"gpio140",
		"gpio141",
		"gpio142",
		"gpio143",
	};

It should be this, will post tomorrow:

	static const char * const phase_flag_groups[] = {
		"gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
		"gpio57", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90", "gpio96",
		"gpio99", "gpio100", "gpio101", "gpio137", "gpio138", "gpio139",
		"gpio140", "gpio141", "gpio142", "gpio143",
	};

Quoted 2 lines

Reviewed-by Bjorn Andersson <[email protected]>

Assuming this isn't invalidated by the above change.

Quoted 3 lines

Regards,
Bjorn

Linus Walleij

2022-10-03 19:16 UTC #9 lore raw

In reply to Richard Acayan

Quoted 5 lines · Richard Acayan

Changes since v5:
- remove function requirement in schema
- change "-state$" regex to double quotes in schema
- drop quotes from qcom-tlmm-state ref in dt schema

The DT bindings seem fine, I'm waiting for Bjorns review of the driver before applying.

Yours,
Linus Walleij