Add BananaPi R3
Subsystems (9)
cover Add BananaPi R3
From: Frank Wunderlich <[email protected]>
This Series adds some Nodes to mt7986 devicetree and the BananaPi R3
i included sams series for mt7986 DTS with small changes
https://patchwork.kernel.org/project/linux-mediatek/cover/[email protected]/
this series need these Patches:
- Add mt7986 i2c support
https://patchwork.kernel.org/project/linux-mediatek/cover/[email protected]/
- Add mmc-support for mt7986
https://patchwork.kernel.org/project/linux-mediatek/cover/[email protected]/
- hwrng: mediatek: add mt7986 support
https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
- pinctrl: mediatek: allow configuring uart rx/tx and rts/cts separately
https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
Frank Wunderlich (6):
dt-bindings: phy: mediatek,tphy: add support for mt7986
dt-bindings: PCI: mediatek-gen3: add support for mt7986
dt-bindings: usb: mtk-xhci: add support for mt7986
dt-bindings: arm64: dts: mediatek: add compatible for bananapi r3
arm64: dts: mt7986: add i2c node
arm64: dts: mt7986: add Bananapi R3
Sam Shih (6):
arm64: dts: mt7986: harmonize device node order
arm64: dts: mt7986: add spi related device nodes
arm64: dts: mt7986: add pcie related device nodes
arm64: dts: mt7986: add usb related device nodes
arm64: dts: mt7986: add crypto related device nodes
arm64: dts: mt7986: add mmc related device nodes
.../devicetree/bindings/arm/mediatek.yaml | 1 + .../bindings/pci/mediatek-pcie-gen3.yaml | 1 + .../bindings/phy/mediatek,tphy.yaml | 1 + .../bindings/usb/mediatek,mtk-xhci.yaml | 1 + arch/arm64/boot/dts/mediatek/Makefile | 2 + .../mediatek/mt7986a-bananapi-bpi-r3-emmc.dts | 34 + .../mediatek/mt7986a-bananapi-bpi-r3-sd.dts | 29 + .../dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi | 609 ++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 263 ++++++-- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 183 ++++++ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 83 ++- 11 files changed, 1152 insertions(+), 55 deletions(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi
Signature · 1 line
2.34.1
RFC 1/12 dt-bindings: phy: mediatek,tphy: add support for mt7986
From: Frank Wunderlich <[email protected]>
Add compatible string for mt7986.
--- Documentation/devicetree/bindings/phy/mediatek,tphy.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +1 -0
@@ -79,6 +79,7 @@ properties: - enum: - mediatek,mt2712-tphy - mediatek,mt7629-tphy + - mediatek,mt7986-tphy - mediatek,mt8183-tphy - mediatek,mt8186-tphy - mediatek,mt8192-tphy
Signature · 1 line
2.34.1
Re: [RFC v1 01/12] dt-bindings: phy: mediatek,tphy: add support for mt7986
Quoted 4 lines · Frank Wunderlich
From: Frank Wunderlich <[email protected]>
Add compatible string for mt7986.
Best regards,
Krzysztof
RFC 2/12 dt-bindings: PCI: mediatek-gen3: add support for mt7986
In reply to Frank WunderlichFrom: Frank Wunderlich <[email protected]>
Add compatible string for mt7986.
---mt7986a.dtsi misses clock-names which are now required since support of MT8192/MT8188/MT8195. This change also introduces a 6th clock which is now needed for all pcie-gen3 dts.
i do not know how to map the clocks to the names...
mediatek-pcie-gen3.yaml:
clock-names:
items:
- const: pl_250m
- const: tl_26m
- const: tl_96m
- const: tl_32k
- const: peri_26m
- enum:
- top_133m # for MT8192
- peri_mem # for MT8188/MT8195
mt7986a.dtsi:
clocks = <&infracfg CLK_INFRA_PCIE_SEL>, <&infracfg CLK_INFRA_IPCIE_CK>, <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, <&infracfg CLK_INFRA_IPCIER_CK>, <&infracfg CLK_INFRA_IPCIEB_CK>; --- Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +1 -0
@@ -51,6 +51,7 @@ properties: oneOf: - items: - enum: + - mediatek,mt7986-pcie - mediatek,mt8188-pcie - mediatek,mt8195-pcie - const: mediatek,mt8192-pcie
Signature · 1 line
2.34.1
Re: [RFC v1 02/12] dt-bindings: PCI: mediatek-gen3: add support for mt7986
Quoted 25 lines · Frank Wunderlich
From: Frank Wunderlich <[email protected]>
Add compatible string for mt7986.
Signed-off-by Frank Wunderlich <[email protected]>---
mt7986a.dtsimisses clock-names which are now required since support of MT8192/MT8188/MT8195. This change also introduces a 6th clock which is now needed for all pcie-gen3 dts.i do not know how to map the clocks to the names...
mediatek-pcie-gen3.yaml:clock-names:
items:
- const:pl_250m
- const:tl_26m
- const:tl_96m
- const:tl_32k
- const:peri_26m
- enum:
-top_133m# for MT8192
-peri_mem# for MT8188/MT8195
Quoted 7 lines
mt7986a.dtsi:clocks = <&infracfg CLK_INFRA_PCIE_SEL>, <&infracfg CLK_INFRA_IPCIE_CK>, <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, <&infracfg CLK_INFRA_IPCIER_CK>, <&infracfg CLK_INFRA_IPCIEB_CK>;
Maybe the clock is not required on mt7986?
Anyway, for the bindings:
Best regards,
Krzysztof
Aw: Re: [RFC v1 02/12] dt-bindings: PCI: mediatek-gen3: add support for mt7986
Hi,
Quoted 6 lines
Gesendet: Dienstag, 18. Oktober 2022 um 17:35 Uhr
Von: "Krzysztof Kozlowski" <[email protected]>Quoted 1 line · Frank Wunderlich
From: Frank Wunderlich <[email protected]>
Maybe the clock is not required on mt7986?
yes, mt7986 does not have all clocks currently defined in binding for gen3-pcie (currently mt8xxx)
the mapping is as followed:
CLK_INFRA_IPCIER_CK: peri_26mCLK_INFRA_IPCIEB_CK: top_133mCLK_INFRA_IPCIE_CK: pcie working clock from SoC, in MT7986 it is equal to tl_26m + tl_96m + tl_32k in MT8192CLK_INFRA_PCIE_SEL: clock mux to select source clock to CLK_INFRA_IPCIE_CK CLK_INFRA_IPCIE_PIPE_CK : pcie working clock from PHY, pl_250m
as far as i see the driver only enables the clocks in bulk (no access to the clock-names), but binding needs the names
got it solved with help from mtk (see my comment on part 7) with filling missing clocks with a fixed-clock-node. If this is the right way this binding-change is enough ;)
Quoted 3 lines
Anyway, for the bindings:
thx
regards Frank
AngeloGioacchino Del Regno
maintainerRe: [RFC v1 02/12] dt-bindings: PCI: mediatek-gen3: add support for mt7986
In reply to Frank WunderlichIl 17/10/22 12:41, Frank Wunderlich ha scritto:
Quoted 26 lines
From: Frank Wunderlich <[email protected]>
Add compatible string for mt7986.
Signed-off-by Frank Wunderlich <[email protected]>---
mt7986a.dtsimisses clock-names which are now required since support of MT8192/MT8188/MT8195. This change also introduces a 6th clock which is now needed for all pcie-gen3 dts.i do not know how to map the clocks to the names...
mediatek-pcie-gen3.yaml:clock-names:
items:
- const:pl_250m
- const:tl_26m
- const:tl_96m
- const:tl_32k
- const:peri_26m
- enum:
-top_133m# for MT8192
-peri_mem# for MT8188/MT8195
Quoted 7 lines
mt7986a.dtsi:clocks = <&infracfg CLK_INFRA_PCIE_SEL>, <&infracfg CLK_INFRA_IPCIE_CK>, <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, <&infracfg CLK_INFRA_IPCIER_CK>, <&infracfg CLK_INFRA_IPCIEB_CK>;
If this SoC has a different clock tree... then you should add bindings for this kind of clock tree.
CLK_INFRA_IPCIER_CK is *not* a peri clock: "peri" means PERICFG, which does not seem to be present in this SoC... so no, you can't assign it to "peri_26m", nor you can assign it to tl_32k, as that's not a 32KHz clock.
CLK_INFRA_PCIEB_CK can be a "top_133m" clock... as it is gating "sysaxi_sel", which is a topckgen clock.
CLK_INFRA_IPCIE_CK is your "tl_(something)" clock, as that's effectively gating "pextp_tl_ck_sel" (which is the PCIe Transaction Layer clock mux).
CLK_INFRA_IPCIE_PIPE_CK seems to be parented to "top_xtal", frequency = 40MHz, so I don't see how can this be a pl_250m? Looks like being a 40m clock and I wish we didn't have clock frequencies specified in the names, as "pl" would fit, but "pl_250m" does not.
I wonder if we can change the clock names and reflect the changes to the mt8192 devicetree (mt8195 does not have any pcie node yet), and if that would be a good idea right now.
...and I've left the first for last, because...
CLK_INFRA_PCIE_SEL: I have no datasheet for this SoC, but if you're sure that this clock is selecting the source clock to CLK_INFRA_IPCIE_CK, then the clock driver is wrong...
Right now, I see the following:
static const char *const infra_pcie_parents[] __initconst = {
"top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel"
};GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1, -1, -1),
....so if you're right, we should instead have:
GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "infra_pcie_sel", 12),
....with this meaning that adding CLK_INFRA_PCIE_SEL in devicetree is useless.
This clock tree looks a bit unclear (because again, there's no datasheet around), but that's what I understand with a rather fast look in the clock drivers and with some experience on other MTK SoCs.
Then again, if this tree is effectively incompatible with the one from MT8192 and MT8195, you should have different clock names... and just as a fast idea:
clock-names = "axi", "tl", "pl", "top";
with clocks, in order:CLK_INFRA_PCIEB_CK, CLK_INFRA_IPCIE_CK,CLK_INFRA_IPCIE_PIPE_CK, CLK_INFRA_IPCIER_CK.
...but feel free to reiterate that :-)
Hope that was helpful.
Cheers,
Angelo
Re: [RFC v1 02/12] dt-bindings: PCI: mediatek-gen3: add support for mt7986
Am 19. Oktober 2022 10:28:59 MESZ schrieb AngeloGioacchino Del Regno <[email protected]>:
Quoted 60 lines
Il 17/10/22 12:41, Frank Wunderlich ha scritto:
If this SoC has a different clock tree... then you should add bindings for this kind of clock tree.
CLK_INFRA_IPCIER_CKis *not* a peri clock: "peri" means PERICFG, which does not seem to be present in this SoC... so no, you can't assign it to "peri_26m", nor you can assign it totl_32k, as that's not a 32KHz clock.
CLK_INFRA_PCIEB_CKcan be a "top_133m" clock... as it is gating "sysaxi_sel", which is a topckgen clock.
CLK_INFRA_IPCIE_CKis your "tl_(something)" clock, as that's effectively gating "pextp_tl_ck_sel" (which is the PCIe Transaction Layer clock mux).
CLK_INFRA_IPCIE_PIPE_CKseems to be parented to "top_xtal", frequency = 40MHz, so I don't see how can this be apl_250m? Looks like being a 40m clock and I wish we didn't have clock frequencies specified in the names, as "pl" would fit, but "pl_250m" does not.
I wonder if we can change the clock names and reflect the changes to the mt8192 devicetree (mt8195 does not have any pcie node yet), and if that would be a good idea right now....and I've left the first for last, because...
CLK_INFRA_PCIE_SEL: I have no datasheet for this SoC, but if you're sure that this clock is selecting the source clock toCLK_INFRA_IPCIE_CK, then the clock driver is wrong...Right now, I see the following:
static const char *const infra_pcie_parents[] __initconst = { "top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel" };
GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "
infra_pcie_sel",infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1, -1, -1),....so if you're right, we should instead have:
GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "infra_pcie_sel", 12),....with this meaning that adding
CLK_INFRA_PCIE_SELin devicetree is useless.This clock tree looks a bit unclear (because again, there's no datasheet around), but that's what I understand with a rather fast look in the clock drivers and with some experience on other MTK SoCs.
Then again, if this tree is effectively incompatible with the one from MT8192 and MT8195, you should have different clock names... and just as a fast idea:
clock-names = "axi", "tl", "pl", "top";
with clocks, in order:
CLK_INFRA_PCIEB_CK,CLK_INFRA_IPCIE_CK,CLK_INFRA_IPCIE_PIPE_CK,CLK_INFRA_IPCIER_CK.
Quoted 5 lines
...but feel free to reiterate that :-)
Hope that was helpful.Cheers,
Angelo
Hi, thanks for digging into the clock-driver. Currently i have mapped it like this (see comment to part7)
clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
<&infracfg CLK_INFRA_IPCIE_CK>, <&clk40m>, <&clk40m>, <&infracfg CLK_INFRA_IPCIER_CK>, <&infracfg CLK_INFRA_IPCIEB_CK>; clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k", "peri_26m", "top_133m";
Mtk says it has same IP block and except missing clocks it is compatible with mt8xxx gen3 pcie driver/binding. Pcie driver only enables the clocks in bulk without names,but binding requires the names property so mapping needs to be correct.
regards Frank
RFC 3/12 dt-bindings: usb: mtk-xhci: add support for mt7986
In reply to Frank WunderlichFrom: Frank Wunderlich <[email protected]>
Add compatible string for mt7986.
--- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +1 -0
@@ -28,6 +28,7 @@ properties: - mediatek,mt7622-xhci - mediatek,mt7623-xhci - mediatek,mt7629-xhci + - mediatek,mt7986-xhci - mediatek,mt8173-xhci - mediatek,mt8183-xhci - mediatek,mt8186-xhci
Signature · 1 line
2.34.1
Re: [RFC v1 03/12] dt-bindings: usb: mtk-xhci: add support for mt7986
Quoted 4 lines · Frank Wunderlich
From: Frank Wunderlich <[email protected]>
Add compatible string for mt7986.
Best regards,
Krzysztof
RFC 4/12 dt-bindings: arm64: dts: mediatek: add compatible for bananapi r3
In reply to Frank WunderlichFrom: Frank Wunderlich <[email protected]>
Add compatible for mt7986 based BananaPi R3 SBC.
--- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/arm/mediatek.yaml +1 -0
@@ -83,6 +83,7 @@ properties: - const: mediatek,mt7629 - items: - enum: + - bananapi,bpi-r3 - mediatek,mt7986a-rfb - const: mediatek,mt7986a - items:
Signature · 1 line
2.34.1
Re: [RFC v1 04/12] dt-bindings: arm64: dts: mediatek: add compatible for bananapi r3
Quoted 5 lines · Frank Wunderlich
From: Frank Wunderlich <[email protected]>
Add compatible for mt7986 based BananaPi R3 SBC.
Signed-off-by Frank Wunderlich <[email protected]>
Best regards,
Krzysztof
RFC 5/12 arm64: dts: mt7986: harmonize device node order
In reply to Frank WunderlichFrom: Sam Shih <[email protected]>
This arrange device tree nodes in alphabetical order.
---
i modified sams patch
https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
by moving pio-node up instead of moving uarts down to ensure alphabetical order for switch-/wifi-node.
And moved uart0 and wifi in mt7986b-rfb too.
--- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 94 ++++++++++---------- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 22 ++--- 2 files changed, 58 insertions(+), 58 deletions(-)
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +47 -47
@@ -54,6 +54,53 @@ switch: switch@0 { }; }; +&pio { + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + &switch { ports { #address-cells = <1>;
@@ -121,50 +168,3 @@ &wifi { pinctrl-0 = <&wf_2g_5g_pins>; pinctrl-1 = <&wf_dbdc_pins>; }; - -&pio { - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1"; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2"; - }; - }; - - wf_2g_5g_pins: wf-2g-5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; - - wf_dbdc_pins: wf-dbdc-pins { - mux { - function = "wifi"; - groups = "wf_dbdc"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA"; - drive-strength = <4>; - }; - }; -};
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +11 -11
@@ -25,10 +25,6 @@ memory@40000000 { }; }; -&uart0 { - status = "okay"; -}; - ð { status = "okay";
@@ -99,13 +95,6 @@ fixed-link { }; }; -&wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; -}; - &pio { wf_2g_5g_pins: wf-2g-5g-pins { mux {
@@ -138,3 +127,14 @@ conf { }; }; }; + +&uart0 { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +};
Signature · 1 line
2.34.1
RFC 6/12 arm64: dts: mt7986: add spi related device nodes
In reply to Frank WunderlichFrom: Sam Shih <[email protected]>
This patch adds spi support for MT7986.
--- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 ++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++ 3 files changed, 98 insertions(+)
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +35 -0
@@ -55,6 +55,20 @@ switch: switch@0 { }; &pio { + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + uart1_pins: uart1-pins { mux { function = "uart";
@@ -101,6 +115,27 @@ conf { }; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + cs-gpios = <0>, <0>; + status = "okay"; + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + cs-gpios = <0>, <0>; + status = "okay"; +}; + &switch { ports { #address-cells = <1>;
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +28 -0
@@ -112,6 +112,34 @@ infracfg: infracfg@10001000 { #clock-cells = <1>; }; + spi0: spi@1100a000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0_CK>, + <&infracfg CLK_INFRA_SPI0_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + + spi1: spi@1100b000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100b000 0 0x100>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_SPI1_CK>, + <&infracfg CLK_INFRA_SPI1_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + topckgen: topckgen@1001b000 { compatible = "mediatek,mt7986-topckgen", "syscon"; reg = <0 0x1001B000 0 0x1000>;
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +35 -0
@@ -96,6 +96,20 @@ fixed-link { }; &pio { + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + wf_2g_5g_pins: wf-2g-5g-pins { mux { function = "wifi";
@@ -128,6 +142,27 @@ conf { }; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + cs-gpios = <0>, <0>; + status = "okay"; + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + cs-gpios = <0>, <0>; + status = "okay"; +}; + &uart0 { status = "okay"; };
Signature · 1 line
2.34.1
RFC 7/12 arm64: dts: mt7986: add pcie related device nodes
In reply to Frank WunderlichFrom: Sam Shih <[email protected]>
This patch adds PCIe support for MT7986.
---
changes compared to sams original version:
- add clock-names to pcie node
driver does bulk handling without names, but binding requires 6 clocks and not only 5 we have
--- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 17 ++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 54 ++++++++++++++++++++ 2 files changed, 71 insertions(+)
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +17 -0
@@ -54,7 +54,24 @@ switch: switch@0 { }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + &pio { + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + spi_flash_pins: spi-flash-pins { mux { function = "spi";
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +54 -0
66 lines not on this page · raw message
Signature · 1 line
2.34.1
Aw: [RFC v1 07/12] arm64: dts: mt7986: add pcie related device nodes
Hi
Quoted 8 lines
Gesendet: Montag, 17. Oktober 2022 um 12:41 Uhr
Von: "Frank Wunderlich" <[email protected]>changes compared to sams original version:
- add clock-names to pcie node
driver does bulk handling without names, but binding requires 6 clocks and not only 5 we have
i got info from mtk that i can define clocks in pcie-node like this:
clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, <&infracfg CLK_INFRA_IPCIE_CK>, <&clk40m>, <&clk40m>, <&infracfg CLK_INFRA_IPCIER_CK>, <&infracfg CLK_INFRA_IPCIEB_CK>; clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k", "peri_26m", "top_133m";
So i only need the binding change i've posted in this series and have clean dtbs_check.
if this is ok, i change it in next version.
regards Frank
Aw: [RFC v1 07/12] arm64: dts: mt7986: add pcie related device nodes
Hi,
posted dt binding series here:
https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
my dts looks now like this:
pcie: pcie@11280000 {
compatible = "mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x00 0x11280000 0x00 0x4000>;
reg-names = "pcie-mac";
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0x00 0x20000000 0x00
0x20000000 0x00 0x10000000>;
clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
<&infracfg CLK_INFRA_IPCIE_CK>,
<&infracfg CLK_INFRA_IPCIER_CK>,
<&infracfg CLK_INFRA_IPCIEB_CK>;
clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
status = "disabled";
phys = <&pcie_port PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
pcie_intc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};will post v2 soon if this is ok...
regards Frank
RFC 8/12 arm64: dts: mt7986: add usb related device nodes
In reply to Frank WunderlichFrom: Sam Shih <[email protected]>
This patch adds USB support for MT7986.
---
changes compared to sams original version:
- reorder xhci-clocks based on yaml binding
--- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 28 ++++++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 55 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 28 ++++++++++ 3 files changed, 111 insertions(+)
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +28 -0
@@ -23,6 +23,24 @@ memory@40000000 { device_type = "memory"; reg = <0 0x40000000 0 0x40000000>; }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; }; ð {
@@ -153,6 +171,12 @@ &spi1 { status = "okay"; }; +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + &switch { ports { #address-cells = <1>;
@@ -214,6 +238,10 @@ &uart2 { status = "okay"; }; +&usb_phy { + status = "okay"; +}; + &wifi { status = "okay"; pinctrl-names = "default", "dbdc";
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +55 -0
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arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +28 -0
@@ -23,6 +23,24 @@ memory@40000000 { device_type = "memory"; reg = <0 0x40000000 0 0x40000000>; }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; }; ð {
@@ -163,10 +181,20 @@ &spi1 { status = "okay"; }; +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + &uart0 { status = "okay"; }; +&usb_phy { + status = "okay"; +}; + &wifi { status = "okay"; pinctrl-names = "default", "dbdc";
Signature · 1 line
2.34.1
RFC 9/12 arm64: dts: mt7986: add crypto related device nodes
In reply to Frank WunderlichFrom: Sam Shih <[email protected]>
This patch adds crypto engine support for MT7986.
--- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 4 ++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 4 ++++ 3 files changed, 23 insertions(+)
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +4 -0
@@ -43,6 +43,10 @@ reg_5v: regulator-5v { }; }; +&crypto { + status = "okay"; +}; + ð { status = "okay";
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +15 -0
@@ -206,6 +206,21 @@ trng: trng@1020f000 { status = "disabled"; }; + crypto: crypto@10320000 { + compatible = "inside-secure,safexcel-eip97"; + reg = <0 0x10320000 0 0x40000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + clocks = <&infracfg CLK_INFRA_EIP97_CK>; + clock-names = "infra_eip97_ck"; + assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; + status = "disabled"; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7986-uart", "mediatek,mt6577-uart";
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +4 -0
@@ -43,6 +43,10 @@ reg_5v: regulator-5v { }; }; +&crypto { + status = "okay"; +}; + ð { status = "okay";
Signature · 1 line
2.34.1
RFC 10/12 arm64: dts: mt7986: add mmc related device nodes
In reply to Frank WunderlichFrom: Sam Shih <[email protected]>
This patch adds mmc support for MT7986.
--- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 85 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 17 ++++ 2 files changed, 102 insertions(+)
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +85 -0
@@ -24,6 +24,15 @@ memory@40000000 { reg = <0 0x40000000 0 0x40000000>; }; + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V";
@@ -76,6 +85,24 @@ switch: switch@0 { }; }; +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>;
@@ -87,6 +114,64 @@ &pcie_phy { }; &pio { + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + pcie_pins: pcie-pins { mux { function = "pcie";
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +17 -0
@@ -285,6 +285,23 @@ ssusb: usb@11200000 { status = "disabled"; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt7986-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11c20000 0 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_MSDC_CK>, + <&infracfg CLK_INFRA_MSDC_HCK_CK>, + <&infracfg CLK_INFRA_MSDC_66M_CK>, + <&infracfg CLK_INFRA_MSDC_133M_CK>; + clock-names = "source", "hclk", "axi_cg", "ahb_cg"; + assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, + <&topckgen CLK_TOP_EMMC_250M_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>, + <&topckgen CLK_TOP_NET1PLL_D5_D2>; + status = "disabled"; + }; + pcie: pcie@11280000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie";
Signature · 1 line
2.34.1
RFC 11/12 arm64: dts: mt7986: add i2c node
In reply to Frank WunderlichFrom: Frank Wunderlich <[email protected]>
Add i2c Node to mt7986 devicetree.
--- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +14 -0
@@ -262,6 +262,20 @@ uart2: serial@11004000 { status = "disabled"; }; + i2c0: i2c@11008000 { + compatible = "mediatek,mt7986-i2c"; + reg = <0 0x11008000 0 0x90>, + <0 0x10217080 0 0x80>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clock-div = <5>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + ssusb: usb@11200000 { compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci";
Signature · 1 line
2.34.1
RFC 12/12 arm64: dts: mt7986: add Bananapi R3
In reply to Frank WunderlichFrom: Frank Wunderlich <[email protected]>
Add support for Bananapi R3 SBC.
- SD/eMMC support (switching first 4 bits of data-bus with sw6/D)
- all rj45 ports and both SFP working (eth1/lan4)
- PCIe and all USB-Ports + SIM-Slot tested
- i2c and all uarts tested
- wifi tested
---
SPI-NAND/NOR switched (CS by sw5/C) not yet included
this is done with DT-Overlays in my tree, but i have no idea yet, how to upstream
break some lines in wifi-eeprom-data because of checkpatch warnings. originally there were 8 x int32 per line
--- arch/arm64/boot/dts/mediatek/Makefile | 2 + .../mediatek/mt7986a-bananapi-bpi-r3-emmc.dts | 34 + .../mediatek/mt7986a-bananapi-bpi-r3-sd.dts | 29 + .../dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi | 609 ++++++++++++++++++ 4 files changed, 674 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi
arch/arm64/boot/dts/mediatek/Makefile +2 -0
@@ -8,6 +8,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dts new file +34 -0
@@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih <[email protected]> + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> + +#include "mt7986a-bananapi-bpi-r3.dtsi" + +/ { + model = "Bananapi BPI-R3 (emmc)"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; +
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dts new file +29 -0
@@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih <[email protected]> + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> + +#include "mt7986a-bananapi-bpi-r3.dtsi" + +/ { + model = "Bananapi BPI-R3 (sdmmc)"; +}; + +&mmc0 { + //sdcard + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + status = "okay"; +}; +
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi new file +609 -0
609 lines not on this page · raw message
Signature · 1 line
2.34.1
Re: [RFC v1 12/12] arm64: dts: mt7986: add Bananapi R3
Quoted 9 lines · Frank Wunderlich
From: Frank Wunderlich <[email protected]>
Add support for Bananapi R3 SBC.
- SD/eMMC support (switching first 4 bits of data-bus with sw6/D)
- all rj45 ports and both SFP working (eth1/lan4)
- PCIe and all USB-Ports + SIM-Slot tested
- i2c and all uarts tested
- wifi tested
Thank you for your patch. There is something to discuss/improve.
Quoted 24 lines
Signed-off-by Frank Wunderlich <[email protected]>---
SPI-NAND/NOR switched (CS by sw5/C) not yet included
this is done with DT-Overlays in my tree, but i have no idea yet, how to upstreambreak some lines in wifi-eeprom-data because of checkpatch warnings. originally there were 8 x int32 per line
--- arch/arm64/boot/dts/mediatek/Makefile | 2 + .../mediatek/mt7986a-bananapi-bpi-r3-emmc.dts | 34 + .../mediatek/mt7986a-bananapi-bpi-r3-sd.dts | 29 + .../dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi | 609 ++++++++++++++++++ 4 files changed, 674 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsiarch/arm64/boot/dts/mediatek/Makefile +0
-0
arch/arm64/boot/dts/mediatek/Makefile dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb · line 11
Quoted 4 lines
arch/arm64/boot/dts/mediatek/Makefile +1
-0@@ -8,6 +8,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtb> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtb
Alphabetical order
Quoted 107 lines
arch/arm64/boot/dts/mediatek/Makefile +0
-0dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtbarch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dts new file +34
-0@@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih <[email protected]> + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> + +#include "mt7986a-bananapi-bpi-r3.dtsi" + +/ { + model = "Bananapi BPI-R3 (emmc)"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; +arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dts new file +29
-0@@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih <[email protected]> + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> + +#include "mt7986a-bananapi-bpi-r3.dtsi" + +/ { + model = "Bananapi BPI-R3 (sdmmc)"; +}; + +&mmc0 { + //sdcard + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + status = "okay"; +}; +arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi new file +23
-0@@ -0,0 +1,609 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Authors: Sam.Shih <[email protected]> + * Frank Wunderlich <[email protected]> + * Daniel Golle <[email protected]> + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +#include "mt7986a.dtsi" + +/ { + model = "Bananapi BPI-R3"; + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1;
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi line 33
Quoted 10 lines
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi new file +10
-0+ }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + factory {
key/button prefix
Does not look like you tested the DTS against bindings. Please run make dtbs_check (see Documentation/devicetree/bindings/writing-schema.rst for instructions).
Quoted 39 lines
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi new file +39
-0+ label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; + + /* i2c of the left SFP cage (wan) */ + i2c_sfp1: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* i2c of the right SFP cage (lan) */ + i2c_sfp2: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + green_led: led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_POWER; + gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi line 82
Quoted 10 lines
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi new file +10
-0+ default-state = "on"; + }; + + blue_led: led-1 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + gpios = <&pio 86 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + };
Blank line
Quoted 24 lines
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi new file +24
-0+ memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v {
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi line 116
Quoted 10 lines
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi new file +10
-0+ compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + /* left SFP cage (wan) */ + sfp1: sfp1 {
sfp-1
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi line 126
Quoted 10 lines
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi new file +10
-0+ compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + los-gpio = <&pio 46 GPIO_ACTIVE_HIGH>; + moddef0-gpio = <&pio 49 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&pio 20 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&pio 7 GPIO_ACTIVE_HIGH>; + }; + + /* right SFP cage (lan) */ + sfp2: sfp2 {
sfp-2
Quoted 36 lines
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi new file +36
-0+ compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; +
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi line 172
Quoted 10 lines
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi new file +10
-0+ mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>;
This does not match your unit address.
Quoted 12 lines
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi new file +12
-0+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default";
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi line 194
Quoted 10 lines
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi new file +10
-0+ pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pio { + i2c_pins: i2c-pins-3-4 {
Usually bindings expect certain suffix or prefix. Are you sure this passes dtbs_check?
Best regards,
Krzysztof