mtd: rawnand: cadence: support 64-bit slave dma interface
Subsystems (3)
PATCH v4 1/1 mtd: rawnand: cadence: support 64-bit slave dma interface
32-bit accesses on 64-bit sdma trigger sdma_err in intr_status register.
Check dma capabilities before reading/writing from/to sdma interface.
---
Changes v1 -> v2:
- Replaced ioread64_rep by cadence_nand_readsq (suggested by Arnd)
- Replaced iowrite64_rep by cadence_nand_writesq (suggested by Arnd)
- Do not try to access 64-bit sdma if __raw_readq/__raw_writeq are not defined
Changes v2 -> v3:
- Use readsq/writesq on 64-bit architectures (Arnd)
- Detect issue on init instead of 1st transfer
Changes v3 -> v4:
- Updated link and reviewed tag (Arnd)
--- .../mtd/nand/raw/cadence-nand-controller.c | 70 +++++++++++++++---- 1 file changed, 58 insertions(+), 12 deletions(-)
drivers/mtd/nand/raw/cadence-nand-controller.c +58 -12
@@ -1184,6 +1184,14 @@ static int cadence_nand_hw_init(struct cdns_nand_ctrl *cdns_ctrl)if (cadence_nand_read_bch_caps (cdns_ctrl))return -EIO ; +#ifndef CONFIG_64BIT +if (cdns_ctrl->caps2.data_dma_width ==8 ) { +dev_err (cdns_ctrl->dev, +"cannot access 64-bit dma on !64-bit architectures" ); +return -EIO ; + } +#endif +/* * Set IO width access to 8. * It is because during SW device discovering width access
@@ -1882,17 +1890,36 @@ static int cadence_nand_read_buf(struct cdns_nand_ctrl *cdns_ctrl,return status;if (!cdns_ctrl->caps1->has_dma) { -int len_in_words = len >>2 ; +u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; + +int len_in_words = (data_dma_width ==4 ) ? len >>2 : len >>3 ;/* read alingment data */ -ioread32_rep (cdns_ctrl->io.virt, buf, len_in_words); +if (data_dma_width ==4 ) +ioread32_rep (cdns_ctrl->io.virt, buf, len_in_words); +#ifdef CONFIG_64BIT + else + readsq(cdns_ctrl->io.virt, buf, len_in_words); +#endif +if (sdma_size > len) { +int read_bytes = (data_dma_width ==4 ) ? + len_in_words <<2 : len_in_words <<3 ; +/* read rest data from slave DMA interface if any */ -ioread32_rep (cdns_ctrl->io.virt, cdns_ctrl->buf, - sdma_size /4 - len_in_words); +if (data_dma_width ==4 ) +ioread32_rep (cdns_ctrl->io.virt, + cdns_ctrl->buf, + sdma_size /4 - len_in_words); +#ifdef CONFIG_64BIT + else + readsq(cdns_ctrl->io.virt, cdns_ctrl->buf, + sdma_size / 8 - len_in_words); +#endif +/* copy rest of data */ -memcpy (buf + (len_in_words <<2 ), cdns_ctrl->buf, - len - (len_in_words <<2 )); +memcpy (buf + read_bytes, cdns_ctrl->buf, + len - read_bytes); }return 0 ; }
@@ -1936,16 +1963,35 @@ static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl,return status;if (!cdns_ctrl->caps1->has_dma) { -int len_in_words = len >>2 ; +u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; + +int len_in_words = (data_dma_width ==4 ) ? len >>2 : len >>3 ; + +if (data_dma_width ==4 ) +iowrite32_rep (cdns_ctrl->io.virt, buf, len_in_words); +#ifdef CONFIG_64BIT + else + writesq(cdns_ctrl->io.virt, buf, len_in_words); +#endif -iowrite32_rep (cdns_ctrl->io.virt, buf, len_in_words);if (sdma_size > len) { +int written_bytes = (data_dma_width ==4 ) ? + len_in_words <<2 : len_in_words <<3 ; +/* copy rest of data */ -memcpy (cdns_ctrl->buf, buf + (len_in_words <<2 ), - len - (len_in_words <<2 )); +memcpy (cdns_ctrl->buf, buf + written_bytes, + len - written_bytes); +/* write all expected by nand controller data */ -iowrite32_rep (cdns_ctrl->io.virt, cdns_ctrl->buf, - sdma_size /4 - len_in_words); +if (data_dma_width ==4 ) +iowrite32_rep (cdns_ctrl->io.virt, + cdns_ctrl->buf, + sdma_size /4 - len_in_words); +#ifdef CONFIG_64BIT + else + writesq(cdns_ctrl->io.virt, cdns_ctrl->buf, + sdma_size / 8 - len_in_words); +#endif }return 0 ;
Signature · 16 lines
2.20.1 -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
Miquel Raynal
maintainerHi Valentin,
[email protected] wrote on Tue, 18 Oct 2022 11:16:31 +0200:
Quoted 5 lines
32-bit accesses on 64-bit sdma trigger
sdma_errinintr_statusregister.Check dma capabilities before reading/writing from/to sdma interface.
What happened to the link? I guess there is some security software interaction here? Should we take the one from your v3?
Quoted 115 lines
Signed-off-by Valentin Korenblit <[email protected]>Reviewed-by Arnd Bergmann <[email protected]>---
Changes v1 -> v2:
- Replacedioread64_repbycadence_nand_readsq(suggested by Arnd)
- Replacediowrite64_repbycadence_nand_writesq(suggested by Arnd)
- Do not try to access 64-bit sdma if __raw_readq/__raw_writeq are not definedChanges v2 -> v3:
- Use readsq/writesq on 64-bit architectures (Arnd)
- Detect issue on init instead of 1st transferChanges v3 -> v4:
- Updated link and reviewed tag (Arnd)--- .../mtd/nand/raw/cadence-nand-controller.c | 70 +++++++++++++++---- 1 file changed, 58 insertions(+), 12 deletions(-)drivers/mtd/nand/raw/cadence-nand-controller.c +51
-12@@ -1184,6 +1184,14 @@ static int cadence_nand_hw_init(struct cdns_nand_ctrl *cdns_ctrl)if (cadence_nand_read_bch_caps (cdns_ctrl))return -EIO ; +#ifndef CONFIG_64BIT +if (cdns_ctrl->caps2.data_dma_width ==8 ) { +dev_err (cdns_ctrl->dev, +"cannot access 64-bit dma on !64-bit architectures" ); +return -EIO ; + } +#endif +/* * Set IO width access to 8. * It is because during SW device discovering width access @@ -1882,17 +1890,36 @@ static int cadence_nand_read_buf(struct cdns_nand_ctrl *cdns_ctrl,return status;if (!cdns_ctrl->caps1->has_dma) { -int len_in_words = len >>2 ; +u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; + +int len_in_words = (data_dma_width ==4 ) ? len >>2 : len >>3 ;/* read alingment data */ -ioread32_rep (cdns_ctrl->io.virt, buf, len_in_words); +if (data_dma_width ==4 ) +ioread32_rep (cdns_ctrl->io.virt, buf, len_in_words); +#ifdef CONFIG_64BIT + else + readsq(cdns_ctrl->io.virt, buf, len_in_words); +#endif +if (sdma_size > len) { +int read_bytes = (data_dma_width ==4 ) ? + len_in_words <<2 : len_in_words <<3 ; +/* read rest data from slave DMA interface if any */ -ioread32_rep (cdns_ctrl->io.virt, cdns_ctrl->buf, - sdma_size /4 - len_in_words); +if (data_dma_width ==4 ) +ioread32_rep (cdns_ctrl->io.virt, + cdns_ctrl->buf, + sdma_size /4 - len_in_words); +#ifdef CONFIG_64BIT + else + readsq(cdns_ctrl->io.virt, cdns_ctrl->buf, + sdma_size / 8 - len_in_words); +#endif +/* copy rest of data */ -memcpy (buf + (len_in_words <<2 ), cdns_ctrl->buf, - len - (len_in_words <<2 )); +memcpy (buf + read_bytes, cdns_ctrl->buf, + len - read_bytes); }return 0 ; }@@ -1936,16 +1963,35 @@ static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl,return status;if (!cdns_ctrl->caps1->has_dma) { -int len_in_words = len >>2 ; +u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; + +int len_in_words = (data_dma_width ==4 ) ? len >>2 : len >>3 ; + +if (data_dma_width ==4 ) +iowrite32_rep (cdns_ctrl->io.virt, buf, len_in_words); +#ifdef CONFIG_64BIT + else + writesq(cdns_ctrl->io.virt, buf, len_in_words); +#endif -iowrite32_rep (cdns_ctrl->io.virt, buf, len_in_words);if (sdma_size > len) { +int written_bytes = (data_dma_width ==4 ) ? + len_in_words <<2 : len_in_words <<3 ; +/* copy rest of data */ -memcpy (cdns_ctrl->buf, buf + (len_in_words <<2 ), - len - (len_in_words <<2 )); +memcpy (cdns_ctrl->buf, buf + written_bytes, + len - written_bytes); +/* write all expected by nand controller data */ -iowrite32_rep (cdns_ctrl->io.virt, cdns_ctrl->buf, - sdma_size /4 - len_in_words); +if (data_dma_width ==4 ) + iowrite32_rep(cdns_ctrl->io.virt,
drivers/mtd/nand/raw/cadence-nand-controller.c static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl, · line 1997
Quoted 10 lines
drivers/mtd/nand/raw/cadence-nand-controller.c +7
-0+ cdns_ctrl->buf, + sdma_size / 4 - len_in_words); +#ifdef CONFIG_64BIT + else + writesq(cdns_ctrl->io.virt, cdns_ctrl->buf, + sdma_size / 8 - len_in_words); +#endif }return 0 ;
Thanks,
Miquèl
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
Hi Miquel,
Quoted 11 lines · Miquel Raynal
Hi Valentin,
[email protected] wrote on Tue, 18 Oct 2022 11:16:31 +0200:
Quoted 5 lines
32-bit accesses on 64-bit sdma trigger
sdma_errinintr_statusregister.Check dma capabilities before reading/writing from/to sdma interface.
What happened to the link? I guess there is some security software interaction here? Should we take the one from your v3?
I copy/pasted the link that I received in Arnd's email.
Maybe this is better:
https://lists.01.org/hyperkitty/list/[email protected]/thread/3NMACGIM5NDUBPXRT5RTBZON6LQE5A3B/
Do you want me to do a v5 with it?
Quoted 124 lines
Quoted 124 lines
Signed-off-by Valentin Korenblit <[email protected]>Reviewed-by Arnd Bergmann <[email protected]>---
Changes v1 -> v2:
- Replacedioread64_repbycadence_nand_readsq(suggested by Arnd)
- Replacediowrite64_repbycadence_nand_writesq(suggested by Arnd)
- Do not try to access 64-bit sdma if __raw_readq/__raw_writeq are not definedChanges v2 -> v3:
- Use readsq/writesq on 64-bit architectures (Arnd)
- Detect issue on init instead of 1st transferChanges v3 -> v4:
- Updated link and reviewed tag (Arnd)--- .../mtd/nand/raw/cadence-nand-controller.c | 70 +++++++++++++++---- 1 file changed, 58 insertions(+), 12 deletions(-)drivers/mtd/nand/raw/cadence-nand-controller.c +58
-12@@ -1184,6 +1184,14 @@ static int cadence_nand_hw_init(struct cdns_nand_ctrl *cdns_ctrl)if (cadence_nand_read_bch_caps (cdns_ctrl))return -EIO ; +#ifndef CONFIG_64BIT +if (cdns_ctrl->caps2.data_dma_width ==8 ) { +dev_err (cdns_ctrl->dev, +"cannot access 64-bit dma on !64-bit architectures" ); +return -EIO ; + } +#endif +/* * Set IO width access to 8. * It is because during SW device discovering width access @@ -1882,17 +1890,36 @@ static int cadence_nand_read_buf(struct cdns_nand_ctrl *cdns_ctrl,return status;if (!cdns_ctrl->caps1->has_dma) { -int len_in_words = len >>2 ; +u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; + +int len_in_words = (data_dma_width ==4 ) ? len >>2 : len >>3 ;/* read alingment data */ -ioread32_rep (cdns_ctrl->io.virt, buf, len_in_words); +if (data_dma_width ==4 ) +ioread32_rep (cdns_ctrl->io.virt, buf, len_in_words); +#ifdef CONFIG_64BIT + else + readsq(cdns_ctrl->io.virt, buf, len_in_words); +#endif +if (sdma_size > len) { +int read_bytes = (data_dma_width ==4 ) ? + len_in_words <<2 : len_in_words <<3 ; +/* read rest data from slave DMA interface if any */ -ioread32_rep (cdns_ctrl->io.virt, cdns_ctrl->buf, - sdma_size /4 - len_in_words); +if (data_dma_width ==4 ) +ioread32_rep (cdns_ctrl->io.virt, + cdns_ctrl->buf, + sdma_size /4 - len_in_words); +#ifdef CONFIG_64BIT + else + readsq(cdns_ctrl->io.virt, cdns_ctrl->buf, + sdma_size / 8 - len_in_words); +#endif +/* copy rest of data */ -memcpy (buf + (len_in_words <<2 ), cdns_ctrl->buf, - len - (len_in_words <<2 )); +memcpy (buf + read_bytes, cdns_ctrl->buf, + len - read_bytes); }return 0 ; }@@ -1936,16 +1963,35 @@ static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl,return status;if (!cdns_ctrl->caps1->has_dma) { -int len_in_words = len >>2 ; +u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; + +int len_in_words = (data_dma_width ==4 ) ? len >>2 : len >>3 ; + +if (data_dma_width ==4 ) +iowrite32_rep (cdns_ctrl->io.virt, buf, len_in_words); +#ifdef CONFIG_64BIT + else + writesq(cdns_ctrl->io.virt, buf, len_in_words); +#endif -iowrite32_rep (cdns_ctrl->io.virt, buf, len_in_words);if (sdma_size > len) { +int written_bytes = (data_dma_width ==4 ) ? + len_in_words <<2 : len_in_words <<3 ; +/* copy rest of data */ -memcpy (cdns_ctrl->buf, buf + (len_in_words <<2 ), - len - (len_in_words <<2 )); +memcpy (cdns_ctrl->buf, buf + written_bytes, + len - written_bytes); +/* write all expected by nand controller data */ -iowrite32_rep (cdns_ctrl->io.virt, cdns_ctrl->buf, - sdma_size /4 - len_in_words); +if (data_dma_width ==4 ) +iowrite32_rep (cdns_ctrl->io.virt, + cdns_ctrl->buf, + sdma_size /4 - len_in_words); +#ifdef CONFIG_64BIT + else + writesq(cdns_ctrl->io.virt, cdns_ctrl->buf, + sdma_size / 8 - len_in_words); +#endif }
Quoted 4 lines
drivers/mtd/nand/raw/cadence-nand-controller.c static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl, · line 1997
Quoted 1 line
drivers/mtd/nand/raw/cadence-nand-controller.c +0
-0return 0 ;Thanks,
Miquèl
Best regards,
Valentin
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The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.
Thank you.
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Quoted 6 lines · Valentin Korenblit
I copy/pasted the link that I received in Arnd's email.
Maybe this is better:
https://lists.01.org/hyperkitty/list/[email protected]/thread/3NMACGIM5NDUBPXRT5RTBZON6LQE5A3B/
To clarify: my point was about using the official 'Link:' tag in the changelog text rather than having a free-form link.
When linking to a mailing list post, the best option is usually one from lore.kernel.org. the lists.01.org link is probably fine if the thread is not archived on lore.
Arnd
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Miquel Raynal
maintainerHi Arnd, Valentin,
[email protected] wrote on Tue, 18 Oct 2022 11:23:04 +0200:
Quoted 6 lines · Valentin Korenblit
Quoted 5 lines
I copy/pasted the link that I received in Arnd's email.
Maybe this is better:
Quoted 8 lines
Quoted 1 line
https://lists.01.org/hyperkitty/list/[email protected]/thread/3NMACGIM5NDUBPXRT5RTBZON6LQE5A3B/
To clarify: my point was about using the official 'Link:' tag in the changelog text rather than having a free-form link.
When linking to a mailing list post, the best option is usually one from lore.kernel.org. the lists.01.org link is probably fine if the thread is not archived on lore.
It is:
https://lore.kernel.org/all/[email protected]/t/
Valentin, can you eventually send a v5 with this link if you agree?
Thanks,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
Miquel Raynal
maintainerHi Valentin,
[email protected] wrote on Tue, 18 Oct 2022 11:20:56 +0200:
Quoted 9 lines
Hi Miquel,
Quoted 6 lines · Miquel Raynal
Hi Valentin,
[email protected] wrote on Tue, 18 Oct 2022 11:16:31 +0200:
Quoted 2 lines
32-bit accesses on 64-bit sdma trigger
sdma_errinintr_statusregister.
Quoted 7 lines
Quoted 5 lines
Quoted 3 lines
Check dma capabilities before reading/writing from/to sdma interface.
What happened to the link? I guess there is some security software interaction here? Should we take the one from your v3?
I copy/pasted the link that I received in Arnd's email.
Actually Arnd's e-mail contains the right link, but you probably have some company software poking in your e-mails and translating external links through your cisco protection.
What Arnd probably meant was to use
rather than
Link to the discussion: xxx
because the former has been standardized.
Quoted 3 lines
Maybe this is better:
https://lists.01.org/hyperkitty/list/[email protected]/thread/3NMACGIM5NDUBPXRT5RTBZON6LQE5A3B/
Yes, this is the right link.
Quoted 2 lines
Do you want me to do a v5 with it?
I'll take care of it, thanks.
Quoted 132 lines
Quoted 115 lines
Quoted 115 lines
Signed-off-by Valentin Korenblit <[email protected]>Reviewed-by Arnd Bergmann <[email protected]>---
Changes v1 -> v2:
- Replacedioread64_repbycadence_nand_readsq(suggested by Arnd)
- Replacediowrite64_repbycadence_nand_writesq(suggested by Arnd)
- Do not try to access 64-bit sdma if __raw_readq/__raw_writeq are not definedChanges v2 -> v3:
- Use readsq/writesq on 64-bit architectures (Arnd)
- Detect issue on init instead of 1st transferChanges v3 -> v4:
- Updated link and reviewed tag (Arnd)--- .../mtd/nand/raw/cadence-nand-controller.c | 70 +++++++++++++++---- 1 file changed, 58 insertions(+), 12 deletions(-)drivers/mtd/nand/raw/cadence-nand-controller.c +54
-11@@ -1184,6 +1184,14 @@ static int cadence_nand_hw_init(struct cdns_nand_ctrl *cdns_ctrl)if (cadence_nand_read_bch_caps (cdns_ctrl))return -EIO ; >> +#ifndef CONFIG_64BIT +if (cdns_ctrl->caps2.data_dma_width ==8 ) { +dev_err (cdns_ctrl->dev, +"cannot access 64-bit dma on !64-bit architectures" ); +return -EIO ; + } +#endif +/* * Set IO width access to 8. * It is because during SW device discovering width access @@ -1882,17 +1890,36 @@ static int cadence_nand_read_buf(struct cdns_nand_ctrl *cdns_ctrl,return status; >> if (!cdns_ctrl->caps1->has_dma) { -int len_in_words = len >>2 ; +u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; + +int len_in_words = (data_dma_width ==4 ) ? len >>2 : len >>3 ; >> /* read alingment data */ -ioread32_rep (cdns_ctrl->io.virt, buf, len_in_words); +if (data_dma_width ==4 ) +ioread32_rep (cdns_ctrl->io.virt, buf, len_in_words); +#ifdef CONFIG_64BIT + else + readsq(cdns_ctrl->io.virt, buf, len_in_words); +#endif +if (sdma_size > len) { +int read_bytes = (data_dma_width ==4 ) ? + len_in_words <<2 : len_in_words <<3 ; +/* read rest data from slave DMA interface if any */ -ioread32_rep (cdns_ctrl->io.virt, cdns_ctrl->buf, - sdma_size /4 - len_in_words); +if (data_dma_width ==4 ) +ioread32_rep (cdns_ctrl->io.virt, + cdns_ctrl->buf, + sdma_size /4 - len_in_words); +#ifdef CONFIG_64BIT + else + readsq(cdns_ctrl->io.virt, cdns_ctrl->buf, + sdma_size / 8 - len_in_words); +#endif +/* copy rest of data */ -memcpy (buf + (len_in_words <<2 ), cdns_ctrl->buf, - len - (len_in_words <<2 )); +memcpy (buf + read_bytes, cdns_ctrl->buf, + len - read_bytes); }return 0 ; }@@ -1936,16 +1963,35 @@ static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl,return status; >> if (!cdns_ctrl->caps1->has_dma) { -int len_in_words = len >>2 ; +u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; + +int len_in_words = (data_dma_width ==4 ) ? len >>2 : len >>3 ; + +if (data_dma_width ==4 ) +iowrite32_rep (cdns_ctrl->io.virt, buf, len_in_words); +#ifdef CONFIG_64BIT + else + writesq(cdns_ctrl->io.virt, buf, len_in_words); +#endif >> - iowrite32_rep(cdns_ctrl->io.virt, buf, len_in_words);if (sdma_size > len) { +int written_bytes = (data_dma_width ==4 ) ? + len_in_words <<2 : len_in_words <<3 ; +/* copy rest of data */ -memcpy (cdns_ctrl->buf, buf + (len_in_words <<2 ), - len - (len_in_words <<2 )); +memcpy (cdns_ctrl->buf, buf + written_bytes, + len - written_bytes); +/* write all expected by nand controller data */ -iowrite32_rep (cdns_ctrl->io.virt, cdns_ctrl->buf, - sdma_size /4 - len_in_words); +if (data_dma_width ==4 ) +iowrite32_rep (cdns_ctrl->io.virt, + cdns_ctrl->buf, + sdma_size /4 - len_in_words); +#ifdef CONFIG_64BIT + elseQuoted 8 lines
drivers/mtd/nand/raw/cadence-nand-controller.c static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl,
Quoted 5 lines
drivers/mtd/nand/raw/cadence-nand-controller.c +3
-0+writesq (cdns_ctrl->io.virt, cdns_ctrl->buf, + sdma_size /8 - len_in_words); +#endif } >> return 0;Thanks,
MiquèlBest regards,
Valentin
-- IMPORTANT NOTICE:
Quoted 5 lines
The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.
Thank you.
Thanks,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/