Enable ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP & fixup race condition on PG_dcache_clean

From: Guo Ren <[email protected]>

The first patch fixup race condition on PG_dcache_clean which found in arm64. Then enable ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP and tested with simple hugetlbfs test case.

# cat /proc/sys/vm/hugetlb_optimize_vmemmap
1
# echo 8 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages
# mount -t hugetlbfs none test/ -o pagesize=2048k
# ./myhugemap_test
# umount test/
# echo 0 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages

No problem found.

Guo Ren (2):
riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte
riscv: Enable ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP

 arch/riscv/Kconfig                  | 1 +
 arch/riscv/include/asm/cacheflush.h | 3 +++
 arch/riscv/mm/cacheflush.c          | 7 ++++++-
 3 files changed, 10 insertions(+), 1 deletion(-)

2.36.1

From: Guo Ren <[email protected]>

RISC-V follows the arm64 flush_icache_pte mechanism and also includes its bug. The patch ensures that instructions are observable in a new mapping. For more details, see 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean in __sync_icache_dcache()").

---
 arch/riscv/mm/cacheflush.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

index 6cb7d96ad9c7..7c9f97fa3938 100644
@@ -82,7 +82,9 @@ void flush_icache_pte(pte_t pte)
 {
 	struct page *page = pte_page(pte);
 
-	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+	if (!test_bit(PG_dcache_clean, &page->flags)) {
 		flush_icache_all();
+		set_bit(PG_dcache_clean, &page->flags);
+	}
 }
 #endif /* CONFIG_MMU */

2.36.1

From: Guo Ren <[email protected]>

This patch enable the feature of "free some vmemmap pages of HugeTLB page" [1]. To make it work correct, we also need fixup PG_dcache_clean setting for huge page [2].

[1] https://lore.kernel.org/linux-doc/[email protected]/
[2] https://lore.kernel.org/linux-mm/[email protected]/

---
 arch/riscv/Kconfig                  | 1 +
 arch/riscv/include/asm/cacheflush.h | 3 +++
 arch/riscv/mm/cacheflush.c          | 3 +++
 3 files changed, 7 insertions(+)

index 6b48a3ae9843..81ac25b0e005 100644
@@ -45,6 +45,7 @@ config RISCV
 	select ARCH_WANT_FRAME_POINTERS
 	select ARCH_WANT_GENERAL_HUGETLB
 	select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
+	select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
 	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
 	select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU
 	select BUILDTIME_TABLE_SORT if MMU

index 8a5c246b0a21..96f7381aeeeb 100644
@@ -17,6 +17,9 @@ static inline void local_flush_icache_all(void)
 
 static inline void flush_dcache_page(struct page *page)
 {
+	if (PageHuge(page))
+		page = compound_head(page);
+
 	if (test_bit(PG_dcache_clean, &page->flags))
 		clear_bit(PG_dcache_clean, &page->flags);
 }

index 7c9f97fa3938..ca35807cf185 100644
@@ -82,6 +82,9 @@ void flush_icache_pte(pte_t pte)
 {
 	struct page *page = pte_page(pte);
 
+	if (PageHuge(page))
+		page = compound_head(page);
+
 	if (!test_bit(PG_dcache_clean, &page->flags)) {
 		flush_icache_all();
 		set_bit(PG_dcache_clean, &page->flags);

2.36.1

We have a new name “HVO" to refer to this feature. So I’d like to rewrite The changelog to something like “Enable HVO [1] for RISCV”.

I’am really glad to see more and more arches for support HVO.

Thanks.

Okay.

Thx

Best Regards
 Guo Ren