perf/x86/intel: Fix pebs event constraints for ICL
Subsystems (3)
PATCH 1/2 perf/x86/intel: Fix pebs event constraints for ICL
From: Kan Liang <[email protected]>
According to the latest event list, update the MEM_INST_RETIRED events which support the DataLA facility.
Fixes 6017608936c1 ("perf/x86/intel: Add Icelake support")
Reported-by Jannis Klinkenberg <[email protected]>
Signed-off-by Kan Liang <[email protected]>
--- arch/x86/events/intel/ds.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
arch/x86/events/intel/ds.c +7 -2
@@ -982,8 +982,13 @@ struct event_constraint intel_icl_pebs_event_constraints[] = {INTEL_FLAGS_UEVENT_CONSTRAINT (0x0400 ,0x800000000ULL ),/* SLOTS */ INTEL_PLD_CONSTRAINT (0x1cd ,0xff ),/* MEM_TRANS_RETIRED.LOAD_LATENCY */ -INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x1d0 ,0xf ),/* MEM_INST_RETIRED.LOAD */ -INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x2d0 ,0xf ),/* MEM_INST_RETIRED.STORE */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x11d0 ,0xf ),/* MEM_INST_RETIRED.STLB_MISS_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x12d0 ,0xf ),/* MEM_INST_RETIRED.STLB_MISS_STORES */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x21d0 ,0xf ),/* MEM_INST_RETIRED.LOCK_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x41d0 ,0xf ),/* MEM_INST_RETIRED.SPLIT_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x42d0 ,0xf ),/* MEM_INST_RETIRED.SPLIT_STORES */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x81d0 ,0xf ),/* MEM_INST_RETIRED.ALL_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x82d0 ,0xf ),/* MEM_INST_RETIRED.ALL_STORES */ INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), /* MEM_LOAD_*_RETIRED.* */
Signature · 1 line
2.35.1
PATCH 2/2 perf/x86/intel: Fix pebs event constraints for SPR
From: Kan Liang <[email protected]>
According to the latest event list, update the MEM_INST_RETIRED events which support the DataLA facility for SPR.
Fixes 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by Kan Liang <[email protected]>
--- arch/x86/events/intel/ds.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
arch/x86/events/intel/ds.c +7 -2
@@ -1009,8 +1009,13 @@ struct event_constraint intel_spr_pebs_event_constraints[] = {INTEL_FLAGS_EVENT_CONSTRAINT (0xc0 ,0xfe ),INTEL_PLD_CONSTRAINT (0x1cd ,0xfe ),INTEL_PSD_CONSTRAINT (0x2cd ,0x1 ), -INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x1d0 ,0xf ), -INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x2d0 ,0xf ), +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x11d0 ,0xf ),/* MEM_INST_RETIRED.STLB_MISS_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x12d0 ,0xf ),/* MEM_INST_RETIRED.STLB_MISS_STORES */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x21d0 ,0xf ),/* MEM_INST_RETIRED.LOCK_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x41d0 ,0xf ),/* MEM_INST_RETIRED.SPLIT_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x42d0 ,0xf ),/* MEM_INST_RETIRED.SPLIT_STORES */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x81d0 ,0xf ),/* MEM_INST_RETIRED.ALL_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x82d0 ,0xf ),/* MEM_INST_RETIRED.ALL_STORES */ INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
Signature · 1 line
2.35.1
[tip: perf/urgent] perf/x86/intel: Fix pebs event constraints for SPR
The following commit has been merged into the perf/urgent branch of tip:
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 0916886bb978e7eae1ca3955ba07f51c020da20c Gitweb: https://git.kernel.org/tip/0916886bb978e7eae1ca3955ba07f51c020da20c Author: Kan Liang <[email protected]> AuthorDate: Mon, 31 Oct 2022 08:41:19 -07:00 Committer: Peter Zijlstra <[email protected]> CommitterDate: Wed, 02 Nov 2022 12:22:06 +01:00
perf/x86/intel: Fix pebs event constraints for SPR
According to the latest event list, update the MEM_INST_RETIRED events which support the DataLA facility for SPR.
Fixes 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by Kan Liang <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
--- arch/x86/events/intel/ds.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
arch/x86/events/intel/ds.c +7 -2
@@ -1009,8 +1009,13 @@ struct event_constraint intel_spr_pebs_event_constraints[] = {INTEL_FLAGS_EVENT_CONSTRAINT (0xc0 ,0xfe ),INTEL_PLD_CONSTRAINT (0x1cd ,0xfe ),INTEL_PSD_CONSTRAINT (0x2cd ,0x1 ), -INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x1d0 ,0xf ), -INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x2d0 ,0xf ), +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x11d0 ,0xf ),/* MEM_INST_RETIRED.STLB_MISS_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x12d0 ,0xf ),/* MEM_INST_RETIRED.STLB_MISS_STORES */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x21d0 ,0xf ),/* MEM_INST_RETIRED.LOCK_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x41d0 ,0xf ),/* MEM_INST_RETIRED.SPLIT_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x42d0 ,0xf ),/* MEM_INST_RETIRED.SPLIT_STORES */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x81d0 ,0xf ),/* MEM_INST_RETIRED.ALL_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x82d0 ,0xf ),/* MEM_INST_RETIRED.ALL_STORES */ INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
The following commit has been merged into the perf/urgent branch of tip:
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: acc5568b90c19ac6375508a93b9676cd18a92a35 Gitweb: https://git.kernel.org/tip/acc5568b90c19ac6375508a93b9676cd18a92a35 Author: Kan Liang <[email protected]> AuthorDate: Mon, 31 Oct 2022 08:41:18 -07:00 Committer: Peter Zijlstra <[email protected]> CommitterDate: Wed, 02 Nov 2022 12:22:06 +01:00
perf/x86/intel: Fix pebs event constraints for ICL
According to the latest event list, update the MEM_INST_RETIRED events which support the DataLA facility.
Fixes 6017608936c1 ("perf/x86/intel: Add Icelake support")
Reported-by Jannis Klinkenberg <[email protected]>
Signed-off-by Kan Liang <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
--- arch/x86/events/intel/ds.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
arch/x86/events/intel/ds.c +7 -2
@@ -982,8 +982,13 @@ struct event_constraint intel_icl_pebs_event_constraints[] = {INTEL_FLAGS_UEVENT_CONSTRAINT (0x0400 ,0x800000000ULL ),/* SLOTS */ INTEL_PLD_CONSTRAINT (0x1cd ,0xff ),/* MEM_TRANS_RETIRED.LOAD_LATENCY */ -INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x1d0 ,0xf ),/* MEM_INST_RETIRED.LOAD */ -INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x2d0 ,0xf ),/* MEM_INST_RETIRED.STORE */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x11d0 ,0xf ),/* MEM_INST_RETIRED.STLB_MISS_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x12d0 ,0xf ),/* MEM_INST_RETIRED.STLB_MISS_STORES */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x21d0 ,0xf ),/* MEM_INST_RETIRED.LOCK_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x41d0 ,0xf ),/* MEM_INST_RETIRED.SPLIT_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x42d0 ,0xf ),/* MEM_INST_RETIRED.SPLIT_STORES */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x81d0 ,0xf ),/* MEM_INST_RETIRED.ALL_LOADS */ +INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST (0x82d0 ,0xf ),/* MEM_INST_RETIRED.ALL_STORES */ INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), /* MEM_LOAD_*_RETIRED.* */