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clk: qcom: reset: support resetting multiple bits

PATCH Applied Robert Marko 3 participants 5 messages Nov 7, 2022 – Dec 2, 2022

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Robert Marko

author
#0 lore raw

PATCH 1/3 clk: qcom: reset: support resetting multiple bits

This patch adds the support for giving the complete bitmask in reset structure and reset operation will use this bitmask for all reset operations.

Currently, reset structure only takes a single bit for each reset and then calculates the bitmask by using the BIT() macro.

However, this is not sufficient anymore for newer SoC-s like IPQ8074, IPQ6018 and more, since their networking resets require multiple bits to be asserted in order to properly reset the HW block completely.

So, in order to allow asserting multiple bits add "bitmask" field to qcom_reset_map, and then use that bitmask value if its populated in the driver, if its not populated, then we just default to existing behaviour and calculate the bitmask on the fly.

Signed-off-by Robert Marko <[email protected]>
---
 drivers/clk/qcom/reset.c | 4 ++--
 drivers/clk/qcom/reset.h | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)
drivers/clk/qcom/reset.c +2 -2
index 2a16adb572d2..0e914ec7aeae 100644
@@ -30,7 +30,7 @@ qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
 
 	rst = to_qcom_reset_controller(rcdev);
 	map = &rst->reset_map[id];
-	mask = BIT(map->bit);
+	mask = map->bitmask ? map->bitmask : BIT(map->bit);
 
 	return regmap_update_bits(rst->regmap, map->reg, mask, mask);
 }

@@ -44,7 +44,7 @@ qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
 
 	rst = to_qcom_reset_controller(rcdev);
 	map = &rst->reset_map[id];
-	mask = BIT(map->bit);
+	mask = map->bitmask ? map->bitmask : BIT(map->bit);
 
 	return regmap_update_bits(rst->regmap, map->reg, mask, 0);
 }
drivers/clk/qcom/reset.h +1 -0
index b8c113582072..9a47c838d9b1 100644
@@ -12,6 +12,7 @@ struct qcom_reset_map {
 	unsigned int reg;
 	u8 bit;
 	u8 udelay;
+	u32 bitmask;
 };
 
 struct regmap;
Signature · 1 line
2.38.1
author
#1 lore raw

PATCH 2/3 dt-bindings: clock: qcom: ipq8074: add missing networking resets

Add bindings for the missing networking resets found in IPQ8074 GCC.

Signed-off-by Robert Marko <[email protected]>
---
 include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
include/dt-bindings/clock/qcom,gcc-ipq8074.h +14 -0
index e4991d303708..f9ea55811104 100644
@@ -367,6 +367,20 @@
 #define GCC_PCIE1_AHB_ARES			129
 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES	130
 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES		131
+#define GCC_PPE_FULL_RESET			132
+#define GCC_UNIPHY0_SOFT_RESET			133
+#define GCC_UNIPHY0_XPCS_RESET			134
+#define GCC_UNIPHY1_SOFT_RESET			135
+#define GCC_UNIPHY1_XPCS_RESET			136
+#define GCC_UNIPHY2_SOFT_RESET			137
+#define GCC_UNIPHY2_XPCS_RESET			138
+#define GCC_EDMA_HW_RESET			139
+#define GCC_NSSPORT1_RESET			140
+#define GCC_NSSPORT2_RESET			141
+#define GCC_NSSPORT3_RESET			142
+#define GCC_NSSPORT4_RESET			143
+#define GCC_NSSPORT5_RESET			144
+#define GCC_NSSPORT6_RESET			145
 
 #define USB0_GDSC				0
 #define USB1_GDSC				1
Signature · 1 line
2.38.1
author
#3 lore raw

PATCH 3/3 clk: qcom: ipq8074: add missing networking resets

In reply to Robert Marko

Downstream QCA 5.4 kernel defines networking resets which are not present in the mainline kernel but are required for the networking drivers.

So, port the downstream resets and avoid using magic values for mask, construct mask for resets which require multiple bits to be set/cleared.

Signed-off-by Robert Marko <[email protected]>
---
 drivers/clk/qcom/gcc-ipq8074.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
drivers/clk/qcom/gcc-ipq8074.c +14 -0
index 42d185fe19c8..37d8a9f4105e 100644
@@ -4826,6 +4826,20 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = {
 	[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
 	[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
 	[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
+	[GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
+	[GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
+	[GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
+	[GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
+	[GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
+	[GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
+	[GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
+	[GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
+	[GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
+	[GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
+	[GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
+	[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
+	[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
+	[GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
 };
 
 static struct gdsc *gcc_ipq8074_gdscs[] = {
Signature · 1 line
2.38.1
maintainer Applied
#4 lore raw

Re: (subset) [PATCH 1/3] clk: qcom: reset: support resetting multiple bits

In reply to Robert Marko
Quoted 8 lines · Robert Marko

This patch adds the support for giving the complete bitmask in reset structure and reset operation will use this bitmask for all reset operations.

Currently, reset structure only takes a single bit for each reset and then calculates the bitmask by using the BIT() macro.

[...]

Applied, thanks!

[1/3] clk: qcom: reset: support resetting multiple bits

      commit: 4a5210893625f89723ea210d7c630b730abb37ad
[2/3] dt-bindings: clock: qcom: ipq8074: add missing networking resets
      commit: bb524058eb5635ee6ecbe3ef154d44088f7a2154
[3/3] clk: qcom: ipq8074: add missing networking resets
      commit: ce520e312918bc8f02d1c6bd58b288c2eb2d23c0

Best regards,

Signature · 1 line
Bjorn Andersson <[email protected]>