arm64: dts: rockchip: Fix gmac phy mode to rgmii on Rock 3A sbc
Subsystems (2)
PATCH 1/3 arm64: dts: rockchip: Fix gmac phy mode to rgmii on Rock 3A sbc
On rk356x ethernet phy support reduced media independent interface (RMII) and reduced gigabit media independent interface (RGMII).
So set the phy mode to rgmii.
--- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +1 -1
@@ -253,7 +253,7 @@ &gmac1 { assigned-clock-rates = <0>, <125000000>; clock_in_out = "output"; phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&gmac1m1_miim &gmac1m1_tx_bus2
Signature · 1 line
2.38.1
PATCH 2/3 arm64: dts: rockchip: Add support of external clock to ethernet node on Rock 3A sbc
Add support of external clock gmac1_clkin which is used as input clock to ethernet node.
--- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +10 -3
@@ -32,6 +32,13 @@ hdmi_con_in: endpoint { }; }; + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + leds { compatible = "gpio-leds";
@@ -249,9 +256,8 @@ &cpu3 { &gmac1 { assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + clock_in_out = "input"; phy-handle = <&rgmii_phy1>; phy-mode = "rgmii"; pinctrl-names = "default";
@@ -259,6 +265,7 @@ &gmac1 { &gmac1m1_tx_bus2 &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk + &gmac1m1_clkinout &gmac1m1_rgmii_bus>; status = "okay"; };
Signature · 1 line
2.38.1
PATCH 3/3 arm64: dts: rockchip: Fix ethernet reset node Rock 3A sbc
In reply to Anand MoonAdd support for snps,reset-gpio reset ethernet gpio pins and drop the mdio reset code.
--- .../boot/dts/rockchip/rk3568-rock-3a.dts | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-)
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +8 -11
@@ -258,6 +258,11 @@ &gmac1 { assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; clock_in_out = "input"; + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + phy-supply = <&vcc_3v3>; phy-handle = <&rgmii_phy1>; phy-mode = "rgmii"; pinctrl-names = "default";
@@ -267,6 +272,9 @@ &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk &gmac1m1_clkinout &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; status = "okay"; };
@@ -583,11 +591,6 @@ &mdio1 { rgmii_phy1: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; }; };
@@ -625,12 +628,6 @@ vcc_mipi_en: vcc_mipi_en { }; }; - ethernet { - eth_phy_rst: eth_phy_rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
Signature · 1 line
2.38.1
Re: [linux-next-v1 3/3] arm64: dts: rockchip: Fix ethernet reset node Rock 3A sbc
Hi Anand,
Quoted 2 lines · Anand Moon
Add support for snps,reset-gpio reset ethernet gpio pins and drop the mdio reset code.
But why? Is it preferred that the MAC driver performs the reset? Or what does this change fix?
Quoted 22 lines
Signed-off-by Anand Moon <[email protected]>--- .../boot/dts/rockchip/rk3568-rock-3a.dts | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-)arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +5
-0@@ -258,6 +258,11 @@ &gmac1 { assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; clock_in_out = "input"; + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + phy-supply = <&vcc_3v3>; phy-handle = <&rgmii_phy1>; phy-mode = "rgmii"; pinctrl-names = "default";
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts &gmac1m1_rx_bus2 · line 277
Quoted 6 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +3
-0@@ -267,6 +272,9 @@ &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk &gmac1m1_clkinout &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>;
Ah, here they are. I would say these delays should be added in patch 1/3 along a comment why the rgmii-id approach does not work.
Quoted 16 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +0
-5status = "okay"; };@@ -583,11 +591,6 @@ &mdio1 { rgmii_phy1: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; }; };
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts vcc_mipi_en: vcc_mipi_en { · line 632
Quoted 8 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +0
-5@@ -625,12 +628,6 @@ vcc_mipi_en: vcc_mipi_en { }; }; - ethernet { - eth_phy_rst: eth_phy_rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - };
I would assume the pinctrl is still required no matter whether the MAC driver or the PHY driver asserts the GPIO reset.
Best regards,
Michael
Quoted 4 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +0
-1- hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
Peter Geis
NAKRe: [linux-next-v1 3/3] arm64: dts: rockchip: Fix ethernet reset node Rock 3A sbc
In reply to Anand MoonQuoted 3 lines · Anand Moon
Add support for snps,reset-gpio reset ethernet gpio pins and drop the mdio reset code.
Nack, the snps,reset-gpio is depreciated in favor of the mdio-reset code. See [0].
Quoted 11 lines
Signed-off-by Anand Moon <[email protected]>--- .../boot/dts/rockchip/rk3568-rock-3a.dts | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-)arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +0
-0
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts &gmac1 { · line 265
Quoted 8 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +5
-0@@ -258,6 +258,11 @@ &gmac1 { assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; clock_in_out = "input"; + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + phy-supply = <&vcc_3v3>;
The phy supply shouldn't be part of this patch.
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts &gmac1m1_rx_bus2 · line 277
Quoted 10 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +3
-0phy-handle = <&rgmii_phy1>; phy-mode = "rgmii"; pinctrl-names = "default";@@ -267,6 +272,9 @@ &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk &gmac1m1_clkinout &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>;
Delays should move to your rgmii patch. Have you tested these to ensure they are in the middle of the functional range for this board?
Quoted 29 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +0
-12status = "okay"; };@@ -583,11 +591,6 @@ &mdio1 { rgmii_phy1: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; }; };@@ -625,12 +628,6 @@ vcc_mipi_en: vcc_mipi_en { }; }; - ethernet { - eth_phy_rst: eth_phy_rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; --
Quoted 2 lines
2.38.1
Quoted 5 lines
_______________________________________________
Linux-rockchip mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-rockchip
Re: [linux-next-v1 3/3] arm64: dts: rockchip: Fix ethernet reset node Rock 3A sbc
Hi Peter / Michael
Quoted 9 lines · Peter Geis
Quoted 3 lines · Anand Moon
Add support for snps,reset-gpio reset ethernet gpio pins and drop the mdio reset code.
Nack, the snps,reset-gpio is depreciated in favor of the mdio-reset code. See [0].
Ok coming to the ethernet reset controller with gpio-reset with MDIO. I got this working by adding ethernet-phy-id to MDIO.
Quoted 6 lines
Quoted 6 lines
Signed-off-by Anand Moon <[email protected]>--- .../boot/dts/rockchip/rk3568-rock-3a.dts | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-)
Quoted 16 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts &gmac1 { · line 265
Quoted 13 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +5
-0@@ -258,6 +258,11 @@ &gmac1 { assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; clock_in_out = "input"; + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + phy-supply = <&vcc_3v3>;The phy supply shouldn't be part of this patch.
Ok will add this in a separate patch.
Quoted 5 lines
Quoted 5 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +0
-0phy-handle = <&rgmii_phy1>; phy-mode = "rgmii"; pinctrl-names = "default";@@ -267,6 +272,9 @@ &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk
Quoted 8 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts &gmac1m1_rx_bus2 · line 277
Quoted 5 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +3
-0&gmac1m1_clkinout &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>;Delays should move to your rgmii patch. Have you tested these to ensure they are in the middle of the functional range for this board?
Ok but this delay is different from the actual requirements see below.
rx-internal-delay-ps and tx-internal-delay-ps
[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/net/ethernet-controller.yaml?h=v6.1-rc5#n222
tx_delay and rx_dealy are used by rockchip binding.
Quoted 20 lines
Quoted 20 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +0
-5status = "okay"; };@@ -583,11 +591,6 @@ &mdio1 { rgmii_phy1: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; }; };@@ -625,12 +628,6 @@ vcc_mipi_en: vcc_mipi_en { }; };
Quoted 14 lines
Quoted 10 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +0
-7- ethernet { - eth_phy_rst: eth_phy_rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; --Quoted 2 lines
2.38.1
Quoted 1 line
Thanks
-Anand
Quoted 4 lines
Quoted 4 lines
_______________________________________________
Linux-rockchip mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-rockchip
Hi Anand,
Quoted 14 lines · Anand Moon
On rk356x ethernet phy support reduced media independent interface (RMII) and reduced gigabit media independent interface (RGMII).
So set the phy mode to rgmii.Signed-off-by Anand Moon <[email protected]>--- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +0
-0
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts &gmac1 { · line 256
Quoted 5 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +1
-1@@ -253,7 +253,7 @@ &gmac1 { assigned-clock-rates = <0>, <125000000>; clock_in_out = "output"; phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii";
What are you trying to fix here? If it ain't broken, don't fix it. I would assume if you switch from rgmii-id to rgmii you need to adjust the rx/tx-delays, otherwise this change does not make sense to me. Feel free to point out what I am missing, though.
Best regards,
Michael
Quoted 3 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +0
-0pinctrl-names = "default"; pinctrl-0 = <&gmac1m1_miim &gmac1m1_tx_bus2
Quoted 4 lines · Anand Moon
On rk356x ethernet phy support reduced media independent interface (RMII) and reduced gigabit media independent interface (RGMII).
So set the phy mode to rgmii.
The RTL8211 supports rgmii-id just fine, you only need to go to rgmii on these boards if you need to tune the delays manually.
Quoted 11 lines
Signed-off-by Anand Moon <[email protected]>--- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +0
-0
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts &gmac1 { · line 256
Quoted 5 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +1
-1@@ -253,7 +253,7 @@ &gmac1 { assigned-clock-rates = <0>, <125000000>; clock_in_out = "output"; phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii";
You should be setting the delay tuning in this patch as well.
Quoted 11 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +0
-1pinctrl-names = "default"; pinctrl-0 = <&gmac1m1_miim &gmac1m1_tx_bus2 --2.38.1
_______________________________________________
Linux-rockchip mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-rockchip
Hi Petter / Michael.
Thanks for your review comments.
Quoted 9 lines · Peter Geis
Quoted 4 lines · Anand Moon
On rk356x ethernet phy support reduced media independent interface (RMII) and reduced gigabit media independent interface (RGMII).
So set the phy mode to rgmii.The RTL8211 supports rgmii-id just fine, you only need to go to rgmii on these boards if you need to tune the delays manually.
Ok rgmii supports internal rx and tx clock delay whereas rgmii-id does not supports internal clock delay.
Quoted 7 lines
Quoted 7 lines
Signed-off-by Anand Moon <[email protected]>--- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Quoted 12 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts &gmac1 { · line 256
Quoted 10 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +1
-1@@ -253,7 +253,7 @@ &gmac1 { assigned-clock-rates = <0>, <125000000>; clock_in_out = "output"; phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii";You should be setting the delay tuning in this patch as well.
I will try to fix this in the next version.
Quoted 6 lines
Quoted 6 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +0
-1pinctrl-names = "default"; pinctrl-0 = <&gmac1m1_miim &gmac1m1_tx_bus2 --2.38.1
Thanks
-Anand