arch/riscv: RISC-V 32-bit NO MMU support

PATCH In review Yimin Gu 3 participants 6 messages Nov 17, 2022 – Nov 26, 2022 RISC-V

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Yimin Gu

author

2022-11-17 14:04 UTC #0 lore raw

cover arch/riscv: RISC-V 32-bit NO MMU support

The following patch adds support for 32-bit RISC-V No-MMU build. Currently for No-MMU RISC-V, only 64-bit is supported. There're no substancial changes in code but macros and compiling options. Uclibc, elf2flt, and the kernel need to be patched.
This is based on damien-lemoal/buildroot which first added 64-bit No-MMU support, and my earlier porting attempt regymm/buildroot.
As a lot of FPGA-based RISC-V cores are 32-bit and many of the low ones are without MMU, this can bring Linux to cores as light as RV32IMA. For this reason, only the minimum required extensions are enabled in the buildroot and kernel configurations.

Yimin Gu (1):
arch/riscv: RISC-V 32-bit NO MMU support

 arch/Config.in.riscv                          |    2 -
 board/riscv/nommu/patches/linux-headers       |    1 +
 ...imental-RISC-V-32-bit-No-MMU-support.patch | 1355 +++++++++++++++++
 configs/qemu_riscv32_nommu_virt_defconfig     |   19 +
 package/Makefile.in                           |   13 +-
 ...ed-RISC-V-32-bit-compilation-support.patch |   74 +
 .../uclibc/0001-RISC-V-32-bit-support.patch   |  145 ++
 package/uclibc/Config.in                      |    2 +
 8 files changed, 1607 insertions(+), 4 deletions(-)
 create mode 120000 board/riscv/nommu/patches/linux-headers
 create mode 100644 board/riscv/nommu/patches/linux/5.19/0001-Experimental-RISC-V-32-bit-No-MMU-support.patch
 create mode 100644 configs/qemu_riscv32_nommu_virt_defconfig
 create mode 100644 package/elf2flt/0006-Added-RISC-V-32-bit-compilation-support.patch
 create mode 100644 package/uclibc/0001-RISC-V-32-bit-support.patch

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2.38.1

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Yimin Gu

author

2022-11-17 14:04 UTC #1 lore raw

PATCH 1/1 arch/riscv: RISC-V 32-bit NO MMU support

Signed-off-by Yimin Gu <[email protected]>

---
 arch/Config.in.riscv                          |    2 -
 board/riscv/nommu/patches/linux-headers       |    1 +
 ...imental-RISC-V-32-bit-No-MMU-support.patch | 1355 +++++++++++++++++
 configs/qemu_riscv32_nommu_virt_defconfig     |   19 +
 package/Makefile.in                           |   13 +-
 ...ed-RISC-V-32-bit-compilation-support.patch |   74 +
 .../uclibc/0001-RISC-V-32-bit-support.patch   |  145 ++
 package/uclibc/Config.in                      |    2 +
 8 files changed, 1607 insertions(+), 4 deletions(-)
 create mode 120000 board/riscv/nommu/patches/linux-headers
 create mode 100644 board/riscv/nommu/patches/linux/5.19/0001-Experimental-RISC-V-32-bit-No-MMU-support.patch
 create mode 100644 configs/qemu_riscv32_nommu_virt_defconfig
 create mode 100644 package/elf2flt/0006-Added-RISC-V-32-bit-compilation-support.patch
 create mode 100644 package/uclibc/0001-RISC-V-32-bit-support.patch

arch/Config.in.riscv +0 -2

index b5e84389e0..c79cf9b410 100644
@@ -71,7 +71,6 @@ choice
 
 config BR2_RISCV_32
 	bool "32-bit"
-	select BR2_USE_MMU
 
 config BR2_RISCV_64
 	bool "64-bit"

@@ -82,7 +81,6 @@ endchoice
 config BR2_RISCV_USE_MMU
 	bool "MMU support"
 	default y
-	depends on BR2_RISCV_64
 	select BR2_USE_MMU
 	help
 	  Enable this option if your RISC-V core has a MMU (Memory

board/riscv/nommu/patches/linux-headers new file +1 -0

new file mode 120000
index 0000000000..ce5e2c77b2
@@ -0,0 +1 @@
+linux/
\ No newline at end of file

board/riscv/nommu/patches/linux/5.19/0001-Experimental-RISC-V-32-bit-No-MMU-support.patch new file +1355 -0

1,355 lines not on this page · raw message

configs/qemu_riscv32_nommu_virt_defconfig new file +19 -0

new file mode 100644
index 0000000000..eed86b3164
@@ -0,0 +1,19 @@
+BR2_riscv=y
+BR2_riscv_custom=y
+BR2_RISCV_ISA_CUSTOM_RVM=y
+BR2_RISCV_32=y
+# BR2_RISCV_USE_MMU is not set
+BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_19=y
+BR2_PTHREADS_NONE=y
+BR2_GLOBAL_PATCH_DIR="board/riscv/nommu/patches"
+BR2_ROOTFS_POST_IMAGE_SCRIPT="board/qemu/post-image.sh"
+BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_DEFCONFIG)"
+BR2_LINUX_KERNEL=y
+BR2_LINUX_KERNEL_CUSTOM_VERSION=y
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.19"
+BR2_LINUX_KERNEL_DEFCONFIG="nommu_rv32_virt"
+BR2_PACKAGE_BUSYBOX_CONFIG="package/busybox/busybox-minimal.config"
+# BR2_PACKAGE_IFUPDOWN_SCRIPTS is not set
+BR2_TARGET_ROOTFS_EXT2=y
+BR2_PACKAGE_HOST_QEMU=y
+BR2_PACKAGE_HOST_QEMU_SYSTEM_MODE=y

package/Makefile.in +11 -2

index 43d214bcbe..f196c3a28d 100644
@@ -39,10 +39,16 @@ endif
 # Compute GNU_TARGET_NAME
 GNU_TARGET_NAME = $(ARCH)-$(TARGET_VENDOR)-$(TARGET_OS)-$(LIBC)$(ABI)
 
-# FLAT binary format needs uclinux, except RISC-V 64-bits which needs
+# FLAT binary format needs uclinux, except RISC-V nommu which needs
 # the regular linux name.
-ifeq ($(BR2_BINFMT_FLAT):$(BR2_RISCV_64),y:)
+ifeq ($(BR2_BINFMT_FLAT),y)
+ifeq ($(BR2_RISCV_64),y)
+TARGET_OS = linux
+else ifeq ($(BR2_RISCV_32),y)
+TARGET_OS = linux
+else
 TARGET_OS = uclinux
+endif
 else
 TARGET_OS = linux
 endif

@@ -177,6 +183,9 @@ ifeq ($(BR2_BINFMT_FLAT),y)
 ifeq ($(BR2_RISCV_64),y)
 TARGET_CFLAGS += -fPIC
 endif
+ifeq ($(BR2_RISCV_32),y)
+TARGET_CFLAGS += -fPIC
+endif
 ifeq ($(BR2_BINFMT_FLAT_ONE),y)
 ELF2FLT_FLAGS = $(if $($(PKG)_FLAT_STACKSIZE),\
 	-Wl$(comma)-elf2flt="-r -s$($(PKG)_FLAT_STACKSIZE)",\

package/elf2flt/0006-Added-RISC-V-32-bit-compilation-support.patch new file +74 -0

74 lines not on this page · raw message

package/uclibc/0001-RISC-V-32-bit-support.patch new file +145 -0

145 lines not on this page · raw message

package/uclibc/Config.in +2 -0

index 2555487f06..a1e9305ca0 100644
@@ -17,6 +17,7 @@ config BR2_PACKAGE_UCLIBC_ARCH_SUPPORTS
 	default y if BR2_powerpc
 	# see libc/sysdeps/linux/riscv64/sys/asm.h
 	default y if BR2_RISCV_64 && (BR2_RISCV_ABI_LP64 || BR2_RISCV_ABI_LP64D)
+	default y if BR2_RISCV_32
 	default y if BR2_sh4
 	default y if BR2_sh4eb
 	default y if BR2_sparc

@@ -138,6 +139,7 @@ config BR2_UCLIBC_TARGET_ARCH
 	default "i386"	   if BR2_i386
 	default "x86_64"   if BR2_x86_64
 	default "riscv64"  if BR2_RISCV_64
+	default "riscv32"  if BR2_RISCV_32
 
 config BR2_UCLIBC_MIPS_ABI
 	string

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Waldemar Brodkorb

Tested-by on the v1 series

2022-11-20 07:50 UTC #2 lore raw

In reply to Yimin Gu

Hi,
Yimin Gu wrote,

Quoted 14 lines

The following patch adds support for 32-bit RISC-V No-MMU build. Currently for No-MMU RISC-V, only 64-bit is supported. There're no substancial changes in code but macros and compiling options. Uclibc, elf2flt, and the kernel need to be patched.
This is based on damien-lemoal/buildroot which first added 64-bit No-MMU support, and my earlier porting attempt regymm/buildroot.
As a lot of FPGA-based RISC-V cores are 32-bit and many of the low ones are without MMU, this can bring Linux to cores as light as RV32IMA. For this reason, only the minimum required extensions are enabled in the buildroot and kernel configurations.
Yimin Gu (1):
arch/riscv: RISC-V 32-bit NO MMU support

Quoted 14 lines

 arch/Config.in.riscv                          |    2 -
 board/riscv/nommu/patches/linux-headers       |    1 +
 ...imental-RISC-V-32-bit-No-MMU-support.patch | 1355 +++++++++++++++++
 configs/qemu_riscv32_nommu_virt_defconfig     |   19 +
 package/Makefile.in                           |   13 +-
 ...ed-RISC-V-32-bit-compilation-support.patch |   74 +
 .../uclibc/0001-RISC-V-32-bit-support.patch   |  145 ++
 package/uclibc/Config.in                      |    2 +
 8 files changed, 1607 insertions(+), 4 deletions(-)
 create mode 120000 board/riscv/nommu/patches/linux-headers
 create mode 100644 board/riscv/nommu/patches/linux/5.19/0001-Experimental-RISC-V-32-bit-No-MMU-support.patch
 create mode 100644 configs/qemu_riscv32_nommu_virt_defconfig
 create mode 100644 package/elf2flt/0006-Added-RISC-V-32-bit-compilation-support.patch
 create mode 100644 package/uclibc/0001-RISC-V-32-bit-support.patch

You can add a

Tested-by Waldemar Brodkorb <[email protected]>

One minor note, add a startup description for noMMU in board/qemu/riscv32-virt/readme.txt.

best regards
Waldemar
_______________________________________________
buildroot mailing list
[email protected]
https://lists.buildroot.org/mailman/listinfo/buildroot

Yimin Gu

author

2022-11-20 15:33 UTC #3 lore raw

PATCH 1/1 arch/riscv: RISC-V 32-bit NO MMU support

Tested-by Waldemar Brodkorb <[email protected]>

Signed-off-by Yimin Gu <[email protected]>

---
 arch/Config.in.riscv                          |    2 -
 .../riscv32-virt/nommu/patches/linux-headers  |    1 +
 ...imental-RISC-V-32-bit-No-MMU-support.patch | 1355 +++++++++++++++++
 board/qemu/riscv32-virt/readme.txt            |    2 +
 configs/qemu_riscv32_nommu_virt_defconfig     |   19 +
 package/Makefile.in                           |   13 +-
 ...ed-RISC-V-32-bit-compilation-support.patch |   74 +
 .../uclibc/0001-RISC-V-32-bit-support.patch   |  145 ++
 package/uclibc/Config.in                      |    2 +
 9 files changed, 1609 insertions(+), 4 deletions(-)
 create mode 120000 board/qemu/riscv32-virt/nommu/patches/linux-headers
 create mode 100644 board/qemu/riscv32-virt/nommu/patches/linux/5.19/0001-Experimental-RISC-V-32-bit-No-MMU-support.patch
 create mode 100644 configs/qemu_riscv32_nommu_virt_defconfig
 create mode 100644 package/elf2flt/0006-Added-RISC-V-32-bit-compilation-support.patch
 create mode 100644 package/uclibc/0001-RISC-V-32-bit-support.patch

arch/Config.in.riscv +0 -2

index b5e84389e0..c79cf9b410 100644
@@ -71,7 +71,6 @@ choice
 
 config BR2_RISCV_32
 	bool "32-bit"
-	select BR2_USE_MMU
 
 config BR2_RISCV_64
 	bool "64-bit"

@@ -82,7 +81,6 @@ endchoice
 config BR2_RISCV_USE_MMU
 	bool "MMU support"
 	default y
-	depends on BR2_RISCV_64
 	select BR2_USE_MMU
 	help
 	  Enable this option if your RISC-V core has a MMU (Memory

board/qemu/riscv32-virt/nommu/patches/linux-headers new file +1 -0

new file mode 120000
index 0000000000..ce5e2c77b2
@@ -0,0 +1 @@
+linux/
\ No newline at end of file

board/qemu/riscv32-virt/nommu/patches/linux/5.19/0001-Experimental-RISC-V-32-bit-No-MMU-support.patch new file +1355 -0

1,355 lines not on this page · raw message

board/qemu/riscv32-virt/readme.txt +2 -0

index 32b4333512..a7ec3ce8bf 100644
@@ -2,4 +2,6 @@ Run Linux in emulation with:
 
   qemu-system-riscv32 -M virt -bios output/images/fw_jump.elf -kernel output/images/Image -append "rootwait root=/dev/vda ro" -drive file=output/images/rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -netdev user,id=net0 -device virtio-net-device,netdev=net0 -nographic # qemu_riscv32_virt_defconfig
 
+  qemu-system-riscv32 -M virt -bios none -kernel output/images/Image -append "rootwait root=/dev/vda ro" -drive file=output/images/rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -nographic -cpu rv32,mmu=off # qemu_riscv32_nommu_virt_defconfig
+
 The login prompt will appear in the terminal that started Qemu.

configs/qemu_riscv32_nommu_virt_defconfig new file +19 -0

new file mode 100644
index 0000000000..5b17f53632
@@ -0,0 +1,19 @@
+BR2_riscv=y
+BR2_riscv_custom=y
+BR2_RISCV_ISA_CUSTOM_RVM=y
+BR2_RISCV_32=y
+# BR2_RISCV_USE_MMU is not set
+BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_19=y
+BR2_PTHREADS_NONE=y
+BR2_GLOBAL_PATCH_DIR="board/qemu/riscv32-virt/nommu/patches"
+BR2_ROOTFS_POST_IMAGE_SCRIPT="board/qemu/post-image.sh"
+BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_DEFCONFIG)"
+BR2_LINUX_KERNEL=y
+BR2_LINUX_KERNEL_CUSTOM_VERSION=y
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.19"
+BR2_LINUX_KERNEL_DEFCONFIG="nommu_rv32_virt"
+BR2_PACKAGE_BUSYBOX_CONFIG="package/busybox/busybox-minimal.config"
+# BR2_PACKAGE_IFUPDOWN_SCRIPTS is not set
+BR2_TARGET_ROOTFS_EXT2=y
+BR2_PACKAGE_HOST_QEMU=y
+BR2_PACKAGE_HOST_QEMU_SYSTEM_MODE=y

package/Makefile.in +11 -2

index 43d214bcbe..f196c3a28d 100644
@@ -39,10 +39,16 @@ endif
 # Compute GNU_TARGET_NAME
 GNU_TARGET_NAME = $(ARCH)-$(TARGET_VENDOR)-$(TARGET_OS)-$(LIBC)$(ABI)
 
-# FLAT binary format needs uclinux, except RISC-V 64-bits which needs
+# FLAT binary format needs uclinux, except RISC-V nommu which needs
 # the regular linux name.
-ifeq ($(BR2_BINFMT_FLAT):$(BR2_RISCV_64),y:)
+ifeq ($(BR2_BINFMT_FLAT),y)
+ifeq ($(BR2_RISCV_64),y)
+TARGET_OS = linux
+else ifeq ($(BR2_RISCV_32),y)
+TARGET_OS = linux
+else
 TARGET_OS = uclinux
+endif
 else
 TARGET_OS = linux
 endif

@@ -177,6 +183,9 @@ ifeq ($(BR2_BINFMT_FLAT),y)
 ifeq ($(BR2_RISCV_64),y)
 TARGET_CFLAGS += -fPIC
 endif
+ifeq ($(BR2_RISCV_32),y)
+TARGET_CFLAGS += -fPIC
+endif
 ifeq ($(BR2_BINFMT_FLAT_ONE),y)
 ELF2FLT_FLAGS = $(if $($(PKG)_FLAT_STACKSIZE),\
 	-Wl$(comma)-elf2flt="-r -s$($(PKG)_FLAT_STACKSIZE)",\

package/elf2flt/0006-Added-RISC-V-32-bit-compilation-support.patch new file +74 -0

74 lines not on this page · raw message

package/uclibc/0001-RISC-V-32-bit-support.patch new file +145 -0

145 lines not on this page · raw message

package/uclibc/Config.in +2 -0

index 2555487f06..a1e9305ca0 100644
@@ -17,6 +17,7 @@ config BR2_PACKAGE_UCLIBC_ARCH_SUPPORTS
 	default y if BR2_powerpc
 	# see libc/sysdeps/linux/riscv64/sys/asm.h
 	default y if BR2_RISCV_64 && (BR2_RISCV_ABI_LP64 || BR2_RISCV_ABI_LP64D)
+	default y if BR2_RISCV_32
 	default y if BR2_sh4
 	default y if BR2_sh4eb
 	default y if BR2_sparc

@@ -138,6 +139,7 @@ config BR2_UCLIBC_TARGET_ARCH
 	default "i386"	   if BR2_i386
 	default "x86_64"   if BR2_x86_64
 	default "riscv64"  if BR2_RISCV_64
+	default "riscv32"  if BR2_RISCV_32
 
 config BR2_UCLIBC_MIPS_ABI
 	string

Signature · 7 lines

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Yimin Gu

author

2022-11-20 15:38 UTC #4 lore raw

In reply to Waldemar Brodkorb

Hi,

Quoted 33 lines · Waldemar Brodkorb

Hi,
Yimin Gu wrote,
Quoted 14 lines
The following patch adds support for 32-bit RISC-V No-MMU build. Currently for No-MMU RISC-V, only 64-bit is supported. There're no substancial changes in code but macros and compiling options. Uclibc, elf2flt, and the kernel need to be patched.
This is based on damien-lemoal/buildroot which first added 64-bit No-MMU support, and my earlier porting attempt regymm/buildroot.
As a lot of FPGA-based RISC-V cores are 32-bit and many of the low ones are without MMU, this can bring Linux to cores as light as RV32IMA. For this reason, only the minimum required extensions are enabled in the buildroot and kernel configurations.
Yimin Gu (1):
arch/riscv: RISC-V 32-bit NO MMU support
Quoted 14 lines
 arch/Config.in.riscv                          |    2 -
 board/riscv/nommu/patches/linux-headers       |    1 +
 ...imental-RISC-V-32-bit-No-MMU-support.patch | 1355 +++++++++++++++++
 configs/qemu_riscv32_nommu_virt_defconfig     |   19 +
 package/Makefile.in                           |   13 +-
 ...ed-RISC-V-32-bit-compilation-support.patch |   74 +
 .../uclibc/0001-RISC-V-32-bit-support.patch   |  145 ++
 package/uclibc/Config.in                      |    2 +
 8 files changed, 1607 insertions(+), 4 deletions(-)
 create mode 120000 board/riscv/nommu/patches/linux-headers
 create mode 100644 board/riscv/nommu/patches/linux/5.19/0001-Experimental-RISC-V-32-bit-No-MMU-support.patch
 create mode 100644 configs/qemu_riscv32_nommu_virt_defconfig
 create mode 100644 package/elf2flt/0006-Added-RISC-V-32-bit-compilation-support.patch
 create mode 100644 package/uclibc/0001-RISC-V-32-bit-support.patch

Quoted 8 lines

You can add a
Tested-by Waldemar Brodkorb <[email protected]>
One minor note, add a startup description for noMMU in board/qemu/riscv32-virt/readme.txt.
best regards
Waldemar

Thanks for the testing and note. I have sent the refined patch in a separate reply.

best regards,
Yimin Gu
_______________________________________________
buildroot mailing list
[email protected]
https://lists.buildroot.org/mailman/listinfo/buildroot

Charles Lohr

2022-11-26 04:00 UTC #5 lore raw

I've tested this a fair bit over the last several days and I really appreciate the work. Any hopes of getting this committed to mainline buildroot?

Quoted 52 lines · Yimin Gu

Hi,
Quoted 9 lines · Waldemar Brodkorb
Hi,
Yimin Gu wrote,
Quoted 5 lines
The following patch adds support for 32-bit RISC-V No-MMU build. Currently for No-MMU RISC-V, only 64-bit is supported. There're no substancial changes in code but macros and compiling options. Uclibc, elf2flt, and the kernel need to be patched.
This is based on damien-lemoal/buildroot which first added 64-bit
No-MMU
Quoted 4 lines
Quoted 4 lines
support, and my earlier porting attempt regymm/buildroot.
As a lot of FPGA-based RISC-V cores are 32-bit and many of the low ones are without MMU, this can bring Linux to cores as light as RV32IMA. For this reason, only the minimum required extensions are enabled in
the
Quoted 5 lines
Quoted 5 lines
buildroot and kernel configurations.
Yimin Gu (1):
arch/riscv: RISC-V 32-bit NO MMU support
Quoted 11 lines
Quoted 11 lines
 arch/Config.in.riscv                          |    2 -
 board/riscv/nommu/patches/linux-headers       |    1 +
 ...imental-RISC-V-32-bit-No-MMU-support.patch | 1355 +++++++++++++++++
 configs/qemu_riscv32_nommu_virt_defconfig     |   19 +
 package/Makefile.in                           |   13 +-
 ...ed-RISC-V-32-bit-compilation-support.patch |   74 +
 .../uclibc/0001-RISC-V-32-bit-support.patch   |  145 ++
 package/uclibc/Config.in                      |    2 +
 8 files changed, 1607 insertions(+), 4 deletions(-)
 create mode 120000 board/riscv/nommu/patches/linux-headers
 create mode 100644
board/riscv/nommu/patches/linux/5.19/0001-Experimental-RISC-V-32-bit-No-MMU-support.patch
Quoted 2 lines
Quoted 2 lines
 create mode 100644 configs/qemu_riscv32_nommu_virt_defconfig
 create mode 100644
package/elf2flt/0006-Added-RISC-V-32-bit-compilation-support.patch
Quoted 10 lines
Quoted 1 line
 create mode 100644 package/uclibc/0001-RISC-V-32-bit-support.patch
You can add a
Tested-by Waldemar Brodkorb <[email protected]>
One minor note, add a startup description for noMMU in board/qemu/riscv32-virt/readme.txt.
best regards
Waldemar
Thanks for the testing and note. I have sent the refined patch in a separate reply.

Quoted 7 lines

best regards,
Yimin Gu
_______________________________________________
buildroot mailing list
[email protected]
https://lists.buildroot.org/mailman/listinfo/buildroot

_______________________________________________
buildroot mailing list
[email protected]
https://lists.buildroot.org/mailman/listinfo/buildroot