Add SM6115 MDSS/DPU support
Subsystems (5)
cover Add SM6115 MDSS/DPU support
This patch series add support for MDSS and DPU block found on SM6115. These patches were tested on Xiaomi Redmi 9T smartphone.
Adam Skladowski (2):
dt-bindings: display/msm: add support for the display on SM6115 drm/msm/disp/dpu1: add support for display on SM6115
.../bindings/display/msm/qcom,sm6115-dpu.yaml | 87 ++++++++ .../display/msm/qcom,sm6115-mdss.yaml | 187 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 87 ++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c | 5 + 6 files changed, 368 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
Signature · 1 line
2.25.1
PATCH 1/2 dt-bindings: display/msm: add support for the display
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM6115 platform.
Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused. Lack of dsi phy supply in example is intended
due to fact on qcm2290, sm6115 and sm6125
this phy is supplied via power domain, not regulator.
--- .../bindings/display/msm/qcom,sm6115-dpu.yaml | 87 ++++++++ .../display/msm/qcom,sm6115-mdss.yaml | 187 ++++++++++++++++++ 2 files changed, 274 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml new file +87 -0
@@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SM6115 target + +maintainers: + - Dmitry Baryshkov <[email protected]> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6115-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display AXI clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock from dispcc + - description: Display lut clock from dispcc + - description: Display rotator clock from dispcc + - description: Display vsync clock from dispcc + + clock-names: + items: + - const: bus + - const: iface + - const: core + - const: lut + - const: rot + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@5e01000 { + compatible = "qcom,sm6115-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; +...
Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml new file +187 -0
187 lines not on this page · raw message
Signature · 1 line
2.25.1
Rob Herring
maintainerRe: [PATCH 1/2] dt-bindings: display/msm: add support for the display
Quoted 7 lines · Adam Skladowski
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM6115 platform.
Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused. Lack of dsi phy supply in example is intended
due to fact on qcm2290, sm6115 and sm6125
this phy is supplied via power domain, not regulator.
Quoted 8 lines
Signed-off-by Adam Skladowski <[email protected]>--- .../bindings/display/msm/qcom,sm6115-dpu.yaml | 87 ++++++++ .../display/msm/qcom,sm6115-mdss.yaml | 187 ++++++++++++++++++ 2 files changed, 274 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:./Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/display/msm/dpu-common.yaml./Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/display/msm/mdss-common.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.example.dtb: display-controller@5e01000: False schema does not allow {'compatible': ['qcom,sm6115-dpu'], 'reg': [[98570240, 585728], [99287040, 8200]], 'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 63], [4294967295, 2], [4294967295, 10], [4294967295, 12], [4294967295, 16], [4294967295, 18]], 'clock-names': ['bus', 'iface', 'core', 'lut', 'rot', 'vsync'], 'operating-points-v2': [[4294967295]], 'power-domains': [[4294967295, 0]], 'interrupts': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[4294967295]]}}}, '$nodename': ['display-controller@5e01000']}
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.example.dtb: display-controller@5e01000: Unevaluated properties are not allowed ('interrupts', 'operating-points-v2', 'ports', 'power-domains' were unexpected)
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.example.dtb: mdss@5e00000: False schema does not allow {'#address-cells': [[1]], '#size-cells': [[1]], 'compatible': ['qcom,sm6115-mdss'], 'reg': [[98566144, 4096]], 'reg-names': ['mdss'], 'power-domains': [[4294967295, 0]], 'clocks': [[4294967295, 61], [4294967295, 63], [4294967295, 10]], 'clock-names': ['iface', 'bus', 'core'], 'interrupts': [[0, 186, 4]], 'interrupt-controller': True, '#interrupt-cells': [[1]], 'iommus': [[4294967295, 1056, 2], [4294967295, 1057, 0]], 'ranges': True, 'display-controller@5e01000': {'compatible': ['qcom,sm6115-dpu'], 'reg': [[98570240, 585728], [99287040, 8200]], 'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 63], [4294967295, 2], [4294967295, 10], [4294967295, 12], [4294967295, 16], [4294967295, 18]], 'clock-names': ['bus', 'iface', 'core', 'lut', 'rot', 'vsync'], 'operating-points-v2': [[4294967295]], 'power-domains': [[4294967295, 0]], 'int
errupts': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[1]], 'phandle': [[3]]}}}}, 'dsi@5e94000': {'compatible': ['qcom,dsi-ctrl-6g-qcm2290'], 'reg': [[99172352, 1024]], 'reg-names': ['dsi_ctrl'], 'interrupts': [[4]], 'clocks': [[4294967295, 4], [4294967295, 7], [4294967295, 14], [4294967295, 8], [4294967295, 2], [4294967295, 63]], 'clock-names': ['byte', 'byte_intf', 'pixel', 'core', 'iface', 'bus'], 'assigned-clocks': [[4294967295, 5], [4294967295, 15]], 'assigned-clock-parents': [[2, 0], [2, 1]], 'operating-points-v2': [[4294967295]], 'power-domains': [[4294967295, 0]], 'phys': [[2]], 'phy-names': ['dsi'], '#address-cells': [[1]], '#size-cells': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[3]], 'phandle': [[1]]}}, 'port@1': {'reg': [[1]], 'endpoint': {}}}}, 'phy@5e94400': {'compatible': ['qcom,dsi-phy-14nm-2290'], 'reg': [[9917 3376, 256], [99173632, 768], [99174400, 392]], 'reg-names': ['dsi_phy', 'dsi_phy_lane', 'dsi_pll'], '#clock-cells': [[1]], '#phy-cells': [[0]], 'clocks': [[4294967295, 2], [4294967295, 0]], 'clock-names': ['iface', 'ref'], 'phandle': [[2]]}, '$nodename': ['mdss@5e00000']}
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.example.dtb: mdss@5e00000: Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'interrupt-controller', 'interrupts', 'power-domains', 'ranges', 'reg', 'reg-names' were unexpected)
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.example.dtb: display-controller@5e01000: False schema does not allow {'compatible': ['qcom,sm6115-dpu'], 'reg': [[98570240, 585728], [99287040, 8200]], 'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 63], [4294967295, 2], [4294967295, 10], [4294967295, 12], [4294967295, 16], [4294967295, 18]], 'clock-names': ['bus', 'iface', 'core', 'lut', 'rot', 'vsync'], 'operating-points-v2': [[4294967295]], 'power-domains': [[4294967295, 0]], 'interrupts': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[1]], 'phandle': [[3]]}}}, '$nodename': ['display-controller@5e01000']}
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.example.dtb: display-controller@5e01000: Unevaluated properties are not allowed ('interrupts', 'operating-points-v2', 'ports', 'power-domains' were unexpected)
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command.
Rob Herring
maintainerRe: [PATCH 1/2] dt-bindings: display/msm: add support for the display
In reply to Adam SkladowskiQuoted 6 lines · Adam Skladowski
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM6115 platform.
Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused. Lack of dsi phy supply in example is intended
due to fact on qcm2290, sm6115 and sm6125
this phy is supplied via power domain, not regulator.
The subject needs 'sm6115' somewhere.
Quoted 27 lines
Signed-off-by Adam Skladowski <[email protected]>--- .../bindings/display/msm/qcom,sm6115-dpu.yaml | 87 ++++++++ .../display/msm/qcom,sm6115-mdss.yaml | 187 ++++++++++++++++++ 2 files changed, 274 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yamlDocumentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml new file +12
-0@@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SM6115 target + +maintainers: + - Dmitry Baryshkov <[email protected]> + +$ref: /schemas/display/msm/dpu-common.yaml#
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml line 22
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml new file +10
-0+ +properties: + compatible: + items: + - const: qcom,sm6115-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set
Drop 'Address offset and size for'.
s/mdp/MDP/ ?
s/vbif/VBIF/ ?
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml new file +4
-0+ + reg-names: + items: + - const: mdp
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml line 36
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml new file +10
-0+ - const: vbif + + clocks: + items: + - description: Display AXI clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock from dispcc + - description: Display lut clock from dispcc + - description: Display rotator clock from dispcc + - description: Display vsync clock from dispcc
Source of the clock is outside the scope of the binding.
Quoted 248 lines
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml new file +51
-0+ + clock-names: + items: + - const: bus + - const: iface + - const: core + - const: lut + - const: rot + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@5e01000 { + compatible = "qcom,sm6115-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; +...Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml new file +187
-0@@ -0,0 +1,187 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6115 Display MDSS + +maintainers: + - Dmitry Baryshkov <[email protected]> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS + are mentioned for SM6115 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6115-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6115-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-ctrl-6g-qcm2290 + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-14nm-2290 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + mdss@5e00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sm6115-mdss"; + reg = <0x05e00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; + ranges; + + display-controller@5e01000 { + compatible = "qcom,sm6115-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible = "qcom,dsi-ctrl-6g-qcm2290"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@5e94400 { + compatible = "qcom,dsi-phy-14nm-2290"; + reg = <0x05e94400 0x100>, + <0x05e94500 0x300>, + <0x05e94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + }; + }; +...Signature · 1 line
2.25.1
Re: [PATCH 1/2] dt-bindings: display/msm: add support for the display
In reply to Adam SkladowskiQuoted 56 lines · Adam Skladowski
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM6115 platform.
Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused. Lack of dsi phy supply in example is intended
due to fact on qcm2290, sm6115 and sm6125
this phy is supplied via power domain, not regulator.Signed-off-by Adam Skladowski <[email protected]>--- .../bindings/display/msm/qcom,sm6115-dpu.yaml | 87 ++++++++ .../display/msm/qcom,sm6115-mdss.yaml | 187 ++++++++++++++++++ 2 files changed, 274 insertions(+)create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yamlcreate mode 100644Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yamlDocumentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml new file +35
-0@@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SM6115 target + +maintainers: + - Dmitry Baryshkov <[email protected]> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6115-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display AXI clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock from dispcc + - description: Display lut clock from dispcc + - description: Display rotator clock from dispcc
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml line 45
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml new file +10
-0+ - description: Display vsync clock from dispcc + + clock-names: + items: + - const: bus + - const: iface + - const: core + - const: lut + - const: rot + - const: vsync
Please add:
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
Per Krzysztof's request these requirements are migrating from dpu-common to individual dpu schemas
Quoted 94 lines
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml new file +42
-0+ +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@5e01000 { + compatible = "qcom,sm6115-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; +...Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml new file +46
-0@@ -0,0 +1,187 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6115 Display MDSS + +maintainers: + - Dmitry Baryshkov <[email protected]> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS + are mentioned for SM6115 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6115-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6115-dpu + + "^dsi@[0-9a-f]+$":
Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml line 56
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml new file +10
-0+ type: object + properties: + compatible: + const: qcom,dsi-ctrl-6g-qcm2290 + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-14nm-2290
required:
compatible
The same story
Quoted 81 lines
Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml new file +81
-0+ +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + mdss@5e00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sm6115-mdss"; + reg = <0x05e00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; + ranges; + + display-controller@5e01000 { + compatible = "qcom,sm6115-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible = "qcom,dsi-ctrl-6g-qcm2290"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel",
Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml line 147
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml new file +10
-0+ "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + phys = <&dsi0_phy>; + phy-names = "dsi";
phy-names are being phased out, please drop this line.
Quoted 40 lines
Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml new file +40
-0+ + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@5e94400 { + compatible = "qcom,dsi-phy-14nm-2290"; + reg = <0x05e94400 0x100>, + <0x05e94500 0x300>, + <0x05e94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + }; + }; +...
Signature · 2 lines
With best wishes Dmitry
Re: [PATCH 1/2] dt-bindings: display/msm: add support for the display
In reply to Adam SkladowskiQuoted 138 lines · Adam Skladowski
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM6115 platform.
Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused. Lack of dsi phy supply in example is intended
due to fact on qcm2290, sm6115 and sm6125
this phy is supplied via power domain, not regulator.Signed-off-by Adam Skladowski <[email protected]>--- .../bindings/display/msm/qcom,sm6115-dpu.yaml | 87 ++++++++ .../display/msm/qcom,sm6115-mdss.yaml | 187 ++++++++++++++++++ 2 files changed, 274 insertions(+)create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yamlcreate mode 100644Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yamlDocumentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml new file +87
-0@@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SM6115 target + +maintainers: + - Dmitry Baryshkov <[email protected]> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6115-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display AXI clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock from dispcc + - description: Display lut clock from dispcc + - description: Display rotator clock from dispcc + - description: Display vsync clock from dispcc + + clock-names: + items: + - const: bus + - const: iface + - const: core + - const: lut + - const: rot + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@5e01000 { + compatible = "qcom,sm6115-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; +...Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml new file +24
-0@@ -0,0 +1,187 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6115 Display MDSS + +maintainers: + - Dmitry Baryshkov <[email protected]> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS + are mentioned for SM6115 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6115-mdss + + clocks:
Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml line 34
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml new file +10
-0+ items: + - description: Display AHB clock from gcc + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core
I think you can drop clock-names from the MDSS node.
Quoted 153 lines
Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml new file +153
-0+ + iommus: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6115-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-ctrl-6g-qcm2290 + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-14nm-2290 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + mdss@5e00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sm6115-mdss"; + reg = <0x05e00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; + ranges; + + display-controller@5e01000 { + compatible = "qcom,sm6115-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible = "qcom,dsi-ctrl-6g-qcm2290"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@5e94400 { + compatible = "qcom,dsi-phy-14nm-2290"; + reg = <0x05e94400 0x100>, + <0x05e94500 0x300>, + <0x05e94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + }; + }; +...
Signature · 2 lines
With best wishes Dmitry
PATCH 2/2 drm/msm/disp/dpu1: add support for display on SM6115
In reply to Adam SkladowskiAdd required display hw catalog changes for SM6115.
--- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 87 +++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c | 5 ++ 4 files changed, 94 insertions(+)
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +87 -0
@@ -321,6 +321,18 @@ static const struct dpu_caps sc7180_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; +static const struct dpu_caps sm6115_dpu_caps = { + .max_mixer_width =DEFAULT_DPU_OUTPUT_LINE_WIDTH , + .max_mixer_blendstages =0x4 , + .qseed_type =DPU_SSPP_SCALER_QSEED3LITE , + .smart_dma_rev =DPU_SSPP_SMART_DMA_V2 ,/* TODO: v2.5 */ + .ubwc_version =DPU_HW_UBWC_VER_20 , + .has_dim_layer = true, + .has_idle_pc = true, + .max_linewidth =2160 , + .pixel_ram_size =DEFAULT_PIXEL_RAM_SIZE , +}; +static const struct dpu_caps sm8150_dpu_caps = { .max_mixer_width =DEFAULT_DPU_OUTPUT_LINE_WIDTH , .max_mixer_blendstages =0xb ,
@@ -475,6 +487,19 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = { }, }; +static const struct dpu_mdp_cfg sm6115_mdp[] = { + { + .name ="top_0" , .id =MDP_TOP , + .base =0x0 , .len =0x494 , + .features =0 , + .highest_bank_bit =0x1 , + .clk_ctrls[DPU_CLK_CTRL_VIG0 ] = { + .reg_off =0x2AC , .bit_off =0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0 ] = { + .reg_off =0x2AC , .bit_off =8 }, + }, +}; +static const struct dpu_mdp_cfg sm8250_mdp[] = { { .name ="top_0" , .id =MDP_TOP ,
@@ -852,6 +877,16 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), }; +static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = +_VIG_SBLK ("0" ,2 ,DPU_SSPP_SCALER_QSEED3LITE ); + +static const struct dpu_sspp_cfg sm6115_sspp[] = { +SSPP_BLK ("sspp_0" ,SSPP_VIG0 ,0x4000 ,VIG_SM8250_MASK , + sm6115_vig_sblk_0,0 ,SSPP_TYPE_VIG ,DPU_CLK_CTRL_VIG0 ), +SSPP_BLK ("sspp_8" ,SSPP_DMA0 ,0x24000 ,DMA_SDM845_MASK , + sdm845_dma_sblk_0,1 ,SSPP_TYPE_DMA ,DPU_CLK_CTRL_DMA0 ), +}; +static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =_VIG_SBLK ("0" ,5 ,DPU_SSPP_SCALER_QSEED3LITE ); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
@@ -1590,6 +1625,35 @@ static const struct dpu_perf_cfg sc7180_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_perf_cfg sm6115_perf_data = { + .max_bw_low =3100000 , + .max_bw_high =4000000 , + .min_core_ib =2400000 , + .min_llcc_ib =800000 , + .min_dram_ib =800000 , + .min_prefill_lines =24 , + .danger_lut_tbl = {0xff ,0xffff ,0x0 }, + .safe_lut_tbl = {0xfff0 ,0xff00 ,0xffff }, + .qos_lut_tbl = { + {.nentry =ARRAY_SIZE (sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry =ARRAY_SIZE (sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry =ARRAY_SIZE (sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, +/* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable =1 , .wr_enable =1 }, + {.rd_enable =1 , .wr_enable =0 } + }, + .clk_inefficiency_factor =105 , + .bw_inefficiency_factor =120 , +}; +static const struct dpu_perf_cfg sm8150_perf_data = { .max_bw_low =12800000 , .max_bw_high =12800000 ,
@@ -1801,6 +1865,28 @@ static const struct dpu_mdss_cfg sc7180_dpu_cfg = { .mdss_irqs = IRQ_SC7180_MASK, }; +static const struct dpu_mdss_cfg sm6115_dpu_cfg = { + .caps = &sm6115_dpu_caps, + .mdp_count =ARRAY_SIZE (sm6115_mdp), + .mdp = sm6115_mdp, + .ctl_count =ARRAY_SIZE (qcm2290_ctl), + .ctl = qcm2290_ctl, + .sspp_count =ARRAY_SIZE (sm6115_sspp), + .sspp = sm6115_sspp, + .mixer_count =ARRAY_SIZE (qcm2290_lm), + .mixer = qcm2290_lm, + .dspp_count =ARRAY_SIZE (qcm2290_dspp), + .dspp = qcm2290_dspp, + .pingpong_count =ARRAY_SIZE (qcm2290_pp), + .pingpong = qcm2290_pp, + .intf_count =ARRAY_SIZE (qcm2290_intf), + .intf = qcm2290_intf, + .vbif_count =ARRAY_SIZE (sdm845_vbif), + .vbif = sdm845_vbif, + .perf = &sm6115_perf_data, + .mdss_irqs =IRQ_SC7180_MASK , +}; +static const struct dpu_mdss_cfg sm8150_dpu_cfg = { .caps = &sm8150_dpu_caps, .mdp_count =ARRAY_SIZE (sdm845_mdp),
@@ -1935,6 +2021,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { { .hw_rev = DPU_HW_VER_510, .dpu_cfg = &sc8180x_dpu_cfg}, { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg}, { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, + { .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg}, { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, };
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +1 -0
@@ -44,6 +44,7 @@#define DPU_HW_VER_510 DPU_HW_VER(5, 1, 1)/* sc8180 */ #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0)/* sm8250 */ #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0)/* sc7180 v1.0 */ +#define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0)/* sm6115|sm4250 */ #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0)/* qcm2290|sm4125 */ #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0)/* sc7280 */
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +1 -0
@@ -1292,6 +1292,7 @@ static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,sc7180-dpu", }, { .compatible = "qcom,sc7280-dpu", }, { .compatible = "qcom,sc8180x-dpu", }, + { .compatible = "qcom,sm6115-dpu", }, { .compatible = "qcom,sm8150-dpu", }, { .compatible = "qcom,sm8250-dpu", }, {}
drivers/gpu/drm/msm/msm_mdss.c +5 -0
@@ -280,6 +280,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)/* UBWC_2_0 */ msm_mdss_setup_ubwc_dec_20 (msm_mdss,0x1e );break ; +case DPU_HW_VER_630 : +/* UBWC_2_0 */ +msm_mdss_setup_ubwc_dec_20 (msm_mdss,0x11f ); +break ;case DPU_HW_VER_720 :msm_mdss_setup_ubwc_dec_40 (msm_mdss,UBWC_3_0 ,6 ,1 ,1 ,1 );break ;
@@ -509,6 +513,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sc7180-mdss" }, { .compatible = "qcom,sc7280-mdss" }, { .compatible = "qcom,sc8180x-mdss" }, + { .compatible = "qcom,sm6115-mdss" }, { .compatible = "qcom,sm8150-mdss" }, { .compatible = "qcom,sm8250-mdss" }, {}
Signature · 1 line
2.25.1
Re: [PATCH 2/2] drm/msm/disp/dpu1: add support for display on SM6115
Quoted 10 lines · Adam Skladowski
Add required display hw catalog changes for SM6115.
Signed-off-by Adam Skladowski <[email protected]>--- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 87 +++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c | 5 ++ 4 files changed, 94 insertions(+)
[skipped]
drivers/gpu/drm/msm/msm_mdss.c static int msm_mdss_enable(struct msm_mdss *msm_mdss) · line 286
Quoted 12 lines
drivers/gpu/drm/msm/msm_mdss.c +4
-0@@ -280,6 +280,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)/* UBWC_2_0 */ msm_mdss_setup_ubwc_dec_20 (msm_mdss,0x1e );break ; +case DPU_HW_VER_630 : +/* UBWC_2_0 */ +msm_mdss_setup_ubwc_dec_20 (msm_mdss,0x11f ); +break ;
According to the vendor dtsi the sm6115 is UBWC 1.0, not 2.0
Could you please doublecheck?
Looks good to me otherwise.
Quoted 11 lines
drivers/gpu/drm/msm/msm_mdss.c +1
-0case DPU_HW_VER_720 :msm_mdss_setup_ubwc_dec_40 (msm_mdss,UBWC_3_0 ,6 ,1 ,1 ,1 );break ;@@ -509,6 +513,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sc7180-mdss" }, { .compatible = "qcom,sc7280-mdss" }, { .compatible = "qcom,sc8180x-mdss" }, + { .compatible = "qcom,sm6115-mdss" }, { .compatible = "qcom,sm8150-mdss" }, { .compatible = "qcom,sm8250-mdss" }, {}
Signature · 2 lines
With best wishes Dmitry
Dmitry Baryshkov
Reviewed-byRe: [PATCH 2/2] drm/msm/disp/dpu1: add support for display on SM6115
Quoted 30 lines · Dmitry Baryshkov
Quoted 10 lines · Adam Skladowski
Add required display hw catalog changes for SM6115.
Signed-off-by Adam Skladowski <[email protected]>---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 87 +++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c | 5 ++4 files changed, 94 insertions(+)[skipped]
drivers/gpu/drm/msm/msm_mdss.c static int msm_mdss_enable(struct msm_mdss · line 287
Quoted 13 lines
drivers/gpu/drm/msm/msm_mdss.c +4
-0@@ -280,6 +280,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) /* UBWC_2_0 */ msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); break; + case DPU_HW_VER_630: + /* UBWC_2_0 */ + msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x11f); + break;According to the vendor dtsi the sm6115 is UBWC 1.0, not 2.0
Quoted 3 lines
Could you please doublecheck?
Looks good to me otherwise.
After doublechecking:
Quoted 13 lines
Quoted 12 lines
case
DPU_HW_VER_720:
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); break;drivers/gpu/drm/msm/msm_mdss.c +1
-0@@ -509,6 +513,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sc7180-mdss" }, { .compatible = "qcom,sc7280-mdss" }, { .compatible = "qcom,sc8180x-mdss" }, + { .compatible = "qcom,sm6115-mdss" }, { .compatible = "qcom,sm8150-mdss" }, { .compatible = "qcom,sm8250-mdss" }, {}
Signature · 2 lines
With best wishes Dmitry