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arm64: dts: apple: Add t600x L1/L2 cache properties and nodes

PATCH Applied Rob Herring 2 participants 2 messages Nov 22, 2022 – Nov 28, 2022

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Device tree bindings Arm/Apple machine support
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Rob Herring

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PATCH 1/1 arm64: dts: apple: Add t600x L1/L2 cache properties and nodes

The t600x CPU nodes are missing the cache hierarchy information. The cache hierarchy on Arm can not be detected and needs to be described in DT. The OS scheduler can make use of this information for scheduling decisions.

The cache size information is based on various articles about the processors. There's also an L3 system level cache (SLC). It's not described here because SLCs typically have some MMIO interface which would need to be described.

Signed-off-by Rob Herring <[email protected]>

---
Based on apple dts changes in linux-next.

This fixes the warning: Unable to detect cache hierarchy for CPU %d

---
 arch/arm64/boot/dts/apple/t6002.dtsi        | 51 +++++++++++++++++++++
 arch/arm64/boot/dts/apple/t600x-common.dtsi | 51 +++++++++++++++++++++
 2 files changed, 102 insertions(+)
arch/arm64/boot/dts/apple/t6002.dtsi +51 -0
index 3b1677ba5262..731d61fbb05f 100644
@@ -29,6 +29,9 @@ cpu_e10: cpu@800 {
 			reg = <0x0 0x800>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0>; /* To be filled by loader */
+			next-level-cache = <&l2_cache_3>;
+			i-cache-size = <0x20000>;
+			d-cache-size = <0x10000>;
 		};
 
 		cpu_e11: cpu@801 {

@@ -37,6 +40,9 @@ cpu_e11: cpu@801 {
 			reg = <0x0 0x801>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0>; /* To be filled by loader */
+			next-level-cache = <&l2_cache_3>;
+			i-cache-size = <0x20000>;
+			d-cache-size = <0x10000>;
 		};
 
 		cpu_p20: cpu@10900 {

@@ -45,6 +51,9 @@ cpu_p20: cpu@10900 {
 			reg = <0x0 0x10900>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0>; /* To be filled by loader */
+			next-level-cache = <&l2_cache_4>;
+			i-cache-size = <0x30000>;
+			d-cache-size = <0x20000>;
 		};
 
 		cpu_p21: cpu@10901 {

@@ -53,6 +62,9 @@ cpu_p21: cpu@10901 {
 			reg = <0x0 0x10901>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0>; /* To be filled by loader */
+			next-level-cache = <&l2_cache_4>;
+			i-cache-size = <0x30000>;
+			d-cache-size = <0x20000>;
 		};
 
 		cpu_p22: cpu@10902 {

@@ -61,6 +73,9 @@ cpu_p22: cpu@10902 {
 			reg = <0x0 0x10902>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0>; /* To be filled by loader */
+			next-level-cache = <&l2_cache_4>;
+			i-cache-size = <0x30000>;
+			d-cache-size = <0x20000>;
 		};
 
 		cpu_p23: cpu@10903 {

@@ -69,6 +84,9 @@ cpu_p23: cpu@10903 {
 			reg = <0x0 0x10903>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0>; /* To be filled by loader */
+			next-level-cache = <&l2_cache_4>;
+			i-cache-size = <0x30000>;
+			d-cache-size = <0x20000>;
 		};
 
 		cpu_p30: cpu@10a00 {

@@ -77,6 +95,9 @@ cpu_p30: cpu@10a00 {
 			reg = <0x0 0x10a00>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0>; /* To be filled by loader */
+			next-level-cache = <&l2_cache_5>;
+			i-cache-size = <0x30000>;
+			d-cache-size = <0x20000>;
 		};
 
 		cpu_p31: cpu@10a01 {

@@ -85,6 +106,9 @@ cpu_p31: cpu@10a01 {
 			reg = <0x0 0x10a01>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0>; /* To be filled by loader */
+			next-level-cache = <&l2_cache_5>;
+			i-cache-size = <0x30000>;
+			d-cache-size = <0x20000>;
 		};
 
 		cpu_p32: cpu@10a02 {

@@ -93,6 +117,9 @@ cpu_p32: cpu@10a02 {
 			reg = <0x0 0x10a02>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0>; /* To be filled by loader */
+			next-level-cache = <&l2_cache_5>;
+			i-cache-size = <0x30000>;
+			d-cache-size = <0x20000>;
 		};
 
 		cpu_p33: cpu@10a03 {

@@ -101,6 +128,30 @@ cpu_p33: cpu@10a03 {
 			reg = <0x0 0x10a03>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0>; /* To be filled by loader */
+			next-level-cache = <&l2_cache_5>;
+			i-cache-size = <0x30000>;
+			d-cache-size = <0x20000>;
+		};
+
+		l2_cache_3: l2-cache-3 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0x400000>;
+		};
+
+		l2_cache_4: l2-cache-4 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0xc00000>;
+		};
+
+		l2_cache_5: l2-cache-5 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0xc00000>;
 		};
 	};
arch/arm64/boot/dts/apple/t600x-common.dtsi +51 -0

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Signature · 1 line
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Applied
#1 lore raw
Quoted 11 lines · Rob Herring

The t600x CPU nodes are missing the cache hierarchy information. The cache hierarchy on Arm can not be detected and needs to be described in DT. The OS scheduler can make use of this information for scheduling decisions.

The cache size information is based on various articles about the processors. There's also an L3 system level cache (SLC). It's not described here because SLCs typically have some MMIO interface which would need to be described.

Signed-off-by Rob Herring <[email protected]>
Quoted 9 lines

---
Based on apple dts changes in linux-next.

This fixes the warning: Unable to detect cache hierarchy for CPU %d

---
 arch/arm64/boot/dts/apple/t6002.dtsi        | 51 +++++++++++++++++++++
 arch/arm64/boot/dts/apple/t600x-common.dtsi | 51 +++++++++++++++++++++
 2 files changed, 102 insertions(+)

[...]

Applied to asahi-soc/dt, thanks!

I probably won't send this one up until the 6.3 cycle; I've rebased our downstream bits/000-devicetree on top so it'll get some downstream testing before going upstream (and in the meantime someone should get around to adding these for the other chips too ;)).

Cheers,
- Hector