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dt-bindings: PCI: qcom: Allow 'dma-coherent' property

PATCH Applied Johan Hovold 4 participants 5 messages Dec 5, 2022 – Dec 6, 2022

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Device tree bindings Arm Qualcomm mailing list PCI PCI native host bridge and endpoint drivers +1 more subsystems
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Johan Hovold

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#0 lore raw

PATCH 1/1 dt-bindings: PCI: qcom: Allow 'dma-coherent' property

Devices on some PCIe buses may be cache coherent and must be marked as such in the devicetree to avoid data corruption.

This is specifically needed on recent Qualcomm platforms like SC8280XP.

Signed-off-by Johan Hovold <[email protected]>

---

Lorenzo, the corresponding SC8280XP DT fix is heading for 6.2 so it would be nice if this one could be merged for 6.2-rc1 (or -rc2) as well to avoid the corresponding DT validation warnings.

Johan

 Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++
 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/pci/qcom,pcie.yaml +2 -0
index 2f851c804bb0..a5859bb3dc28 100644
@@ -62,6 +62,8 @@ properties:
     minItems: 3
     maxItems: 13
 
+  dma-coherent: true
+
   interconnects:
     maxItems: 2
Signature · 1 line
2.37.4
maintainer Acked-by on v1 1/1
#1 lore raw
Quoted 12 lines · Johan Hovold

Devices on some PCIe buses may be cache coherent and must be marked as such in the devicetree to avoid data corruption.

This is specifically needed on recent Qualcomm platforms like SC8280XP.

Signed-off-by Johan Hovold <[email protected]>

---

Lorenzo, the corresponding SC8280XP DT fix is heading for 6.2 so it would be nice if this one could be merged for 6.2-rc1 (or -rc2) as well to avoid the corresponding DT validation warnings.

Quoted 6 lines

Johan

 Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++
 1 file changed, 2 insertions(+)
Acked-by Rob Herring <[email protected]>
maintainer
#2 lore raw
In reply to Johan Hovold
Quoted 11 lines · Johan Hovold

Devices on some PCIe buses may be cache coherent and must be marked as such in the devicetree to avoid data corruption.

This is specifically needed on recent Qualcomm platforms like SC8280XP.

Signed-off-by Johan Hovold <[email protected]>

---

Lorenzo, the corresponding SC8280XP DT fix is heading for 6.2 so it would be nice if this one could be merged for 6.2-rc1 (or -rc2) as well to avoid the corresponding DT validation warnings.

What's the commit base for this patch ? I tried applying to my pci/dt branch to no avail, please let me know and I will merge it.

Lorenzo

Quoted 23 lines

Johan

 Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++
 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/pci/qcom,pcie.yaml +2 -0
index 2f851c804bb0..a5859bb3dc28 100644
@@ -62,6 +62,8 @@ properties:
     minItems: 3
     maxItems: 13
 
+  dma-coherent: true
+
   interconnects:
     maxItems: 2
Signature · 1 line
2.37.4
#3 lore raw
Quoted 9 lines · Lorenzo Pieralisi
Quoted 8 lines · Johan Hovold

Devices on some PCIe buses may be cache coherent and must be marked as such in the devicetree to avoid data corruption.

This is specifically needed on recent Qualcomm platforms like SC8280XP.

Signed-off-by Johan Hovold <[email protected]>

---

Quoted 6 lines
Quoted 3 lines

Lorenzo, the corresponding SC8280XP DT fix is heading for 6.2 so it would be nice if this one could be merged for 6.2-rc1 (or -rc2) as well to avoid the corresponding DT validation warnings.

What's the commit base for this patch ? I tried applying to my pci/dt branch to no avail, please let me know and I will merge it.

That should be pci/qcom which has 3a936b2a5a58 ("dt-bindings: PCI: qcom:
Add SC8280XP/SA8540P interconnects").

Johan