Krait Documentation conversion

Convert kpss-acc driver Documentation to yaml.
The original Documentation was wrong all along. Fix it while we are converting it.
The example was wrong as kpss-acc-v2 should only expose the regs but we don't have any driver that expose additional clocks. The kpss-acc driver is only specific to v1. For this exact reason, split the Documentation to 2 different schema, v1 as clock-controller and v2 for power-controller as per msm-3.10 specification, the exposed regs handle power domains.

Signed-off-by Christian Marangi <[email protected]>

---
  .../bindings/arm/msm/qcom,kpss-acc.txt        | 49 -------------
  .../bindings/clock/qcom,kpss-acc-v1.yaml      | 72 +++++++++++++++++++
  .../bindings/power/qcom,kpss-acc-v2.yaml      | 47 ++++++++++++
  3 files changed, 119 insertions(+), 49 deletions(-)

delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml create mode 100644 Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml

Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt deleted +0 -49

deleted file mode 100644
index 7f696362a4a1..000000000000
@@ -1,49 +0,0 @@
-Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
-
-The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
-There is one ACC register region per CPU within the KPSS remapped region as
-well as an alias register region that remaps accesses to the ACC associated
-with the CPU accessing the region.
-
-PROPERTIES
-
-- compatible:
-	Usage: required
-	Value type: <string>
-	Definition: should be one of:
-			"qcom,kpss-acc-v1"
-			"qcom,kpss-acc-v2"
-
-- reg:
-	Usage: required
-	Value type: <prop-encoded-array>
-	Definition: the first element specifies the base address and size of
-		    the register region. An optional second element specifies
-		    the base address and size of the alias register region.
-
-- clocks:
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: reference to the pll parents.
-
-- clock-names:
-        Usage: required
-        Value type: <stringlist>
-        Definition: must be "pll8_vote", "pxo".
-
-- clock-output-names:
-	Usage: optional
-	Value type: <string>
-	Definition: Name of the output clock. Typically acpuX_aux where X is a
-		    CPU number starting at 0.
-
-Example:
-
-	clock-controller@2088000 {
-		compatible = "qcom,kpss-acc-v2";
-		reg = <0x02088000 0x1000>,
-		      <0x02008000 0x1000>;
-		clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
-		clock-names = "pll8_vote", "pxo";
-		clock-output-names = "acpu0_aux";
-	};

Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml new file +72 -0

new file mode 100644
index 000000000000..a466e4e8aacd
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
+
+maintainers:
+  - Christian Marangi <[email protected]>
+
+description:
+  The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
+  There is one ACC register region per CPU within the KPSS remapped region as
+  well as an alias register region that remaps accesses to the ACC associated
+  with the CPU accessing the region. ACC v1 is currently used as a
+  clock-controller for enabling the cpu and hanling the aux clocks.
+
+properties:
+  compatible:
+    const: qcom,kpss-acc-v1
+
+  reg:
+    items:
+      - description: Base address and size of the register region
+      - description: Optional base address and size of the alias register region
+    minItems: 1
+
+  clocks:
+    minItems: 2
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: pll8_vote
+      - const: pxo
+
+  clock-output-names:
+    description: Name of the aux clock. Krait can have at most 4 cpu.
+    enum:
+      - acpu0_aux
+      - acpu1_aux
+      - acpu2_aux
+      - acpu3_aux
+
+  '#clock-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - clock-output-names
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+
+    clock-controller@2088000 {
+      compatible = "qcom,kpss-acc-v1";
+      reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+      clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+      clock-names = "pll8_vote", "pxo";
+      clock-output-names = "acpu0_aux";
+      #clock-cells = <0>;
+    };
+
+...

Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml new file +25 -0

new file mode 100644
index 000000000000..91af95569ae6
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/qcom,kpss-acc-v2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v2
+
+maintainers:
+  - Christian Marangi <[email protected]>
+
+description:
+  The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
+  There is one ACC register region per CPU within the KPSS remapped region as
+  well as an alias register region that remaps accesses to the ACC associated
+  with the CPU accessing the region. ACC v2 is currently used as a
+  power-controller for enabling the cpu.
+
+properties:
+  compatible:
+    const: qcom,kpss-acc-v2
+
+  reg:
+    items:
+      - description: Base address and size of the register region

Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml new file +12 -0

+
+additionalProperties: false
+
+examples:
+  - |
+    power-controller@f9088000 {
+      compatible = "qcom,kpss-acc-v2";
+      reg = <0xf9088000 0x1000>,
+            <0xf9008000 0x1000>;
+      #power-domain-cells = <0>;
+    };
+...

Quoted 193 lines · Christian Marangi

Convert kpss-acc driver Documentation to yaml.
The original Documentation was wrong all along. Fix it while we are converting it.
The example was wrong as kpss-acc-v2 should only expose the regs but we don't have any driver that expose additional clocks. The kpss-acc driver is only specific to v1. For this exact reason, split the Documentation to 2 different schema, v1 as clock-controller and v2 for power-controller as per msm-3.10 specification, the exposed regs handle power domains.

Signed-off-by Christian Marangi <[email protected]>

---
  .../bindings/arm/msm/qcom,kpss-acc.txt        | 49 -------------
  .../bindings/clock/qcom,kpss-acc-v1.yaml      | 72 +++++++++++++++++++
  .../bindings/power/qcom,kpss-acc-v2.yaml      | 47 ++++++++++++
  3 files changed, 119 insertions(+), 49 deletions(-)

delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml create mode 100644 Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml

Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt deleted +0 -49

deleted file mode 100644
index 7f696362a4a1..000000000000
@@ -1,49 +0,0 @@
-Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
-
-The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
-There is one ACC register region per CPU within the KPSS remapped region as
-well as an alias register region that remaps accesses to the ACC associated
-with the CPU accessing the region.
-
-PROPERTIES
-
-- compatible:
-	Usage: required
-	Value type: <string>
-	Definition: should be one of:
-			"qcom,kpss-acc-v1"
-			"qcom,kpss-acc-v2"
-
-- reg:
-	Usage: required
-	Value type: <prop-encoded-array>
-	Definition: the first element specifies the base address and size of
-		    the register region. An optional second element specifies
-		    the base address and size of the alias register region.
-
-- clocks:
-        Usage: required
-        Value type: <prop-encoded-array>
-        Definition: reference to the pll parents.
-
-- clock-names:
-        Usage: required
-        Value type: <stringlist>
-        Definition: must be "pll8_vote", "pxo".
-
-- clock-output-names:
-	Usage: optional
-	Value type: <string>
-	Definition: Name of the output clock. Typically acpuX_aux where X is a
-		    CPU number starting at 0.
-
-Example:
-
-	clock-controller@2088000 {
-		compatible = "qcom,kpss-acc-v2";
-		reg = <0x02088000 0x1000>,
-		      <0x02008000 0x1000>;
-		clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
-		clock-names = "pll8_vote", "pxo";
-		clock-output-names = "acpu0_aux";
-	};

Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml new file +72 -0

new file mode 100644
index 000000000000..a466e4e8aacd
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
+
+maintainers:
+  - Christian Marangi <[email protected]>
+
+description:
+  The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
+  There is one ACC register region per CPU within the KPSS remapped region as
+  well as an alias register region that remaps accesses to the ACC associated
+  with the CPU accessing the region. ACC v1 is currently used as a
+  clock-controller for enabling the cpu and hanling the aux clocks.
+
+properties:
+  compatible:
+    const: qcom,kpss-acc-v1
+
+  reg:
+    items:
+      - description: Base address and size of the register region
+      - description: Optional base address and size of the alias register region
+    minItems: 1
+
+  clocks:
+    minItems: 2
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: pll8_vote
+      - const: pxo
+
+  clock-output-names:
+    description: Name of the aux clock. Krait can have at most 4 cpu.
+    enum:
+      - acpu0_aux
+      - acpu1_aux
+      - acpu2_aux
+      - acpu3_aux
+
+  '#clock-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - clock-output-names
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+
+    clock-controller@2088000 {
+      compatible = "qcom,kpss-acc-v1";
+      reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+      clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+      clock-names = "pll8_vote", "pxo";
+      clock-output-names = "acpu0_aux";
+      #clock-cells = <0>;
+    };
+
+...

Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml new file +34 -0

new file mode 100644
index 000000000000..91af95569ae6
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/qcom,kpss-acc-v2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v2
+
+maintainers:
+  - Christian Marangi <[email protected]>
+
+description:
+  The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
+  There is one ACC register region per CPU within the KPSS remapped region as
+  well as an alias register region that remaps accesses to the ACC associated
+  with the CPU accessing the region. ACC v2 is currently used as a
+  power-controller for enabling the cpu.
+
+properties:
+  compatible:
+    const: qcom,kpss-acc-v2
+
+  reg:
+    items:
+      - description: Base address and size of the register region
+      - description: Optional base address and size of the alias register region
+    minItems: 1
+
+  '#power-domain-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg

Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml line 35

Quoted 1 line

Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml new file +1 -0

+  - '#power-domain-cells'

This dictates that if at some point we implement the kps-acc-v2 driver, it will return a single power domain. I can not confirm that this would be the case. I see that you want to migrate from the clock-controller as the acc-v2 doesn't provide clocks. I'd suggest instead using the neutral power-manager@... node name. It doesn't demand anything, so we can drop the (unused and unsupported) #power-domain-cells property.

Quoted 12 lines

Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml new file +12 -0

+
+additionalProperties: false
+
+examples:
+  - |
+    power-controller@f9088000 {
+      compatible = "qcom,kpss-acc-v2";
+      reg = <0xf9088000 0x1000>,
+            <0xf9008000 0x1000>;
+      #power-domain-cells = <0>;
+    };
+...

Signature · 2 lines

With best wishes
Dmitry

Rework kpss-gcc driver Documentation to yaml Documentation and move it to clock as it's a clock-controller.
The current kpss-gcc Documentation have major problems and can't be converted directly. Introduce various changes to the original Documentation.

Add #clock-cells additional binding as this clock outputs a static clk named acpu_l2_aux with supported compatible.
Only some compatible require and outputs a clock, for the others, set only the reg as a required binding to correctly export the kpss-gcc registers. As the reg is shared also add the required syscon compatible.

Signed-off-by Christian Marangi <[email protected]>

---
 .../bindings/arm/msm/qcom,kpss-gcc.txt        | 44 ----------
 .../bindings/clock/qcom,kpss-gcc.yaml         | 88 +++++++++++++++++++
 2 files changed, 88 insertions(+), 44 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml

Fix dtbs_check warning now that we have a correct kpss-gcc yaml schema. Add additional qcom,kpss-gcc compatible to differentiate devices where kpss-gcc should provide a clk and where kpss-gcc should just provide the registers and the syscon phandle.
Add missing #clock-cells and remove useless clock-output-names for ipq806x.
Add missing bindings for msm8960 and apq8064 kpss-gcc node.

Signed-off-by Christian Marangi <[email protected]>

---
  arch/arm/boot/dts/qcom-apq8064.dtsi | 5 ++++-
  arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++--
  arch/arm/boot/dts/qcom-mdm9615.dtsi | 2 +-
  arch/arm/boot/dts/qcom-msm8660.dtsi | 2 +-
  arch/arm/boot/dts/qcom-msm8960.dtsi | 5 ++++-
  5 files changed, 12 insertions(+), 6 deletions(-)

arch/arm/boot/dts/qcom-apq8064.dtsi +4 -1

index 1f3e0aa9ab0c..1e68b42acb91 100644
@@ -880,8 +880,11 @@ mmcc: clock-controller@4000000 {
  		};
 
  		l2cc: clock-controller@2011000 {
-			compatible = "qcom,kpss-gcc", "syscon";
+			compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
  			reg = <0x2011000 0x1000>;
+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+			clock-names = "pll8_vote", "pxo";
+			#clock-cells = <0>;
  		};
 
  		rpm: rpm@108000 {

arch/arm/boot/dts/qcom-ipq8064.dtsi +2 -2

index 7e784b0995da..de87fcaaa836 100644
@@ -570,11 +570,11 @@ IRQ_TYPE_EDGE_RISING)>,
  		};
 
  		l2cc: clock-controller@2011000 {
-			compatible = "qcom,kpss-gcc", "syscon";
+			compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
  			reg = <0x02011000 0x1000>;
  			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
  			clock-names = "pll8_vote", "pxo";
-			clock-output-names = "acpu_l2_aux";
+			#clock-cells = <0>;
  		};
 
  		acc0: clock-controller@2088000 {

arch/arm/boot/dts/qcom-mdm9615.dtsi +1 -1

index b0fe1d95d88f..61dfec3b9037 100644
@@ -116,7 +116,7 @@ lcc: clock-controller@28000000 {
  		};
 
  		l2cc: clock-controller@2011000 {
-			compatible = "qcom,kpss-gcc", "syscon";
+			compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
  			reg = <0x02011000 0x1000>;
  		};
 

arch/arm/boot/dts/qcom-msm8660.dtsi +1 -1

index 86f76d0feff4..f601b40ebcf4 100644
@@ -473,7 +473,7 @@ pm8058_led133: led@133 {
  		};
 
  		l2cc: clock-controller@2082000 {
-			compatible = "qcom,kpss-gcc", "syscon";
+			compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon";
  			reg = <0x02082000 0x1000>;
  		};
 

arch/arm/boot/dts/qcom-msm8960.dtsi +4 -1

index 7debf9db7cb1..3bd07cac315b 100644
@@ -183,8 +183,11 @@ clock-controller@4000000 {
  		};
 
  		l2cc: clock-controller@2011000 {
-			compatible = "qcom,kpss-gcc", "syscon";
+			compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
  			reg = <0x2011000 0x1000>;
+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+			clock-names = "pll8_vote", "pxo";
+			#clock-cells = <0>;
  		};
 
  		rpm: rpm@108000 {

Fix dtbs_check warning now that we have a correct kpss-acc-v1 yaml schema.

Add missing clocks, clock-names, clock-output-names and #clock-cells bindings for each kpss-acc-v1 clock-controller to reflect Documentation schema.

Signed-off-by Christian Marangi <[email protected]>

---
  arch/arm/boot/dts/qcom-apq8064.dtsi | 16 ++++++++++++++++
  arch/arm/boot/dts/qcom-ipq8064.dtsi |  8 ++++++++
  arch/arm/boot/dts/qcom-msm8960.dtsi |  8 ++++++++
  3 files changed, 32 insertions(+)

arch/arm/boot/dts/qcom-apq8064.dtsi +16 -0

index 1e68b42acb91..af84f2d350ef 100644
@@ -389,21 +389,37 @@ timer@200a000 {
  		acc0: clock-controller@2088000 {
  			compatible = "qcom,kpss-acc-v1";
  			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+			clock-names = "pll8_vote", "pxo";
+			clock-output-names = "acpu0_aux";
+			#clock-cells = <0>;
  		};
 
  		acc1: clock-controller@2098000 {
  			compatible = "qcom,kpss-acc-v1";
  			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+			clock-names = "pll8_vote", "pxo";
+			clock-output-names = "acpu1_aux";
+			#clock-cells = <0>;
  		};
 
  		acc2: clock-controller@20a8000 {
  			compatible = "qcom,kpss-acc-v1";
  			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+			clock-names = "pll8_vote", "pxo";
+			clock-output-names = "acpu2_aux";
+			#clock-cells = <0>;
  		};
 
  		acc3: clock-controller@20b8000 {
  			compatible = "qcom,kpss-acc-v1";
  			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+			clock-names = "pll8_vote", "pxo";
+			clock-output-names = "acpu3_aux";
+			#clock-cells = <0>;
  		};
 
  		saw0: power-controller@2089000 {

arch/arm/boot/dts/qcom-ipq8064.dtsi +8 -0

index de87fcaaa836..e796094a7af5 100644
@@ -580,6 +580,10 @@ l2cc: clock-controller@2011000 {
  		acc0: clock-controller@2088000 {
  			compatible = "qcom,kpss-acc-v1";
  			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+			clock-names = "pll8_vote", "pxo";
+			clock-output-names = "acpu0_aux";
+			#clock-cells = <0>;
  		};
 
  		saw0: regulator@2089000 {

@@ -591,6 +595,10 @@ saw0: regulator@2089000 {
  		acc1: clock-controller@2098000 {
  			compatible = "qcom,kpss-acc-v1";
  			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+			clock-names = "pll8_vote", "pxo";
+			clock-output-names = "acpu1_aux";
+			#clock-cells = <0>;
  		};
 
  		saw1: regulator@2099000 {

arch/arm/boot/dts/qcom-msm8960.dtsi +8 -0

index 3bd07cac315b..4fd56d85be3f 100644
@@ -208,11 +208,19 @@ regulators {
  		acc0: clock-controller@2088000 {
  			compatible = "qcom,kpss-acc-v1";
  			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+			clock-names = "pll8_vote", "pxo";
+			clock-output-names = "acpu0_aux";
+			#clock-cells = <0>;
  		};
 
  		acc1: clock-controller@2098000 {
  			compatible = "qcom,kpss-acc-v1";
  			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+			clock-names = "pll8_vote", "pxo";
+			clock-output-names = "acpu1_aux";
+			#clock-cells = <0>;
  		};
 
  		saw0: regulator@2089000 {

Fix dtbs_check warning now that we have a correct kpss-acc-v2 yaml schema.
Change acc node naming to power-controller and add missing binding #power-domain-cells for each kpss-acc-v2 power-controller to reflect Documentation schema.

Signed-off-by Christian Marangi <[email protected]>

---
  arch/arm/boot/dts/qcom-apq8084.dtsi | 12 ++++++++----
  arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++++----
  arch/arm/boot/dts/qcom-msm8974.dtsi | 12 ++++++++----
  3 files changed, 24 insertions(+), 12 deletions(-)