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add VTM nodes to TI's K3 SoCs

PATCH Applied Bryan Brattlof 3 participants 13 messages Jan 20, 2023 – Jun 15, 2023

Subsystems (2)
Device tree bindings Arm/Texas Instruments K3 architecture

v2 of 3 Applied Latest is v3 →

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Bryan Brattlof

author
#0 lore raw

v2 cover add VTM nodes to TI's K3 SoCs

Hello again everyone!

This patch series adds in basic VTM nodes for all of TI's K3 SoCs. As of right now these do not do much other than add thermal entries into the sysfs directory and power down the device once it's exceeded a critical temperature.

Changes from v1:
- Fixed indexing of thermal nodes[0]

[0] https://lore.kernel.org/all/[email protected]/

Thanks for reviewing!
~Bryan

Bryan Brattlof (6):
arm64: dts: ti: k3-am64-main: add VTM node
arm64: dts: ti: k3-am62-wakeup: add VTM node
arm64: dts: ti: k3-j721e-mcu-wakeup: add VTM node
arm64: dts: ti: k3-j721s2-mcu-wakeup: add VTM node
arm64: dts: ti: k3-j7200-mcu-wakeup: add VTM node
arm64: dts: ti: k3-am62a-wakeup: add VTM node

 arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi   |  33 ++++++
 arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi    |   8 ++
 arch/arm64/boot/dts/ti/k3-am62.dtsi           |   6 +-
 arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi  |  47 ++++++++
 arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi   |   8 ++
 arch/arm64/boot/dts/ti/k3-am62a.dtsi          |   2 +
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi      |   8 ++
 arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi   |  33 ++++++
 arch/arm64/boot/dts/ti/k3-am64.dtsi           |   3 +
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      |   8 ++
 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi  |  47 ++++++++
 arch/arm64/boot/dts/ti/k3-j7200.dtsi          |   2 +
 .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi      |   9 ++
 arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi  |  75 +++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e.dtsi          |   2 +
 .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi     |   8 ++
 arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi | 103 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721s2.dtsi         |   2 +
 18 files changed, 403 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi

base-commit: 1b929c02afd37871d5afb9d498426f83432e71c2

Signature · 1 line
2.39.0
author
#1 lore raw

PATCH v2 1/6 arm64: dts: ti: k3-am64-main: add VTM node

The am64x supports a single VTM module which is located in the main domain with two associated temperature monitors located at different hot spots on the die.

Signed-off-by Bryan Brattlof <[email protected]>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi    |  8 +++++
 arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi | 33 +++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am64.dtsi         |  3 ++
 3 files changed, 44 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi
arch/arm64/boot/dts/ti/k3-am64-main.dtsi +8 -0
index 5e8036f32d79d..dc8c1c6021630 100644
@@ -1392,4 +1392,12 @@ elm0: ecc@25010000 {
 		clock-names = "fck";
 		status = "disabled";
 	};
+
+	main_vtm0: temperature-sensor@b00000 {
+		compatible = "ti,j7200-vtm";
+		reg = <0x00 0xb00000 0x00 0x400>,
+		      <0x00 0xb01000 0x00 0x400>;
+		power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+		#thermal-sensor-cells = <1>;
+	};
 };
arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi new file +33 -0
new file mode 100644
index 0000000000000..036db56ba7977
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+	main0_thermal: main0-thermal {
+		polling-delay-passive = <250>;	/* milliSeconds */
+		polling-delay = <500>;		/* milliSeconds */
+		thermal-sensors = <&main_vtm0 0>;
+
+		trips {
+			main0_crit: main0-crit {
+				temperature = <105000>;	/* milliCelsius */
+				hysteresis = <2000>;	/* milliCelsius */
+				type = "critical";
+			};
+		};
+	};
+
+	main1_thermal: main1-thermal {
+		polling-delay-passive = <250>;	/* milliSeconds */
+		polling-delay = <500>;		/* milliSeconds */
+		thermal-sensors = <&main_vtm0 1>;
+
+		trips {
+			main1_crit: main1-crit {
+				temperature = <105000>;	/* milliCelsius */
+				hysteresis = <2000>;	/* milliCelsius */
+				type = "critical";
+			};
+		};
+	};
+};
arch/arm64/boot/dts/ti/k3-am64.dtsi +3 -0
index c858725133af4..3ac0545cbfe6f 100644
@@ -69,6 +69,7 @@ cbass_main: bus@f4000 {
 			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
 			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
 			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
 			 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
 			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
 			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */

@@ -105,6 +106,8 @@ cbass_mcu: bus@4000000 {
 			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
 		};
 	};
+
+	#include "k3-am64-thermal.dtsi"
 };
 
 /* Now include the peripherals for each bus segments */
Signature · 1 line
2.39.0
Tested-by on v2 1/6
#2 lore raw

Re: [PATCH v2 1/6] arm64: dts: ti: k3-am64-main: add VTM node

Hi

Quoted 5 lines

The am64x supports a single VTM module which is located in the main domain with two associated temperature monitors located at different hot spots on the die.

Signed-off-by Bryan Brattlof <[email protected]>
Tested-by Christian Gmeiner <[email protected]>
Signature · 5 lines
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info/privacypolicy
author
#3 lore raw

PATCH v2 2/6 arm64: dts: ti: k3-am62-wakeup: add VTM node

In reply to Bryan Brattlof

The am62x supports a single Voltage and Thermal Management (VTM) module located in the wakeup domain with two associated temperature monitors located in hot spots of the die.

Signed-off-by Bryan Brattlof <[email protected]>
---
 arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi | 33 +++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi  |  8 +++++
 arch/arm64/boot/dts/ti/k3-am62.dtsi         |  6 +++-
 3 files changed, 46 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi
arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi new file +33 -0
new file mode 100644
index 0000000000000..a358757e26f07
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+	main0_thermal: main0-thermal {
+		polling-delay-passive = <250>;	/* milliSeconds */
+		polling-delay = <500>;		/* milliSeconds */
+		thermal-sensors = <&wkup_vtm0 0>;
+
+		trips {
+			main0_crit: main0-crit {
+				temperature = <105000>;	/* milliCelsius */
+				hysteresis = <2000>;	/* milliCelsius */
+				type = "critical";
+			};
+		};
+	};
+
+	main1_thermal: main1-thermal {
+		polling-delay-passive = <250>;	/* milliSeconds */
+		polling-delay = <500>;		/* milliSeconds */
+		thermal-sensors = <&wkup_vtm0 1>;
+
+		trips {
+			main1_crit: main1-crit {
+				temperature = <105000>;	/* milliCelsius */
+				hysteresis = <2000>;	/* milliCelsius */
+				type = "critical";
+			};
+		};
+	};
+};
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +8 -0
index 38dced6b4fef9..91ec9887ac6d1 100644
@@ -40,4 +40,12 @@ wkup_i2c0: i2c@2b200000 {
 		clock-names = "fck";
 		status = "disabled";
 	};
+
+	wkup_vtm0: temperature-sensor@b00000 {
+		compatible = "ti,j7200-vtm";
+		reg = <0x00 0xb00000 0x00 0x400>,
+		      <0x00 0xb01000 0x00 0x400>;
+		power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+		#thermal-sensor-cells = <1>;
+	};
 };
arch/arm64/boot/dts/ti/k3-am62.dtsi +5 -1
index 37fcbe7a3c336..74cf1b4d7a6ad 100644
@@ -80,6 +80,7 @@ cbass_main: bus@f0000 {
 			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
 
 			 /* Wakeup Domain Range */
+			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
 			 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
 			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
 

@@ -94,10 +95,13 @@ cbass_wakeup: bus@2b000000 {
 			compatible = "simple-bus";
 			#address-cells = <2>;
 			#size-cells = <2>;
-			ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
+				 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
 				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
 		};
 	};
+
+	#include "k3-am62-thermal.dtsi"
 };
 
 /* Now include the peripherals for each bus segments */
Signature · 1 line
2.39.0
maintainer
#4 lore raw

Re: [PATCH v2 2/6] arm64: dts: ti: k3-am62-wakeup: add VTM node

Hi Bryan,

arch/arm64/boot/dts/ti/k3-am62.dtsi cbass_wakeup: bus@2b000000 { · line 98

Quoted 6 lines · Bryan Brattlof
arch/arm64/boot/dts/ti/k3-am62.dtsi +1 -1
@@ -94,10 +95,13 @@ cbass_wakeup: bus@2b000000 {
 			compatible = "simple-bus";
 			#address-cells = <2>;
 			#size-cells = <2>;
-			ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */

You would need to update unit address in node name as well:

			cbass_wakeup: bus@b00000 {

arch/arm64/boot/dts/ti/k3-am62.dtsi cbass_wakeup: bus@2b000000 { · line 105

Quoted 7 lines
arch/arm64/boot/dts/ti/k3-am62.dtsi +3 -0
+				 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
 				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
 		};
 	};
+
+	#include "k3-am62-thermal.dtsi"
 };

Regards
Vignesh

author
#5 lore raw

Re: [PATCH v2 2/6] arm64: dts: ti: k3-am62-wakeup: add VTM node

Hi Vignesh!

On January 28, 2023 thus sayeth Raghavendra, Vignesh:

Quoted 11 lines

Hi Bryan,

arch/arm64/boot/dts/ti/k3-am62.dtsi cbass_wakeup: bus@2b000000 { · line 98

Quoted 6 lines · Bryan Brattlof
arch/arm64/boot/dts/ti/k3-am62.dtsi +1 -1
@@ -94,10 +95,13 @@ cbass_wakeup: bus@2b000000 {
 			compatible = "simple-bus";
 			#address-cells = <2>;
 			#size-cells = <2>;
-			ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */

You would need to update unit address in node name as well:

Quoted 1 line
			cbass_wakeup: bus@b00000 {

Ah! I missed that. I'll get this fixed

~Bryan

#6 lore raw

Re: [PATCH v2 2/6] arm64: dts: ti: k3-am62-wakeup: add VTM node

Quoted 16 lines

Hi Vignesh!

On January 28, 2023 thus sayeth Raghavendra, Vignesh:

Quoted 11 lines

Hi Bryan,

arch/arm64/boot/dts/ti/k3-am62.dtsi cbass_wakeup: bus@2b000000 { · line 98

Quoted 6 lines · Bryan Brattlof
arch/arm64/boot/dts/ti/k3-am62.dtsi +1 -1
@@ -94,10 +95,13 @@ cbass_wakeup: bus@2b000000 {
                    compatible = "simple-bus";
                    #address-cells = <2>;
                    #size-cells = <2>;
-                   ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+                   ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */

You would need to update unit address in node name as well:

Quoted 1 line
                      cbass_wakeup: bus@b00000 {
Quoted 1 line

Ah! I missed that. I'll get this fixed

Any update on this? Would be great if these changes could make it into the next merge window.

Signature · 5 lines
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info/privacypolicy
author
#7 lore raw

Re: [PATCH v2 2/6] arm64: dts: ti: k3-am62-wakeup: add VTM node

Hi Christian!

On April 3, 2023 thus sayeth Christian Gmeiner:

Quoted 16 lines
Quoted 16 lines

Hi Vignesh!

On January 28, 2023 thus sayeth Raghavendra, Vignesh:

Quoted 12 lines

Hi Bryan,

arch/arm64/boot/dts/ti/k3-am62.dtsi cbass_wakeup: bus@2b000000 { · line 98

Quoted 6 lines · Bryan Brattlof
arch/arm64/boot/dts/ti/k3-am62.dtsi +1 -1
@@ -94,10 +95,13 @@ cbass_wakeup: bus@2b000000 {
                    compatible = "simple-bus";
                    #address-cells = <2>;
                    #size-cells = <2>;
-                   ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+                   ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */

You would need to update unit address in node name as well:

                      cbass_wakeup: bus@b00000 {
Quoted 5 lines
Quoted 1 line

Ah! I missed that. I'll get this fixed

Any update on this? Would be great if these changes could make it into the next merge window.

You got me :) I let this fall off my radar... I'll send out v3 by today or tomorrow to restart the review process.

Thank you for reviewing and for the reminder Christian ~Bryan

author
#8 lore raw

PATCH v2 3/6 arm64: dts: ti: k3-j721e-mcu-wakeup: add VTM node

In reply to Bryan Brattlof

The j721e supports a single Voltage and Thermal Management (VTM) module located in the wakeup domain with five associated temperature monitors located in various hot spots on the die.

Signed-off-by Bryan Brattlof <[email protected]>
---
 .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi      |  9 +++
 arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi  | 75 +++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e.dtsi          |  2 +
 3 files changed, 86 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +9 -0
index 8ac78034d5d6b..a6472a077a8cd 100644
@@ -425,4 +425,13 @@ mcu_mcan1: can@40568000 {
 		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 		status = "disabled";
 	};
+
+	wkup_vtm0: temperature-sensor@42040000 {
+		compatible = "ti,j721e-vtm";
+		reg = <0x00 0x42040000 0x00 0x350>,
+		      <0x00 0x42050000 0x00 0x350>,
+		      <0x00 0x43000300 0x00 0x10>;
+		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+		#thermal-sensor-cells = <1>;
+	};
 };
arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi new file +75 -0

75 lines not on this page · raw message

arch/arm64/boot/dts/ti/k3-j721e.dtsi +2 -0
index 0e23886c9fd1d..934dffbc136f3 100644
@@ -181,6 +181,8 @@ cbass_mcu_wakeup: bus@28380000 {
 				 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
 		};
 	};
+
+	#include "k3-j721e-thermal.dtsi"
 };
 
 /* Now include the peripherals for each bus segments */
Signature · 1 line
2.39.0
author
#9 lore raw

PATCH v2 4/6 arm64: dts: ti: k3-j721s2-mcu-wakeup: add VTM node

In reply to Bryan Brattlof

The j721s2 supports a single Voltage and Thermal Management (VTM) device located in the wakeup domain with seven associated temperature monitors located in various hot spots on the die.

Signed-off-by Bryan Brattlof <[email protected]>
---
 .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi     |   8 ++
 arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi | 103 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721s2.dtsi         |   2 +
 3 files changed, 113 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +8 -0
index 0af242aa98162..b31a0a812f83f 100644
@@ -306,4 +306,12 @@ cpts@3d000 {
 			ti,cpts-periodic-outputs = <2>;
 		};
 	};
+
+	wkup_vtm0: temperature-sensor@42040000 {
+		compatible = "ti,j7200-vtm";
+		reg = <0x0 0x42040000 0x0 0x350>,
+		      <0x0 0x42050000 0x0 0x350>;
+		power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
+		#thermal-sensor-cells = <1>;
+	};
 };
arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi new file +103 -0

103 lines not on this page · raw message

arch/arm64/boot/dts/ti/k3-j721s2.dtsi +2 -0
index 7b930a85a29d6..0c8234a4d7978 100644
@@ -161,6 +161,8 @@ cbass_mcu_wakeup: bus@28380000 {
 		};
 
 	};
+
+	#include "k3-j721s2-thermal.dtsi"
 };
 
 /* Now include peripherals from each bus segment */
Signature · 1 line
2.39.0
author
#10 lore raw

PATCH v2 5/6 arm64: dts: ti: k3-j7200-mcu-wakeup: add VTM node

In reply to Bryan Brattlof

The j7200 supports a single Voltage and Thermal Management (VTM) device located in the wakeup domain with three associated temperature monitors located in various hot spots on the die.

Signed-off-by Bryan Brattlof <[email protected]>
---
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      |  8 ++++
 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi  | 47 +++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j7200.dtsi          |  2 +
 3 files changed, 57 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +8 -0
index fe669deba4896..1eb16542bf9f1 100644
@@ -399,4 +399,12 @@ rng: rng@40910000 {
 			status = "disabled"; /* Used by OP-TEE */
 		};
 	};
+
+	wkup_vtm0: temperature-sensor@42040000 {
+		compatible = "ti,j7200-vtm";
+		reg = <0x00 0x42040000 0x00 0x350>,
+		      <0x00 0x42050000 0x00 0x350>;
+		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+		#thermal-sensor-cells = <1>;
+	};
 };
arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi new file +47 -0

47 lines not on this page · raw message

arch/arm64/boot/dts/ti/k3-j7200.dtsi +2 -0
index b6da0454cc5bd..2abc872ecec08 100644
@@ -168,6 +168,8 @@ cbass_mcu_wakeup: bus@28380000 {
 				 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
 		};
 	};
+
+	#include "k3-j7200-thermal.dtsi"
 };
 
 /* Now include the peripherals for each bus segments */
Signature · 1 line
2.39.0
author
#11 lore raw

PATCH v2 6/6 arm64: dts: ti: k3-am62a-wakeup: add VTM node

In reply to Bryan Brattlof

The am62ax supports a single Voltage and Thermal Management (VTM) device located in the wakeup domain with three associated temperature monitors located in various hot spots of the die.

Signed-off-by Bryan Brattlof <[email protected]>
---
 arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi | 47 ++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi  |  8 ++++
 arch/arm64/boot/dts/ti/k3-am62a.dtsi         |  2 +
 3 files changed, 57 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi
arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi new file +47 -0
new file mode 100644
index 0000000000000..85ce545633ea5
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+	main0_thermal: main0-thermal {
+		polling-delay-passive = <250>;	/* milliSeconds */
+		polling-delay = <500>;		/* milliSeconds */
+		thermal-sensors = <&wkup_vtm0 0>;
+
+		trips {
+			main0_crit: main0-crit {
+				temperature = <125000>;	/* milliCelsius */
+				hysteresis = <2000>;	/* milliCelsius */
+				type = "critical";
+			};
+		};
+	};
+
+	main1_thermal: main1-thermal {
+		polling-delay-passive = <250>;	/* milliSeconds */
+		polling-delay = <500>;		/* milliSeconds */
+		thermal-sensors = <&wkup_vtm0 1>;
+
+		trips {
+			main1_crit: main1-crit {
+				temperature = <125000>;	/* milliCelsius */
+				hysteresis = <2000>;	/* milliCelsius */
+				type = "critical";
+			};
+		};
+	};
+
+	main2_thermal: main2-thermal {
+	       polling-delay-passive = <250>;	/* milliSeconds */
+	       polling-delay = <500>;		/* milliSeconds */
+	       thermal-sensors = <&wkup_vtm0 2>;
+
+		trips {
+			main2_crit: main2-crit {
+				temperature = <125000>;	/* milliCelsius */
+				hysteresis = <2000>;	/* milliCelsius */
+				type = "critical";
+			};
+		};
+	};
+};
arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +8 -0
index 81d984414fd4a..9bdafead7199a 100644
@@ -51,4 +51,12 @@ wkup_rtc0: rtc@2b1f0000 {
 		wakeup-source;
 		status = "disabled";
 	};
+
+	wkup_vtm0: temperature-sensor@b00000 {
+		compatible = "ti,j7200-vtm";
+		reg = <0x00 0xb00000 0x00 0x400>,
+		      <0x00 0xb01000 0x00 0x400>;
+		power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+		#thermal-sensor-cells = <1>;
+	};
 };
arch/arm64/boot/dts/ti/k3-am62a.dtsi +2 -0
index 6eb87c3f9f3ce..84e8adeeebb61 100644
@@ -114,6 +114,8 @@ cbass_wakeup: bus@b00000 {
 				 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
 		};
 	};
+
+	#include "k3-am62a-thermal.dtsi"
 };
 
 /* Now include the peripherals for each bus segments */
Signature · 1 line
2.39.0
maintainer Applied
#12 lore raw
In reply to Bryan Brattlof

Hi Bryan Brattlof,

Quoted 9 lines · Bryan Brattlof

This patch series adds in basic VTM nodes for all of TI's K3 SoCs. As of right now these do not do much other than add thermal entries into the sysfs directory and power down the device once it's exceeded a critical temperature.

Changes from v1:
- Fixed indexing of thermal nodes[0]

[...]

I have applied the following to branch ti-k3-dts-next on [1]. Thank you!

[1/6] arm64: dts: ti: k3-am64-main: add VTM node

      commit: 96135297a76003faae68e3aa86e2e19851510eb9
[2/6] arm64: dts: ti: k3-am62-wakeup: add VTM node
      commit: bbb6dc62505acf6fcb80573f7e7a59875c33be0d
[3/6] arm64: dts: ti: k3-j721e-mcu-wakeup: add VTM node
      commit: 8fb4e87c55979c1f6691346205b884d1863ca6db
[4/6] arm64: dts: ti: k3-j721s2-mcu-wakeup: add VTM node
      commit: d148e3fe52c855b1709ed031eff6e63e87ad0372
[5/6] arm64: dts: ti: k3-j7200-mcu-wakeup: add VTM node
      commit: 4aa6586a9720849527379c415d0977f0d5bcfcac
[6/6] arm64: dts: ti: k3-am62a-wakeup: add VTM node
      commit: 225312fbaf37bb283dbc92a0a1d4dfe58629ab64

All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh