Add ASPEED AST2600 I2Cv2 controller driver

AST2600 support new register set for I2Cv2 controller, add bindings document to support driver of i2cv2 new register mode controller.

+? clock-frequency:
+??? description:
+????? Desired I2C bus clock frequency in Hz. default 100khz. +
+? multi-master:
+??? type: boolean
+??? description:
+????? states that there is another master active on this bus

+? aspeed,gr:
+??? $ref: /schemas/types.yaml#/definitions/phandle +??? description: The phandle of i2c global register node.

-----Original Message-----
From: Jeremy Kerr <[email protected]>
Sent: Monday, February 20, 2023 4:29 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2

Hi Ryan,

Quoted 2 lines

AST2600 support new register set for I2Cv2 controller, add bindings document to support driver of i2cv2 new register mode controller.

Some comments inline:

Quoted 8 lines

+? clock-frequency:
+??? description:
+????? Desired I2C bus clock frequency in Hz. default 100khz. +
+? multi-master:
+??? type: boolean
+??? description:
+????? states that there is another master active on this bus

These are common to all i2c controllers, but I see that i2c-controller.yaml doesn't include them (while i2c.text does).

I assume we're OK to include these in the device bindings in the meantime. But in that case, you may also want to include the common "smbus-alert" property, which you consume in your driver.

Quoted 6 lines

+? timeout:
+??? type: boolean
+??? description: Enable i2c bus timeout for master/slave (35ms) +
+? byte-mode:
+??? type: boolean

Quoted 5 lines

+??? description: Force i2c driver use byte mode transmit +
+? buff-mode:
+??? type: boolean
+??? description: Force i2c driver use buffer mode transmit

These three aren't really a property of the hardware, more of the intended driver configuration. Do they really belong in the DT?

[and how would a DT author know which modes to choose?]

Quoted 3 lines

+? aspeed,gr:
+??? $ref: /schemas/types.yaml#/definitions/phandle +??? description: The phandle of i2c global register node.

We'll probably want this to be consistent with other instances of aspeed global register references. I've used "aspeed,global-regs" in the proposed i3c binding:

https://lore.kernel.org/linux-devicetree/cover.1676532146.git.jk at codeconstruc t.com.au/T/#mda2d005f77ca0c481b1f1edadb58fc1b007a5cc3

I'd argue that "global-regs" is a little more clear, but I'm okay with either way - that change has been Acked but not been merged yet.
Whichever we choose though, it should be consistent.

Quoted 7 lines

These are common to all i2c controllers, but I see that i2c-controller.yaml doesn't include them (while i2c.text does).

I assume we're OK to include these in the device bindings in the meantime. But in that case, you may also want to include the common "smbus-alert" property, which you consume in your driver.

Since i2c.text have multi-master, smbus-alert. I don't need those two right?

Quoted 16 lines

Review

Quoted 12 lines

+? timeout:
+??? type: boolean
+??? description: Enable i2c bus timeout for master/slave (35ms)

(quoted diff) +8 -0

+
+? byte-mode:
+??? type: boolean
+??? description: Force i2c driver use byte mode transmit
+
+? buff-mode:
+??? type: boolean
+??? description: Force i2c driver use buffer mode transmit

These three aren't really a property of the hardware, more of the intended driver configuration. Do they really belong in the DT?

Sorry, I am confused.
This is hardware controller mode setting for each i2c transfer. So I add it in property for change different i2c transfer mode. Is my mis-understand the property setting?

Quoted 2 lines

[and how would a DT author know which modes to choose?]

Quoted 9 lines

Quoted 8 lines

+? clock-frequency:
+??? description:
+????? Desired I2C bus clock frequency in Hz. default 100khz. +
+? multi-master:
+??? type: boolean
+??? description:
+????? states that there is another master active on this bus

Quoted 7 lines

These are common to all i2c controllers, but I see that i2c-controller.yaml doesn't include them (while i2c.text does).

I assume we're OK to include these in the device bindings in the meantime. But in that case, you may also want to include the common "smbus-alert" property, which you consume in your driver.

Since i2c.text have multi-master, smbus-alert. I don't need those two right?

Quoted 6 lines

Quoted 6 lines

+? timeout:
+??? type: boolean
+??? description: Enable i2c bus timeout for master/slave (35ms) +
+? byte-mode:
+??? type: boolean

Quoted 9 lines

Quoted 5 lines

+??? description: Force i2c driver use byte mode transmit +
+? buff-mode:
+??? type: boolean
+??? description: Force i2c driver use buffer mode transmit

These three aren't really a property of the hardware, more of the intended driver configuration. Do they really belong in the DT?

Sorry, I am confused.
This is hardware controller mode setting for each i2c transfer. So I add it in property for change different i2c transfer mode. Is my mis-understand the property setting?

-----Original Message-----
From: Jeremy Kerr <[email protected]>
Sent: Monday, February 20, 2023 7:24 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2

Hi Ryan,

Quoted 12 lines

Quoted 12 lines

Quoted 8 lines

+? clock-frequency:
+??? description:
+????? Desired I2C bus clock frequency in Hz. default 100khz. +
+? multi-master:
+??? type: boolean
+??? description:
+????? states that there is another master active on this bus

These are common to all i2c controllers, but I see that i2c-controller.yaml doesn't include them (while i2c.text does).

Quoted 5 lines

Quoted 4 lines

I assume we're OK to include these in the device bindings in the meantime. But in that case, you may also want to include the common "smbus-alert" property, which you consume in your driver.

Since i2c.text have multi-master, smbus-alert. I don't need those two right?

Depends whether the maintainers consider i2c.text as part of the schema, I figure. Might be best to get their input on this.

Quoted 15 lines

Quoted 6 lines

Quoted 6 lines

+? timeout:
+??? type: boolean
+??? description: Enable i2c bus timeout for master/slave (35ms) +
+? byte-mode:
+??? type: boolean

Quoted 9 lines

Quoted 5 lines

+??? description: Force i2c driver use byte mode transmit +
+? buff-mode:
+??? type: boolean
+??? description: Force i2c driver use buffer mode transmit

These three aren't really a property of the hardware, more of the intended driver configuration. Do they really belong in the DT?

Quoted 4 lines

Sorry, I am confused.
This is hardware controller mode setting for each i2c transfer. So I add it in property for change different i2c transfer mode. Is my mis-understand the property setting?

It depends what this is configuration is for.

Would you set the transfer mode based on the design of the board? Is there something about the physical i2c bus wiring (or some other hardware design choice) that would mean you use one setting over another?

On the other hand, if it's just because of OS behaviour, then this doesn't belong in the DT.

Maybe to help us understand: why would you ever *not* want DMA mode? Isn't that always preferable?

Hello Jeremy,

Quoted 25 lines

-----Original Message-----
From: Jeremy Kerr <[email protected]>
Sent: Monday, February 20, 2023 7:24 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2

Hi Ryan,

Quoted 12 lines

Quoted 12 lines

Quoted 8 lines

+? clock-frequency:
+??? description:
+????? Desired I2C bus clock frequency in Hz. default 100khz. +
+? multi-master:
+??? type: boolean
+??? description:
+????? states that there is another master active on this bus

These are common to all i2c controllers, but I see that i2c-controller.yaml doesn't include them (while i2c.text does).

Quoted 8 lines

Quoted 5 lines

Quoted 4 lines

I assume we're OK to include these in the device bindings in the meantime. But in that case, you may also want to include the common "smbus-alert" property, which you consume in your driver.

Since i2c.text have multi-master, smbus-alert. I don't need those two right?

Depends whether the maintainers consider i2c.text as part of the schema, I figure. Might be best to get their input on this.

Yes, I will drop this, also integrate into aspeed,i2c.yaml file.

Quoted 20 lines

Quoted 19 lines

Quoted 6 lines

Quoted 6 lines

+? timeout:
+??? type: boolean
+??? description: Enable i2c bus timeout for master/slave (35ms) +
+? byte-mode:
+??? type: boolean

Quoted 9 lines

Quoted 5 lines

+??? description: Force i2c driver use byte mode transmit +
+? buff-mode:
+??? type: boolean
+??? description: Force i2c driver use buffer mode transmit

These three aren't really a property of the hardware, more of the intended driver configuration. Do they really belong in the DT?

Sorry, I am confused.
This is hardware controller mode setting for each i2c transfer. So I add it in property for change different i2c transfer mode. Is my mis-understand the property setting?

Quoted 6 lines

It depends what this is configuration is for.

Would you set the transfer mode based on the design of the board? Is there something about the physical i2c bus wiring (or some other hardware design choice) that would mean you use one setting over another?

No, it not depend on board design. It is only for register control for controller transfer behave.

The controller support 3 different trigger mode for transfer.
Byte mode: it means step by step to issue transfer.
Example i2c read, each step will issue interrupt then driver need trigger for next step.
Sr (start read) | D | D | D | P
Buffer mode: it means, the data can prepare into buffer register, then Trigger transfer. So Sr D D D P, only have only 1 interrupt handling. The DMA mode most like with buffer mode, The differ is data prepare in DRAM, than trigger transfer.

Quoted 5 lines

On the other hand, if it's just because of OS behaviour, then this doesn't belong in the DT.

Maybe to help us understand: why would you ever *not* want DMA mode? Isn't that always preferable?

In AST SOC i2c design is 16 i2c bus share one dma engine.
It can be switch setting by dts setting. Otherwise driver by default probe is DMA mode.

Quoted 20 lines

Quoted 15 lines

Quoted 6 lines

Quoted 6 lines

+? timeout:
+??? type: boolean
+??? description: Enable i2c bus timeout for master/slave (35ms) +
+? byte-mode:
+??? type: boolean

Quoted 9 lines

Quoted 5 lines

+??? description: Force i2c driver use byte mode transmit +
+? buff-mode:
+??? type: boolean
+??? description: Force i2c driver use buffer mode transmit

These three aren't really a property of the hardware, more of the intended driver configuration. Do they really belong in the DT?

Quoted 4 lines

Sorry, I am confused.
This is hardware controller mode setting for each i2c transfer. So I add it in property for change different i2c transfer mode. Is my mis-understand the property setting?

Quoted 6 lines

It depends what this is configuration is for.

Would you set the transfer mode based on the design of the board? Is there something about the physical i2c bus wiring (or some other hardware design choice) that would mean you use one setting over another?

No, it not depend on board design. It is only for register control for controller transfer behave.
The controller support 3 different trigger mode for transfer.
Byte mode: it means step by step to issue transfer.
Example i2c read, each step will issue interrupt then driver need trigger for next step.
Sr (start read) | D | D | D | P
Buffer mode: it means, the data can prepare into buffer register, then Trigger transfer. So Sr D D D P, only have only 1 interrupt handling. The DMA mode most like with buffer mode, The differ is data prepare in DRAM, than trigger transfer.

Quoted 7 lines

On the other hand, if it's just because of OS behaviour, then this doesn't belong
in the DT.

Maybe to help us understand: why would you ever *not* want DMA mode?
Isn't that always preferable?

In AST SOC i2c design is 16 i2c bus share one dma engine.

It can be switch setting by dts setting. Otherwise driver by default probe is DMA mode.

AST2600 support new register set for I2Cv2 controller, add bindings document to support driver of i2cv2 new register mode controller.

Signed-off-by Ryan Chen <[email protected]>

---
 .../devicetree/bindings/i2c/aspeed,i2cv2.yaml | 83 +++++++++++++++++++
 1 file changed, 83 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +14 -0

new file mode 100644
index 000000000000..913fb45d5fbe
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/aspeed,i2cv2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED I2Cv2 Controller on the AST26XX SoCs
+
+maintainers:
+  - Ryan Chen <[email protected]>
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +10 -0

+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description:
+      Reference clock for the I2C bus
+
+  resets:

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +10 -0

+
+  aspeed,gr:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: The phandle of i2c global register node.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Monday, February 20, 2023 4:35 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2

Quoted 10 lines · Ryan Chen

AST2600 support new register set for I2Cv2 controller, add bindings document to support driver of i2cv2 new register mode controller.

Signed-off-by Ryan Chen <[email protected]>

---
 .../devicetree/bindings/i2c/aspeed,i2cv2.yaml | 83
+++++++++++++++++++
 1 file changed, 83 insertions(+)
 create mode 100644

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml

New compatible is okay, but as this is the same controller as old one, this should go to old binding.

There are several issues anyway here, but I won't reviewing it except few obvious cases.

Quoted 25 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +17 -0

new file mode 100644
index 000000000000..913fb45d5fbe
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/aspeed,i2cv2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED I2Cv2 Controller on the AST26XX SoCs
+
+maintainers:
+  - Ryan Chen <[email protected]>
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - aspeed,ast2600-i2cv2

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 24

Quoted 6 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +6 -0

+
+  reg:
+    minItems: 1
+    items:
+      - description: address offset and range of register
+      - description: address offset and range of buffer register

Why this is optional?

Quoted 15 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +14 -0

+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description:
+      Reference clock for the I2C bus
+
+  resets:
+    maxItems: 1
+
+  clock-frequency:
+    description:

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 44

Quoted 6 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +6 -0

+      Desired I2C bus clock frequency in Hz. default 100khz.
+
+  multi-master:
+    type: boolean
+    description:
+      states that there is another master active on this bus

Drop description and type. Just :true.

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 48

Quoted 4 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +4 -0

+
+  timeout:
+    type: boolean
+    description: Enable i2c bus timeout for master/slave (35ms)

Why this is property for DT? It's for sure not bool, but proper type coming from units.

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 52

Quoted 4 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +4 -0

+
+  byte-mode:
+    type: boolean
+    description: Force i2c driver use byte mode transmit

Drop, not a DT property.

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 56

Quoted 4 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +4 -0

+
+  buff-mode:
+    type: boolean
+    description: Force i2c driver use buffer mode transmit

Drop, not a DT property.

Quoted 14 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +14 -0

+
+  aspeed,gr:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: The phandle of i2c global register node.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - resets
+  - aspeed,gr
+
+unevaluatedProperties: false

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 76

Quoted 6 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +6 -0

+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/ast2600-clock.h>
+    i2c: i2c-bus at 80 {

You did not test the bindings... This is i2c.

Best regards,
Krzysztof

Hello Krzysztof,

Quoted 54 lines

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Monday, February 20, 2023 4:35 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2

Quoted 10 lines · Ryan Chen

AST2600 support new register set for I2Cv2 controller, add bindings document to support driver of i2cv2 new register mode controller.

Signed-off-by Ryan Chen <[email protected]>

---
 .../devicetree/bindings/i2c/aspeed,i2cv2.yaml | 83
+++++++++++++++++++
 1 file changed, 83 insertions(+)
 create mode 100644

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml

New compatible is okay, but as this is the same controller as old one, this should go to old binding.

There are several issues anyway here, but I won't reviewing it except few obvious cases.

Quoted 25 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +17 -0

new file mode 100644
index 000000000000..913fb45d5fbe
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/aspeed,i2cv2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED I2Cv2 Controller on the AST26XX SoCs
+
+maintainers:
+  - Ryan Chen <[email protected]>
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - aspeed,ast2600-i2cv2

Quoted 8 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 24

Quoted 6 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +6 -0

+
+  reg:
+    minItems: 1
+    items:
+      - description: address offset and range of register
+      - description: address offset and range of buffer register

Why this is optional?

Will modify minItems: 1 to 2

Quoted 15 lines

Quoted 15 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +14 -0

+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description:
+      Reference clock for the I2C bus
+
+  resets:
+    maxItems: 1
+
+  clock-frequency:
+    description:

Quoted 9 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 44

Quoted 6 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +6 -0

+      Desired I2C bus clock frequency in Hz. default 100khz.
+
+  multi-master:
+    type: boolean
+    description:
+      states that there is another master active on this bus

Drop description and type. Just :true.

Since i2c.txt have multi-master will drop it.

Quoted 5 lines

Quoted 4 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +4 -0

+
+  timeout:
+    type: boolean
+    description: Enable i2c bus timeout for master/slave (35ms)

Quoted 2 lines

Why this is property for DT? It's for sure not bool, but proper type coming from units.

This is i2c controller feature for enable slave mode inactive timeout and also master mode sda/scl auto release timeout.
So I will modify to
aspeed,timeout:
type: boolean
description: I2C bus timeout enable for master/slave mode

Quoted 6 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 52

Quoted 5 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +4 -0

+
+  byte-mode:
+    type: boolean
+    description: Force i2c driver use byte mode transmit

Quoted 9 lines

Drop, not a DT property.

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 56

Quoted 4 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +4 -0

+
+  buff-mode:
+    type: boolean
+    description: Force i2c driver use buffer mode transmit

Drop, not a DT property.

The controller support 3 different for transfer.
Byte mode: it means step by step to issue transfer.
Example i2c read, each step will issue interrupt then enable next step. Sr (start read) | D | D | D | P
Buffer mode: it means, the data can prepare into buffer register, then Trigger transfer. So Sr D D D P, only have only 1 interrupt handling. The DMA mode most like with buffer mode,
The differ is data prepare in DRAM, than trigger transfer.

So, should I modify to
aspeed,byte:
type: boolean
description: Enable i2c controller transfer with byte mode

aspeed,buff:
type: boolean
description: Enable i2c controller transfer with buff mode

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Tuesday, February 21, 2023 5:40 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2

Quoted 100 lines · Ryan Chen

Hello Krzysztof,

Quoted 56 lines

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Monday, February 20, 2023 4:35 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org;
linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2

Quoted 10 lines · Ryan Chen

AST2600 support new register set for I2Cv2 controller, add bindings document to support driver of i2cv2 new register mode controller.

Signed-off-by Ryan Chen <[email protected]>

---
 .../devicetree/bindings/i2c/aspeed,i2cv2.yaml | 83
+++++++++++++++++++
 1 file changed, 83 insertions(+)
 create mode 100644

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml

New compatible is okay, but as this is the same controller as old one, this should go to old binding.

There are several issues anyway here, but I won't reviewing it except few obvious cases.

Quoted 25 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +17 -0

new file mode 100644
index 000000000000..913fb45d5fbe
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/aspeed,i2cv2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED I2Cv2 Controller on the AST26XX SoCs
+
+maintainers:
+  - Ryan Chen <[email protected]>
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - aspeed,ast2600-i2cv2

Quoted 8 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 24

Quoted 6 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +6 -0

+
+  reg:
+    minItems: 1
+    items:
+      - description: address offset and range of register
+      - description: address offset and range of buffer register

Why this is optional?

Will modify minItems: 1 to 2

Quoted 15 lines

Quoted 15 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +14 -0

+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description:
+      Reference clock for the I2C bus
+
+  resets:
+    maxItems: 1
+
+  clock-frequency:
+    description:

Quoted 9 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 44

Quoted 6 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +6 -0

+      Desired I2C bus clock frequency in Hz. default 100khz.
+
+  multi-master:
+    type: boolean
+    description:
+      states that there is another master active on this bus

Drop description and type. Just :true.

Since i2c.txt have multi-master will drop it.

Quoted 7 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 48

Quoted 4 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +4 -0

+
+  timeout:
+    type: boolean
+    description: Enable i2c bus timeout for master/slave (35ms)

Why this is property for DT? It's for sure not bool, but proper type coming from units.

Quoted 6 lines

This is i2c controller feature for enable slave mode inactive timeout and also master mode sda/scl auto release timeout.
So I will modify to
aspeed,timeout:
type: boolean
description: I2C bus timeout enable for master/slave mode

This does not answer my concerns. Why this is board specific?

Quoted 30 lines

Quoted 7 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 52

Quoted 6 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +4 -0

+
+  byte-mode:
+    type: boolean
+    description: Force i2c driver use byte mode transmit

Quoted 9 lines

Drop, not a DT property.

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 56

Quoted 4 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +4 -0

+
+  buff-mode:
+    type: boolean
+    description: Force i2c driver use buffer mode transmit

Drop, not a DT property.

The controller support 3 different for transfer.
Byte mode: it means step by step to issue transfer.
Example i2c read, each step will issue interrupt then enable next step. Sr (start read) | D | D | D | P
Buffer mode: it means, the data can prepare into buffer register, then Trigger transfer. So Sr D D D P, only have only 1 interrupt handling. The DMA mode most like with buffer mode, The differ is data prepare in DRAM, than trigger transfer.

So, should I modify to
aspeed,byte:
type: boolean
description: Enable i2c controller transfer with byte mode

Quoted 3 lines

aspeed,buff:
type: boolean
description: Enable i2c controller transfer with buff mode

1. No, these are not bools but enum in such case.

2. And why exactly this is board-specific?

Quoted 5 lines

Quoted 5 lines

Quoted 5 lines

Review

Quoted 2 lines

(quoted diff) +2 -0

+    type: boolean
+    description: Enable i2c bus timeout for master/slave (35ms)

Why this is property for DT? It's for sure not bool, but proper type coming from units.

Quoted 8 lines

Quoted 6 lines

This is i2c controller feature for enable slave mode inactive timeout and also master mode sda/scl auto release timeout.
So I will modify to
aspeed,timeout:
type: boolean
description: I2C bus timeout enable for master/slave mode

This does not answer my concerns. Why this is board specific?

Sorry, can?t catch your point.
It is not board specific. It is controller feature.
ASPEED SOC chip is server product, master connect may have fingerprint connect to another board. And also support hotplug.
For example I2C controller as slave mode, and suddenly disconnected. Slave state machine will keep waiting for master clock in for rx/tx transfer. So it need timeout setting to enable timeout unlock controller state. And in another side. As master mode, slave is clock stretching. The master will be keep waiting, until slave release cll stretching.

So in those reason add this timeout design in controller.

Quoted 34 lines

Quoted 33 lines

Quoted 7 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 52

Quoted 6 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +4 -0

+
+  byte-mode:
+    type: boolean
+    description: Force i2c driver use byte mode transmit

Quoted 9 lines

Drop, not a DT property.

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 56

Quoted 4 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +4 -0

+
+  buff-mode:
+    type: boolean
+    description: Force i2c driver use buffer mode transmit

Drop, not a DT property.

The controller support 3 different for transfer.
Byte mode: it means step by step to issue transfer.
Example i2c read, each step will issue interrupt then enable next step. Sr (start read) | D | D | D | P
Buffer mode: it means, the data can prepare into buffer register, then Trigger transfer. So Sr D D D P, only have only 1 interrupt handling. The DMA mode most like with buffer mode, The differ is data prepare in DRAM, than trigger transfer.

So, should I modify to
aspeed,byte:
type: boolean
description: Enable i2c controller transfer with byte mode

aspeed,buff:
type: boolean
description: Enable i2c controller transfer with buff mode

Quoted 1 line

1. No, these are not bools but enum in such case.

Thanks, will modify following.
aspeed,xfer_mode:

    enum: [0, 1, 2]
    description:
      0: byte mode, 1: buff_mode, 2: dma_mode

Quoted 2 lines

2. And why exactly this is board-specific?

No, it not depends on board design. It is only for register control for controller transfer behave. The controller support 3 different trigger mode for transfer.
Assign bus#1 ~ 3 : dma tranfer and assign bus#4 ~ 6 : buffer mode transfer,
That can reduce the dram usage.

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Tuesday, February 21, 2023 7:05 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2

Quoted 13 lines · Ryan Chen

Quoted 5 lines

Quoted 5 lines

Quoted 5 lines

Review

Quoted 2 lines

(quoted diff) +2 -0

+    type: boolean
+    description: Enable i2c bus timeout for master/slave (35ms)

Why this is property for DT? It's for sure not bool, but proper type coming from units.

Quoted 8 lines

Quoted 6 lines

This is i2c controller feature for enable slave mode inactive timeout and also master mode sda/scl auto release timeout. So I will modify to
aspeed,timeout:
type: boolean
description: I2C bus timeout enable for master/slave mode

This does not answer my concerns. Why this is board specific?

Quoted 9 lines

Sorry, can?t catch your point.
It is not board specific. It is controller feature.
ASPEED SOC chip is server product, master connect may have fingerprint connect to another board. And also support hotplug.
For example I2C controller as slave mode, and suddenly disconnected. Slave state machine will keep waiting for master clock in for rx/tx transfer. So it need timeout setting to enable timeout unlock controller state. And in another side. As master mode, slave is clock stretching. The master will be keep waiting, until slave release cll stretching.

OK, thanks for describing the feature. I still do not see how this is DT related.

Quoted 2 lines

So in those reason add this timeout design in controller.

You need to justify why DT is correct place for this property. DT is not for configuring OS, but to describe hardware. I gave you one possibility
- why different boards would like to set this property. You said it is not board specific, thus all boards will have it (or none of them).
Without any other reason, this is not a DT property. Drop.

Quoted 34 lines

Quoted 34 lines

Quoted 33 lines

Quoted 7 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 52

Quoted 6 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +4 -0

+
+  byte-mode:
+    type: boolean
+    description: Force i2c driver use byte mode transmit

Quoted 9 lines

Drop, not a DT property.

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml line 56

Quoted 4 lines

Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml new file +4 -0

+
+  buff-mode:
+    type: boolean
+    description: Force i2c driver use buffer mode transmit

Drop, not a DT property.

The controller support 3 different for transfer.
Byte mode: it means step by step to issue transfer.
Example i2c read, each step will issue interrupt then enable next step. Sr (start read) | D | D | D | P
Buffer mode: it means, the data can prepare into buffer register, then Trigger transfer. So Sr D D D P, only have only 1 interrupt handling. The DMA mode most like with buffer mode, The differ is data prepare in DRAM, than trigger transfer.

So, should I modify to
aspeed,byte:
type: boolean
description: Enable i2c controller transfer with byte mode

aspeed,buff:
type: boolean
description: Enable i2c controller transfer with buff mode

Quoted 7 lines

Quoted 1 line

1. No, these are not bools but enum in such case.

Thanks, will modify following.
aspeed,xfer_mode:

    enum: [0, 1, 2]
    description:
      0: byte mode, 1: buff_mode, 2: dma_mode

Just keep it text - byte, buffered, dma

Quoted 3 lines

Quoted 2 lines

2. And why exactly this is board-specific?

Quoted 1 line

No, it not depends on board design. It is only for register control for

controller transfer behave.

Quoted 3 lines

The controller support 3 different trigger mode for transfer. Assign bus#1 ~ 3 : dma tranfer and assign bus#4 ~ 6 : buffer mode transfer, That can reduce the dram usage.

Then anyway it does not look like property for Devicetree. DT describes hardware, not OS behavior.

Hello Krzysztof,

Quoted 35 lines

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Tuesday, February 21, 2023 7:05 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2

Quoted 13 lines · Ryan Chen

Quoted 5 lines

Quoted 5 lines

Quoted 5 lines

Review

Quoted 2 lines

(quoted diff) +2 -0

+    type: boolean
+    description: Enable i2c bus timeout for master/slave (35ms)

Why this is property for DT? It's for sure not bool, but proper type coming from units.

Quoted 8 lines

Quoted 6 lines

This is i2c controller feature for enable slave mode inactive timeout and also master mode sda/scl auto release timeout. So I will modify to
aspeed,timeout:
type: boolean
description: I2C bus timeout enable for master/slave mode

This does not answer my concerns. Why this is board specific?

Quoted 9 lines

Sorry, can?t catch your point.
It is not board specific. It is controller feature.
ASPEED SOC chip is server product, master connect may have fingerprint connect to another board. And also support hotplug.
For example I2C controller as slave mode, and suddenly disconnected. Slave state machine will keep waiting for master clock in for rx/tx transfer. So it need timeout setting to enable timeout unlock controller state. And in another side. As master mode, slave is clock stretching. The master will be keep waiting, until slave release cll stretching.

Quoted 1 line

OK, thanks for describing the feature. I still do not see how this is DT related.

Let me draw more about the board-specific. The following is an example about i2c layout in board.
Board A Board B
-------------------------------------------------------- --------------------------------------------------------

|    i2c bus#1(master/slave)  <--------------------> fingerprint.(can be unplug)    <--------------------> i2c bus#x (master/slave) |
|    i2c bus#2(master) -> tmp i2c device     |			     		|									|
|    i2c bus#3(master) -> adc i2c device      |					|									|

-------------------------------------------------------- --------------------------------------------------------
In this case i2c bus#1 need enable timeout, avoid suddenly unplug the connector. That slave will keep state to drive clock stretching. So it is specific enable in i2c bus#1. Others is not needed enable timeout.
Does this draw is more clear in scenario?

Quoted 63 lines

Quoted 3 lines

So in those reason add this timeout design in controller.

You need to justify why DT is correct place for this property. DT is not for configuring OS, but to describe hardware. I gave you one possibility
- why different boards would like to set this property. You said it is not board specific, thus all boards will have it (or none of them).
Without any other reason, this is not a DT property. Drop.

Quoted 34 lines

Quoted 34 lines

Quoted 33 lines

Quoted 7 lines

Review

Quoted 6 lines

(quoted diff) +4 -0

+
+  byte-mode:
+    type: boolean
+    description: Force i2c driver use byte mode transmit

Quoted 9 lines

Drop, not a DT property.

Review

Quoted 4 lines

(quoted diff) +4 -0

+
+  buff-mode:
+    type: boolean
+    description: Force i2c driver use buffer mode transmit

Drop, not a DT property.

The controller support 3 different for transfer.
Byte mode: it means step by step to issue transfer.
Example i2c read, each step will issue interrupt then enable next step. Sr (start read) | D | D | D | P
Buffer mode: it means, the data can prepare into buffer register, then Trigger transfer. So Sr D D D P, only have only 1 interrupt handling. The DMA mode most like with buffer mode, The differ is data prepare in DRAM, than trigger transfer.

So, should I modify to
aspeed,byte:
type: boolean
description: Enable i2c controller transfer with byte mode

aspeed,buff:
type: boolean
description: Enable i2c controller transfer with buff mode

Quoted 7 lines

Quoted 1 line

1. No, these are not bools but enum in such case.

Thanks, will modify following.
aspeed,xfer_mode:

    enum: [0, 1, 2]
    description:
      0: byte mode, 1: buff_mode, 2: dma_mode

Just keep it text - byte, buffered, dma

Quoted 4 lines

Quoted 2 lines

2. And why exactly this is board-specific?

No, it not depends on board design. It is only for register control for

controller transfer behave.

Quoted 3 lines

The controller support 3 different trigger mode for transfer. Assign bus#1 ~ 3 : dma tranfer and assign bus#4 ~ 6 : buffer mode transfer, That can reduce the dram usage.

Quoted 2 lines

Then anyway it does not look like property for Devicetree. DT describes hardware, not OS behavior.

The same draw, in this case, i2c bus#1 that is multi-master transfer architecture. Both will inactive with trunk data. That cane enable i2c#1 use DMA transfer to reduce CPU utilized. Others (bus#2/3) can keep byte/buff mode.

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Wednesday, February 22, 2023 4:26 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2

Quoted 40 lines · Ryan Chen

Hello Krzysztof,

Quoted 38 lines

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Tuesday, February 21, 2023 7:05 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org;
linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2

Quoted 13 lines · Ryan Chen

Quoted 5 lines

Quoted 5 lines

Quoted 5 lines

Review

Quoted 2 lines

(quoted diff) +2 -0

+    type: boolean
+    description: Enable i2c bus timeout for master/slave (35ms)

Why this is property for DT? It's for sure not bool, but proper type coming from units.

Quoted 8 lines

Quoted 6 lines

This is i2c controller feature for enable slave mode inactive timeout and also master mode sda/scl auto release timeout. So I will modify to
aspeed,timeout:
type: boolean
description: I2C bus timeout enable for master/slave mode

This does not answer my concerns. Why this is board specific?

Quoted 9 lines

Sorry, can?t catch your point.
It is not board specific. It is controller feature.
ASPEED SOC chip is server product, master connect may have fingerprint connect to another board. And also support hotplug. For example I2C controller as slave mode, and suddenly disconnected. Slave state machine will keep waiting for master clock in for rx/tx transfer. So it need timeout setting to enable timeout unlock controller state. And in another side. As master mode, slave is clock stretching. The master will be keep waiting, until slave release cll stretching.

OK, thanks for describing the feature. I still do not see how this is DT

related.

Quoted 4 lines

Let me draw more about the board-specific. The following is an example about i2c layout in board. Board A

Board B

Quoted 1 line

--------------------------------------------------------

	--------------------------------------------------------

Quoted 1 line

| i2c bus#1(master/slave) <--------------------> fingerprint.(can be unplug)

<--------------------> i2c bus#x (master/slave) |

Quoted 1 line

| i2c bus#2(master) -> tmp i2c device |

	|									|
> |    i2c bus#3(master) -> adc i2c device      |					|
								|

Quoted 1 line

--------------------------------------------------------

	--------------------------------------------------------

Quoted 1 line

In this case i2c bus#1 need enable timeout, avoid suddenly unplug the

connector. That slave will keep state to drive clock stretching.

Quoted 2 lines

So it is specific enable in i2c bus#1. Others is not needed enable timeout. Does this draw is more clear in scenario?

I2C bus #1 works in slave mode? So you always need it for slave work?

Quoted 68 lines

Quoted 67 lines

Quoted 3 lines

So in those reason add this timeout design in controller.

You need to justify why DT is correct place for this property. DT is not for configuring OS, but to describe hardware. I gave you one possibility
- why different boards would like to set this property. You said it is not board specific, thus all boards will have it (or none of them). Without any other reason, this is not a DT property. Drop.

Quoted 34 lines

Quoted 34 lines

Quoted 33 lines

Quoted 7 lines

Review

Quoted 6 lines

(quoted diff) +4 -0

+
+  byte-mode:
+    type: boolean
+    description: Force i2c driver use byte mode transmit

Quoted 9 lines

Drop, not a DT property.

Review

Quoted 4 lines

(quoted diff) +4 -0

+
+  buff-mode:
+    type: boolean
+    description: Force i2c driver use buffer mode transmit

Drop, not a DT property.

The controller support 3 different for transfer.
Byte mode: it means step by step to issue transfer.
Example i2c read, each step will issue interrupt then enable next step. Sr (start read) | D | D | D | P
Buffer mode: it means, the data can prepare into buffer register, then Trigger transfer. So Sr D D D P, only have only 1 interrupt handling. The DMA mode most like with buffer mode, The differ is data prepare in DRAM, than trigger transfer.

So, should I modify to
aspeed,byte:
type: boolean
description: Enable i2c controller transfer with byte mode

aspeed,buff:
type: boolean
description: Enable i2c controller transfer with buff mode

Quoted 7 lines

Quoted 1 line

1. No, these are not bools but enum in such case.

Thanks, will modify following.
aspeed,xfer_mode:

    enum: [0, 1, 2]
    description:
      0: byte mode, 1: buff_mode, 2: dma_mode

Just keep it text - byte, buffered, dma

Quoted 5 lines

Quoted 2 lines

2. And why exactly this is board-specific?

No, it not depends on board design. It is only for register control for

controller transfer behave.

Quoted 3 lines

The controller support 3 different trigger mode for transfer. Assign bus#1 ~ 3 : dma tranfer and assign bus#4 ~ 6 : buffer mode transfer, That can reduce the dram usage.

Then anyway it does not look like property for Devicetree. DT describes hardware, not OS behavior.

Quoted 1 line

The same draw, in this case, i2c bus#1 that is multi-master transfer

architecture.

Quoted 1 line

Both will inactive with trunk data. That cane enable i2c#1 use DMA transfer

to reduce CPU utilized.

Quoted 1 line

Others (bus#2/3) can keep byte/buff mode.

Isn't then current bus configuration for I2C#1 known to the driver? Jeremy asked few other questions around here...

Quoted 12 lines

Board B

Quoted 1 line

--------------------------------------------------------

	--------------------------------------------------------

Quoted 1 line

| i2c bus#1(master/slave) <--------------------> fingerprint.(can be unplug)

<--------------------> i2c bus#x (master/slave) |

Quoted 1 line

| i2c bus#2(master) -> tmp i2c device |

	|									|
> |    i2c bus#3(master) -> adc i2c device      |					|
								|

Quoted 1 line

--------------------------------------------------------

	--------------------------------------------------------

Quoted 1 line

In this case i2c bus#1 need enable timeout, avoid suddenly unplug the

Quoted 5 lines

connector. That slave will keep state to drive clock stretching.

Quoted 2 lines

So it is specific enable in i2c bus#1. Others is not needed enable timeout. Does this draw is more clear in scenario?

I2C bus #1 works in slave mode? So you always need it for slave work?

Yes, it is both slave/master mode. It is always dual role. Slave must always work. Due to another board master will send.

Quoted 71 lines

Quoted 62 lines

Quoted 62 lines

Quoted 4 lines

So in those reason add this timeout design in controller.

You need to justify why DT is correct place for this property. DT is not for configuring OS, but to describe hardware. I gave you one possibility
- why different boards would like to set this property. You said it is not board specific, thus all boards will have it (or none of them). Without any other reason, this is not a DT property. Drop.

Quoted 34 lines

Quoted 34 lines

Quoted 33 lines

Quoted 7 lines

Review

Quoted 6 lines

(quoted diff) +4 -0

+
+  byte-mode:
+    type: boolean
+    description: Force i2c driver use byte mode transmit

Quoted 9 lines

Drop, not a DT property.

Review

Quoted 4 lines

(quoted diff) +4 -0

+
+  buff-mode:
+    type: boolean
+    description: Force i2c driver use buffer mode transmit

Drop, not a DT property.

The controller support 3 different for transfer.
Byte mode: it means step by step to issue transfer.
Example i2c read, each step will issue interrupt then enable next step. Sr (start read) | D | D | D | P
Buffer mode: it means, the data can prepare into buffer register, then Trigger transfer. So Sr D D D P, only have only 1 interrupt handling. The DMA mode most like with buffer mode, The differ is data prepare in DRAM, than trigger transfer.

So, should I modify to
aspeed,byte:
type: boolean
description: Enable i2c controller transfer with byte mode

aspeed,buff:
type: boolean
description: Enable i2c controller transfer with buff mode

Quoted 7 lines

Quoted 1 line

1. No, these are not bools but enum in such case.

Thanks, will modify following.
aspeed,xfer_mode:

    enum: [0, 1, 2]
    description:
      0: byte mode, 1: buff_mode, 2: dma_mode

Just keep it text - byte, buffered, dma

Quoted 5 lines

Quoted 2 lines

2. And why exactly this is board-specific?

No, it not depends on board design. It is only for register control for

controller transfer behave.

Quoted 8 lines

Quoted 6 lines

Quoted 3 lines

The controller support 3 different trigger mode for transfer. Assign bus#1 ~ 3 : dma tranfer and assign bus#4 ~ 6 : buffer mode transfer, That can reduce the dram usage.

Then anyway it does not look like property for Devicetree. DT describes hardware, not OS behavior.

The same draw, in this case, i2c bus#1 that is multi-master transfer

architecture.

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Both will inactive with trunk data. That cane enable i2c#1 use DMA transfer

to reduce CPU utilized.

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Others (bus#2/3) can keep byte/buff mode.

Isn't then current bus configuration for I2C#1 known to the driver? Jeremy asked few other questions around here...

No, The driver don't know currently board configuration.

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Wednesday, February 22, 2023 6:36 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2

Quoted 9 lines · Ryan Chen

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Board B

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--------------------------------------------------------

	--------------------------------------------------------

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| i2c bus#1(master/slave) <-------------------->
| fingerprint.(can be unplug)

<--------------------> i2c bus#x (master/slave) |

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| i2c bus#2(master) -> tmp i2c device |

	|									|
> |    i2c bus#3(master) -> adc i2c device      |

	|

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								|

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--------------------------------------------------------

	--------------------------------------------------------

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In this case i2c bus#1 need enable timeout, avoid suddenly unplug the

connector. That slave will keep state to drive clock stretching.

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So it is specific enable in i2c bus#1. Others is not needed enable timeout. Does this draw is more clear in scenario?

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I2C bus #1 works in slave mode? So you always need it for slave work?

Yes, it is both slave/master mode. It is always dual role. Slave must always

work.

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Due to another board master will send.

I meant that you need this property when it works in slave mode? It would be then redundant to have in DT as it is implied by the mode.

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So in those reason add this timeout design in controller.

You need to justify why DT is correct place for this property. DT is not for configuring OS, but to describe hardware. I gave you one possibility
- why different boards would like to set this property. You said it is not board specific, thus all boards will have it (or none of them). Without any other reason, this is not a DT property. Drop.

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Review

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+
+  byte-mode:
+    type: boolean
+    description: Force i2c driver use byte mode transmit

Drop, not a DT property.

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+
+  buff-mode:
+    type: boolean
+    description: Force i2c driver use buffer mode transmit

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Drop, not a DT property.

The controller support 3 different for transfer.
Byte mode: it means step by step to issue transfer. Example i2c read, each step will issue interrupt then enable next

step.

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Sr (start read) | D | D | D | P
Buffer mode: it means, the data can prepare into buffer register, then Trigger transfer. So Sr D D D P, only have only 1 interrupt

handling.

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The DMA mode most like with buffer mode, The differ is data prepare in DRAM, than trigger transfer.

So, should I modify to
aspeed,byte:
type: boolean
description: Enable i2c controller transfer with byte mode

aspeed,buff:
type: boolean
description: Enable i2c controller transfer with buff mode

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1. No, these are not bools but enum in such case.

Thanks, will modify following.
aspeed,xfer_mode:

    enum: [0, 1, 2]
    description:
      0: byte mode, 1: buff_mode, 2: dma_mode

Just keep it text - byte, buffered, dma

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2. And why exactly this is board-specific?

No, it not depends on board design. It is only for register control for

controller transfer behave.

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The controller support 3 different trigger mode for transfer. Assign bus#1 ~ 3 : dma tranfer and assign bus#4 ~ 6 : buffer mode transfer, That can reduce the dram usage.

Then anyway it does not look like property for Devicetree. DT describes hardware, not OS behavior.

The same draw, in this case, i2c bus#1 that is multi-master transfer

architecture.

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Both will inactive with trunk data. That cane enable i2c#1 use DMA transfer

to reduce CPU utilized.

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Others (bus#2/3) can keep byte/buff mode.

Isn't then current bus configuration for I2C#1 known to the driver? Jeremy asked few other questions around here...

No, The driver don't know currently board configuration.

It knows whether it is working in multi-master/slave mode.

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connector. That slave will keep state to drive clock stretching.

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So it is specific enable in i2c bus#1. Others is not needed enable timeout. Does this draw is more clear in scenario?

I2C bus #1 works in slave mode? So you always need it for slave work?

Yes, it is both slave/master mode. It is always dual role. Slave must always

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work.

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Due to another board master will send.

I meant that you need this property when it works in slave mode? It would be then redundant to have in DT as it is implied by the mode.

But timeout feature is also apply in master. It for avoid suddenly slave miss(un-plug) Master can timeout and release the SDA/SCL, return.

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The same draw, in this case, i2c bus#1 that is multi-master transfer

architecture.

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Both will inactive with trunk data. That cane enable i2c#1 use DMA transfer

to reduce CPU utilized.

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Others (bus#2/3) can keep byte/buff mode.

Isn't then current bus configuration for I2C#1 known to the driver? Jeremy asked few other questions around here...

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No, The driver don't know currently board configuration.

It knows whether it is working in multi-master/slave mode.

But in DT can decide which i2c bus number can use dma or buffer mode transfer.
If in another i2c bus support master only, also can use dma to transfer trunk data to another slave.

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Thursday, February 23, 2023 5:29 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2

Quoted 2 lines · Ryan Chen

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connector. That slave will keep state to drive clock stretching.

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So it is specific enable in i2c bus#1. Others is not needed enable

timeout.

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Does this draw is more clear in scenario?

I2C bus #1 works in slave mode? So you always need it for slave work?

Yes, it is both slave/master mode. It is always dual role. Slave must always

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work.

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Due to another board master will send.

I meant that you need this property when it works in slave mode? It would be then redundant to have in DT as it is implied by the mode.

But timeout feature is also apply in master. It for avoid suddenly slave miss(un-plug) Master can timeout and release the SDA/SCL, return.

OK, yet the property should describe the hardware, not the register feature you want to program. You need to properly model it in DT binding to represent hardware setup, not your desired Linux driver behavior.

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The same draw, in this case, i2c bus#1 that is multi-master transfer

architecture.

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Both will inactive with trunk data. That cane enable i2c#1 use DMA transfer

to reduce CPU utilized.

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Others (bus#2/3) can keep byte/buff mode.

Isn't then current bus configuration for I2C#1 known to the driver? Jeremy asked few other questions around here...

No, The driver don't know currently board configuration.

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It knows whether it is working in multi-master/slave mode.

But in DT can decide which i2c bus number can use dma or buffer mode

transfer.

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If in another i2c bus support master only, also can use dma to transfer trunk

data to another slave.

and none of these were explained in commit msg or device description.

Add i2cv2 new register mode driver to support AST2600 i2c new register mode. AST2600 i2c controller have legacy and new register mode. The new register mode have global register support 4 base clock for scl clock selection, and new clock divider mode. The i2c new register mode have separate register set to control i2c master and slave.

Signed-off-by Ryan Chen <[email protected]>

---
 MAINTAINERS                      |    9 +
 drivers/i2c/busses/Kconfig       |   11 +
 drivers/i2c/busses/Makefile      |    1 +
 drivers/i2c/busses/i2c-ast2600.c | 1703 ++++++++++++++++++++++++++++++
 4 files changed, 1724 insertions(+)
 create mode 100644 drivers/i2c/busses/i2c-ast2600.c

MAINTAINERS +9 -0

index 749710e22b4d..c9841568cb24 100644
@@ -1924,6 +1924,15 @@ F:	Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.
 F:	drivers/i2c/busses/i2c-aspeed.c
 F:	drivers/irqchip/irq-aspeed-i2c-ic.c
 
+ARM/ASPEED I2CV2 DRIVER
+M:      Ryan Chen <[email protected]>
+R:      Andrew Jeffery <[email protected]>
+L:      linux-i2c at vger.kernel.org
+L:      openbmc at lists.ozlabs.org (moderated for non-subscribers)
+S:      Maintained
+F:      Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml
+F:      drivers/i2c/busses/i2c-ast2600.c
+
 ARM/ASPEED MACHINE SUPPORT
 M:	Joel Stanley <[email protected]>
 R:	Andrew Jeffery <[email protected]>

drivers/i2c/busses/Kconfig +11 -0

index 7284206b278b..f3f7500ce768 100644
@@ -389,6 +389,17 @@ config I2C_ALTERA
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-altera.
 
+config I2C_AST2600
+	tristate "Aspeed I2C v2 Controller"
+	depends on ARCH_ASPEED || COMPILE_TEST
+	select I2C_SMBUS
+	help
+	  If you say yes to this option, support will be included for the
+	  Aspeed I2C controller with new register set.
+
+	  This driver can also be built as a module.  If so, the module
+	  will be called i2c-new-aspeed.
+
 config I2C_ASPEED
 	tristate "Aspeed I2C Controller"
 	depends on ARCH_ASPEED || COMPILE_TEST

drivers/i2c/busses/Makefile +1 -0

index c5cac15f075c..d0ab4d45781c 100644
@@ -38,6 +38,7 @@ obj-$(CONFIG_I2C_POWERMAC)	+= i2c-powermac.o
 obj-$(CONFIG_I2C_ALTERA)	+= i2c-altera.o
 obj-$(CONFIG_I2C_AMD_MP2)	+= i2c-amd-mp2-pci.o i2c-amd-mp2-plat.o
 obj-$(CONFIG_I2C_ASPEED)	+= i2c-aspeed.o
+obj-$(CONFIG_I2C_AST2600)	+= i2c-ast2600.o
 obj-$(CONFIG_I2C_AT91)		+= i2c-at91.o
 i2c-at91-objs			:= i2c-at91-core.o i2c-at91-master.o
 ifeq ($(CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL),y)

drivers/i2c/busses/i2c-ast2600.c new file +208 -0

new file mode 100644
index 000000000000..b5fe0af57d11
@@ -0,0 +1,1703 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * ASPEED AST2600 new register set I2C controller driver
+ *
+ * Copyright (C) ASPEED Technology Inc.
+ */
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/reset.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/of_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/i2c-smbus.h>
+
+/*
+ * APB clk : 100Mhz
+ * div	: scl		: baseclk [APB/((div/2) + 1)] : tBuf [1/bclk * 16]
+ * I2CG10[31:24] base clk4 for i2c auto recovery timeout counter (0xC6)
+ * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
+ * 0x3c : 100.8Khz	: 3.225Mhz					  : 4.96us
+ * 0x3d : 99.2Khz	: 3.174Mhz					  : 5.04us
+ * 0x3e : 97.65Khz	: 3.125Mhz					  : 5.12us
+ * 0x40 : 97.75Khz	: 3.03Mhz					  : 5.28us
+ * 0x41 : 99.5Khz	: 2.98Mhz					  : 5.36us (default)
+ * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
+ * 0x12 : 400Khz	: 10Mhz						  : 1.6us
+ * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us
+ * 0x08 : 1Mhz		: 20Mhz						  : 0.8us
+ */
+#define AST2600_I2CG_ISR			0x00
+#define AST2600_I2CG_SLAVE_ISR		0x04
+#define AST2600_I2CG_OWNER		0x08
+#define AST2600_I2CG_CTRL		0x0C
+#define AST2600_I2CG_CLK_DIV_CTRL	0x10
+
+#define AST2600_I2CG_SLAVE_PKT_NAK	BIT(4)
+#define AST2600_I2CG_M_S_SEPARATE_INTR	BIT(3)
+#define AST2600_I2CG_CTRL_NEW_REG	BIT(2)
+#define AST2600_I2CG_CTRL_NEW_CLK_DIV	BIT(1)
+
+#define AST2600_GLOBAL_INIT				\
+			(AST2600_I2CG_CTRL_NEW_REG |	\
+			AST2600_I2CG_CTRL_NEW_CLK_DIV)
+#define I2CCG_DIV_CTRL 0xC6411208
+
+/* 0x00 : I2CC Master/Slave Function Control Register  */
+#define AST2600_I2CC_FUN_CTRL		0x00
+#define AST2600_I2CC_SLAVE_ADDR_RX_EN		BIT(20)
+#define AST2600_I2CC_MASTER_RETRY_MASK		GENMASK(19, 18)
+#define AST2600_I2CC_MASTER_RETRY(x)		(((x) & GENMASK(1, 0)) << 18)
+#define AST2600_I2CC_BUS_AUTO_RELEASE		BIT(17)
+#define AST2600_I2CC_M_SDA_LOCK_EN			BIT(16)
+#define AST2600_I2CC_MULTI_MASTER_DIS		BIT(15)
+#define AST2600_I2CC_M_SCL_DRIVE_EN			BIT(14)
+#define AST2600_I2CC_MSB_STS				BIT(9)
+#define AST2600_I2CC_SDA_DRIVE_1T_EN		BIT(8)
+#define AST2600_I2CC_M_SDA_DRIVE_1T_EN		BIT(7)
+#define AST2600_I2CC_M_HIGH_SPEED_EN		BIT(6)
+/* reserver 5 : 2 */
+#define AST2600_I2CC_SLAVE_EN			BIT(1)
+#define AST2600_I2CC_MASTER_EN			BIT(0)
+
+/* 0x04 : I2CC Master/Slave Clock and AC Timing Control Register #1 */
+#define AST2600_I2CC_AC_TIMING		0x04
+#define AST2600_I2CC_TTIMEOUT(x)			(((x) & GENMASK(4, 0)) << 24)
+#define AST2600_I2CC_TCKHIGHMIN(x)			(((x) & GENMASK(3, 0)) << 20)
+#define AST2600_I2CC_TCKHIGH(x)			(((x) & GENMASK(3, 0)) << 16)
+#define AST2600_I2CC_TCKLOW(x)			(((x) & GENMASK(3, 0)) << 12)
+#define AST2600_I2CC_THDDAT(x)			(((x) & GENMASK(1, 0)) << 10)
+#define AST2600_I2CC_TOUTBASECLK(x)			(((x) & GENMASK(1, 0)) << 8)
+#define AST2600_I2CC_TBASECLK(x)			((x) & GENMASK(3, 0))
+
+/* 0x08 : I2CC Master/Slave Transmit/Receive Byte Buffer Register */
+#define AST2600_I2CC_STS_AND_BUFF		0x08
+#define AST2600_I2CC_TX_DIR_MASK			GENMASK(31, 29)
+#define AST2600_I2CC_SDA_OE				BIT(28)
+#define AST2600_I2CC_SDA_O				BIT(27)
+#define AST2600_I2CC_SCL_OE				BIT(26)
+#define AST2600_I2CC_SCL_O				BIT(25)
+
+#define AST2600_I2CC_SCL_LINE_STS			BIT(18)
+#define AST2600_I2CC_SDA_LINE_STS			BIT(17)
+#define AST2600_I2CC_BUS_BUSY_STS			BIT(16)
+
+#define AST2600_I2CC_GET_RX_BUFF(x)			(((x) >> 8) & GENMASK(7, 0))
+
+/* 0x0C : I2CC Master/Slave Pool Buffer Control Register  */
+#define AST2600_I2CC_BUFF_CTRL		0x0C
+#define AST2600_I2CC_GET_RX_BUF_LEN(x)		(((x) >> 24) & GENMASK(5, 0))
+#define AST2600_I2CC_SET_RX_BUF_LEN(x)		(((((x) - 1) & GENMASK(4, 0)) << 16) | BIT(0))
+#define AST2600_I2CC_SET_TX_BUF_LEN(x)		(((((x) - 1) & GENMASK(4, 0)) << 8) | BIT(0))
+#define AST2600_I2CC_GET_TX_BUF_LEN(x)		((((x) >> 8) & GENMASK(4, 0)) + 1)
+
+/* 0x10 : I2CM Master Interrupt Control Register */
+#define AST2600_I2CM_IER			0x10
+/* 0x14 : I2CM Master Interrupt Status Register   : WC */
+#define AST2600_I2CM_ISR			0x14
+
+#define AST2600_I2CM_PKT_TIMEOUT			BIT(18)
+#define AST2600_I2CM_PKT_ERROR			BIT(17)
+#define AST2600_I2CM_PKT_DONE			BIT(16)
+
+#define AST2600_I2CM_BUS_RECOVER_FAIL		BIT(15)
+#define AST2600_I2CM_SDA_DL_TO			BIT(14)
+#define AST2600_I2CM_BUS_RECOVER			BIT(13)
+#define AST2600_I2CM_SMBUS_ALT			BIT(12)
+
+#define AST2600_I2CM_SCL_LOW_TO			BIT(6)
+#define AST2600_I2CM_ABNORMAL			BIT(5)
+#define AST2600_I2CM_NORMAL_STOP			BIT(4)
+#define AST2600_I2CM_ARBIT_LOSS			BIT(3)
+#define AST2600_I2CM_RX_DONE			BIT(2)
+#define AST2600_I2CM_TX_NAK				BIT(1)
+#define AST2600_I2CM_TX_ACK				BIT(0)
+
+/* 0x18 : I2CM Master Command/Status Register   */
+#define AST2600_I2CM_CMD_STS		0x18
+#define AST2600_I2CM_PKT_ADDR(x)			(((x) & GENMASK(6, 0)) << 24)
+#define AST2600_I2CM_PKT_EN				BIT(16)
+#define AST2600_I2CM_SDA_OE_OUT_DIR			BIT(15)
+#define AST2600_I2CM_SDA_O_OUT_DIR			BIT(14)
+#define AST2600_I2CM_SCL_OE_OUT_DIR			BIT(13)
+#define AST2600_I2CM_SCL_O_OUT_DIR			BIT(12)
+#define AST2600_I2CM_RECOVER_CMD_EN			BIT(11)
+
+#define AST2600_I2CM_RX_DMA_EN			BIT(9)
+#define AST2600_I2CM_TX_DMA_EN			BIT(8)
+/* Command Bit */
+#define AST2600_I2CM_RX_BUFF_EN			BIT(7)
+#define AST2600_I2CM_TX_BUFF_EN			BIT(6)
+#define AST2600_I2CM_STOP_CMD			BIT(5)
+#define AST2600_I2CM_RX_CMD_LAST			BIT(4)
+#define AST2600_I2CM_RX_CMD				BIT(3)
+
+#define AST2600_I2CM_TX_CMD				BIT(1)
+#define AST2600_I2CM_START_CMD			BIT(0)
+
+/* 0x1C : I2CM Master DMA Transfer Length Register	 */
+#define AST2600_I2CM_DMA_LEN		0x1C
+/* Tx Rx support length 1 ~ 4096 */
+#define AST2600_I2CM_SET_RX_DMA_LEN(x)	((((x) & GENMASK(11, 0)) << 16) | BIT(31))
+#define AST2600_I2CM_SET_TX_DMA_LEN(x)	(((x) & GENMASK(11, 0)) | BIT(15))
+
+/* 0x20 : I2CS Slave Interrupt Control Register   */
+#define AST2600_I2CS_IER			0x20
+/* 0x24 : I2CS Slave Interrupt Status Register	 */
+#define AST2600_I2CS_ISR			0x24
+
+#define AST2600_I2CS_ADDR_INDICATE_MASK	GENMASK(31, 30)
+#define AST2600_I2CS_SLAVE_PENDING			BIT(29)
+
+#define AST2600_I2CS_WAIT_TX_DMA			BIT(25)
+#define AST2600_I2CS_WAIT_RX_DMA			BIT(24)
+
+#define AST2600_I2CS_ADDR3_NAK			BIT(22)
+#define AST2600_I2CS_ADDR2_NAK			BIT(21)
+#define AST2600_I2CS_ADDR1_NAK			BIT(20)
+
+#define AST2600_I2CS_ADDR_MASK			GENMASK(19, 18)
+#define AST2600_I2CS_PKT_ERROR			BIT(17)
+#define AST2600_I2CS_PKT_DONE			BIT(16)
+#define AST2600_I2CS_INACTIVE_TO			BIT(15)
+
+#define AST2600_I2CS_SLAVE_MATCH			BIT(7)
+#define AST2600_I2CS_ABNOR_STOP			BIT(5)
+#define AST2600_I2CS_STOP				BIT(4)
+#define AST2600_I2CS_RX_DONE_NAK			BIT(3)
+#define AST2600_I2CS_RX_DONE			BIT(2)
+#define AST2600_I2CS_TX_NAK				BIT(1)
+#define AST2600_I2CS_TX_ACK				BIT(0)
+
+/* 0x28 : I2CS Slave CMD/Status Register   */
+#define AST2600_I2CS_CMD_STS		0x28
+#define AST2600_I2CS_ACTIVE_ALL			GENMASK(18, 17)
+#define AST2600_I2CS_PKT_MODE_EN			BIT(16)
+#define AST2600_I2CS_AUTO_NAK_NOADDR		BIT(15)
+#define AST2600_I2CS_AUTO_NAK_EN			BIT(14)
+
+#define AST2600_I2CS_ALT_EN				BIT(10)
+#define AST2600_I2CS_RX_DMA_EN			BIT(9)
+#define AST2600_I2CS_TX_DMA_EN			BIT(8)
+#define AST2600_I2CS_RX_BUFF_EN			BIT(7)
+#define AST2600_I2CS_TX_BUFF_EN			BIT(6)
+#define AST2600_I2CS_RX_CMD_LAST			BIT(4)
+
+#define AST2600_I2CS_TX_CMD				BIT(2)
+
+#define AST2600_I2CS_DMA_LEN		0x2C
+#define AST2600_I2CS_SET_RX_DMA_LEN(x)	(((((x) - 1) & GENMASK(11, 0)) << 16) | BIT(31))
+#define AST2600_I2CS_RX_DMA_LEN_MASK	(GENMASK(11, 0) << 16)
+
+#define AST2600_I2CS_SET_TX_DMA_LEN(x)	((((x) - 1) & GENMASK(11, 0)) | BIT(15))
+#define AST2600_I2CS_TX_DMA_LEN_MASK	GENMASK(11, 0)
+
+/* I2CM Master DMA Tx Buffer Register   */
+#define AST2600_I2CM_TX_DMA			0x30
+/* I2CM Master DMA Rx Buffer Register	*/
+#define AST2600_I2CM_RX_DMA			0x34

drivers/i2c/busses/i2c-ast2600.c new file +84 -0

+
+#define AST2600_I2CM_DMA_LEN_STS		0x48
+#define AST2600_I2CS_DMA_LEN_STS		0x4C
+
+#define AST2600_I2C_GET_TX_DMA_LEN(x)		((x) & GENMASK(12, 0))
+#define AST2600_I2C_GET_RX_DMA_LEN(x)		(((x) >> 16) & GENMASK(12, 0))
+
+/* 0x40 : Slave Device Address Register */
+#define AST2600_I2CS_ADDR3_ENABLE			BIT(23)
+#define AST2600_I2CS_ADDR3(x)			((x) << 16)
+
+#define AST2600_I2CS_ADDR2_ENABLE			BIT(15)
+#define AST2600_I2CS_ADDR2(x)			((x) << 8)
+#define AST2600_I2CS_ADDR1_ENABLE			BIT(7)
+#define AST2600_I2CS_ADDR1(x)			(x)
+
+#define I2C_SLAVE_MSG_BUF_SIZE		256
+
+#define AST2600_I2C_DMA_SIZE		4096
+
+#define MASTER_TRIGGER_LAST_STOP	(AST2600_I2CM_RX_CMD_LAST | AST2600_I2CM_STOP_CMD)
+#define SLAVE_TRIGGER_CMD	(AST2600_I2CS_ACTIVE_ALL | AST2600_I2CS_PKT_MODE_EN)
+
+/* i2c timeout counter: use base clk4 1Mhz
+ * 1/(1000/4096) = 4.096ms * 8 = 32.768ms
+ */
+#define AST_I2C_TIMEOUT_CLK		0x2
+#define AST_I2C_TIMEOUT_COUNT	0x8
+
+struct ast2600_i2c_timing_table {
+	u32 divisor;
+	u32 timing;
+};
+
+enum xfer_mode {
+	BYTE_MODE = 0,
+	BUFF_MODE,
+	DMA_MODE,
+};
+
+struct ast2600_i2c_bus {
+	struct i2c_adapter		adap;
+	struct device			*dev;
+	void __iomem			*reg_base;
+	struct regmap			*gr_regmap;
+	struct reset_control		*rst;
+	int				irq;
+	enum xfer_mode			mode;
+	struct clk			*clk;
+	u32				apb_clk;
+	u32				bus_frequency;
+	int				slave_operate;
+	int				timeout_enable;
+	/* smbus alert */
+	int				alert_enable;
+	struct i2c_smbus_alert_setup	alert_data;
+	struct i2c_client		*ara;
+	/* Multi-master */
+	bool				multi_master;
+	/* master structure */
+	int				cmd_err;
+	struct completion		cmd_complete;
+	struct i2c_msg			*msgs;
+	size_t				buf_index;
+	/* cur xfer msgs index*/
+	int				msgs_index;
+	int				msgs_count;
+	u8				*master_safe_buf;
+	dma_addr_t			master_dma_addr;
+	/*total xfer count */
+	int				master_xfer_cnt;
+	/* Buffer mode */
+	void __iomem			*buf_base;
+	size_t				buf_size;
+	/* Slave structure */
+	int				slave_xfer_len;
+	int				slave_xfer_cnt;
+#ifdef CONFIG_I2C_SLAVE
+	unsigned char			*slave_dma_buf;
+	dma_addr_t			slave_dma_addr;
+	struct i2c_client		*slave;
+#endif
+};
+

drivers/i2c/busses/i2c-ast2600.c new file +158 -0

+	state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
+	if (!(state & AST2600_I2CC_SDA_LINE_STS) && (state & AST2600_I2CC_SCL_LINE_STS)) {
+		writel(AST2600_I2CM_RECOVER_CMD_EN, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
+		r = wait_for_completion_timeout(&i2c_bus->cmd_complete, i2c_bus->adap.timeout);
+		if (r == 0) {
+			dev_dbg(i2c_bus->dev, "recovery timed out\n");
+			ret = -ETIMEDOUT;
+		} else {
+			if (i2c_bus->cmd_err) {
+				dev_dbg(i2c_bus->dev, "recovery error\n");
+				ret = -EPROTO;
+			}
+		}
+	}
+
+	dev_dbg(i2c_bus->dev, "Recovery done [%x]\n",
+		readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
+	if (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) & AST2600_I2CC_BUS_BUSY_STS) {
+		dev_dbg(i2c_bus->dev, "Can't recovery bus [%x]\n",
+			readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
+	}
+
+	writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+	return ret;
+}
+
+#ifdef CONFIG_I2C_SLAVE
+static void ast2600_i2c_slave_packet_dma_irq(struct ast2600_i2c_bus *i2c_bus, u32 sts)
+{
+	int slave_rx_len;
+	u32 cmd = 0;
+	u8 value;
+	int i = 0;
+
+	sts &= ~(AST2600_I2CS_SLAVE_PENDING);
+	/* Handle i2c slave timeout condition */
+	if (AST2600_I2CS_INACTIVE_TO & sts) {
+		cmd = SLAVE_TRIGGER_CMD;
+		cmd |= AST2600_I2CS_RX_DMA_EN;
+		writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE),
+		       i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value);
+		return;
+	}
+
+	sts &= ~(AST2600_I2CS_PKT_DONE | AST2600_I2CS_PKT_ERROR);
+
+	switch (sts) {
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_RX_DMA:
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_WAIT_RX_DMA:
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
+		slave_rx_len = AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
+						      AST2600_I2CS_DMA_LEN_STS));
+		for (i = 0; i < slave_rx_len; i++) {
+			i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED,
+					&i2c_bus->slave_dma_buf[i]);
+		}
+		writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE),
+				i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN;
+		break;
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_STOP:
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value);
+		writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE),
+				i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN;
+		break;
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE_NAK |
+			AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_WAIT_RX_DMA |
+			AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+	case AST2600_I2CS_RX_DONE_NAK | AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+	case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_RX_DMA | AST2600_I2CS_STOP:
+	case AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+	case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_RX_DMA:
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+		if (sts & AST2600_I2CS_SLAVE_MATCH)
+			i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
+
+		slave_rx_len = AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
+						      AST2600_I2CS_DMA_LEN_STS));
+		for (i = 0; i < slave_rx_len; i++) {
+			i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED,
+					&i2c_bus->slave_dma_buf[i]);
+		}
+		writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE),
+		       i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		if (sts & AST2600_I2CS_STOP)
+			i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN;
+		break;
+
+	/* it is Mw data Mr coming -> it need send tx */
+	case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_TX_DMA:
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_TX_DMA:
+		/* it should be repeat start read */
+		if (sts & AST2600_I2CS_SLAVE_MATCH)
+			i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
+
+		slave_rx_len = AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
+						      AST2600_I2CS_DMA_LEN_STS));
+		for (i = 0; i < slave_rx_len; i++) {
+			i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED,
+					&i2c_bus->slave_dma_buf[i]);
+		}
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_REQUESTED,
+				&i2c_bus->slave_dma_buf[0]);
+		writel(0, i2c_bus->reg_base + AST2600_I2CS_DMA_LEN_STS);
+		writel(AST2600_I2CS_SET_TX_DMA_LEN(1),
+				i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_TX_DMA_EN;
+		break;
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_WAIT_TX_DMA:
+		/* First Start read */
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_REQUESTED,
+				&i2c_bus->slave_dma_buf[0]);
+		writel(AST2600_I2CS_SET_TX_DMA_LEN(1),
+				i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_TX_DMA_EN;
+		break;
+	case AST2600_I2CS_WAIT_TX_DMA:
+		/* it should be next start read */
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_PROCESSED,
+				&i2c_bus->slave_dma_buf[0]);
+		writel(0, i2c_bus->reg_base + AST2600_I2CS_DMA_LEN_STS);
+		writel(AST2600_I2CS_SET_TX_DMA_LEN(1),
+				i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_TX_DMA_EN;
+		break;
+
+	case AST2600_I2CS_TX_NAK | AST2600_I2CS_STOP:
+		/* it just tx complete */
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value);
+		writel(0, i2c_bus->reg_base + AST2600_I2CS_DMA_LEN_STS);
+		writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE),
+		       i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN;
+		break;
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE:
+		cmd = 0;
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
+		break;
+	case AST2600_I2CS_STOP:
+		cmd = 0;
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value);
+		break;
+	default:
+		dev_dbg(i2c_bus->dev, "todo slave isr case %x, sts %x\n", sts,
+			readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
+		break;
+	}
+
+	if (cmd)
+		writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+	writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_ISR);
+	readl(i2c_bus->reg_base + AST2600_I2CS_ISR);
+	dev_dbg(i2c_bus->dev, "cmd %x\n", cmd);

drivers/i2c/busses/i2c-ast2600.c new file +11 -0

+		writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base + AST2600_I2CM_ISR);
+		complete(&i2c_bus->cmd_complete);
+		return 1;
+	}
+
+	if (AST2600_I2CM_PKT_DONE & sts) {
+		ast2600_i2c_master_package_irq(i2c_bus, sts);
+		return 1;
+	}
+
+	return 0;

drivers/i2c/busses/i2c-ast2600.c new file +7 -0

+			return IRQ_HANDLED;
+		}
+	}
+#endif
+	return ast2600_i2c_master_irq(i2c_bus) ? IRQ_HANDLED : IRQ_NONE;
+}
+

drivers/i2c/busses/i2c-ast2600.c new file +12 -0

+
+static int ast2600_i2c_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct ast2600_i2c_bus *i2c_bus;
+	struct resource *res;
+	u32 global_ctrl;
+	int ret = 0;
+
+	i2c_bus = devm_kzalloc(&pdev->dev, sizeof(*i2c_bus), GFP_KERNEL);
+	if (!i2c_bus)
+		return -ENOMEM;

drivers/i2c/busses/i2c-ast2600.c new file +6 -0

+	if (IS_ERR(i2c_bus->gr_regmap)) {
+		dev_err(&pdev->dev, "failed to find ast2600 i2c global regmap\n");
+		ret = -ENOMEM;
+		goto free_mem;
+	}
+

drivers/i2c/busses/i2c-ast2600.c new file +13 -0

+		i2c_bus->timeout_enable = 1;
+
+	i2c_bus->dev = &pdev->dev;
+	init_completion(&i2c_bus->cmd_complete);
+
+	i2c_bus->reg_base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(i2c_bus->reg_base)) {
+		ret = PTR_ERR(i2c_bus->reg_base);
+		goto free_mem;
+	}
+
+	i2c_bus->irq = platform_get_irq(pdev, 0);
+	if (i2c_bus->irq < 0) {

drivers/i2c/busses/i2c-ast2600.c new file +15 -0

+
+	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &i2c_bus->bus_frequency);
+	if (ret < 0) {
+		dev_warn(&pdev->dev, "Could not read bus-frequency property\n");
+		i2c_bus->bus_frequency = 100000;
+	}
+
+	/* Initialize the I2C adapter */
+	i2c_bus->adap.owner = THIS_MODULE;
+	i2c_bus->adap.algo = &i2c_ast2600_algorithm;
+	i2c_bus->adap.retries = 0;
+	i2c_bus->adap.dev.parent = i2c_bus->dev;
+	i2c_bus->adap.dev.of_node = pdev->dev.of_node;
+	i2c_bus->adap.algo_data = i2c_bus;
+	strscpy(i2c_bus->adap.name, pdev->name, sizeof(i2c_bus->adap.name));

drivers/i2c/busses/i2c-ast2600.c new file +5 -0

+
+	return ret;
+}
+
+static int ast2600_i2c_remove(struct platform_device *pdev)

drivers/i2c/busses/i2c-ast2600.c new file +14 -0

+
+#ifdef CONFIG_I2C_SLAVE
+	/* for memory buffer initial */
+	if (i2c_bus->mode == DMA_MODE)
+		dma_free_coherent(i2c_bus->dev, I2C_SLAVE_MSG_BUF_SIZE,
+				i2c_bus->slave_dma_buf, i2c_bus->slave_dma_addr);
+#endif
+
+	return 0;
+}
+
+static struct platform_driver ast2600_i2c_bus_driver = {
+	.probe = ast2600_i2c_probe,
+	.remove = ast2600_i2c_remove,

On 20/02/2023 07:17, Ryan Chen wrote:

Quoted 18 lines

drivers/i2c/busses/i2c-ast2600.c new file +18 -0

+	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &i2c_bus->bus_frequency);
+	if (ret < 0) {
+		dev_warn(&pdev->dev, "Could not read bus-frequency property\n");
+		i2c_bus->bus_frequency = 100000;
+	}
+
+	/* Initialize the I2C adapter */
+	i2c_bus->adap.owner = THIS_MODULE;
+	i2c_bus->adap.algo = &i2c_ast2600_algorithm;
+	i2c_bus->adap.retries = 0;
+	i2c_bus->adap.dev.parent = i2c_bus->dev;
+	i2c_bus->adap.dev.of_node = pdev->dev.of_node;
+	i2c_bus->adap.algo_data = i2c_bus;
+	strscpy(i2c_bus->adap.name, pdev->name, sizeof(i2c_bus->adap.name));
+	i2c_set_adapdata(&i2c_bus->adap, i2c_bus);
+
+	ast2600_i2c_init(i2c_bus);
+

drivers/i2c/busses/i2c-ast2600.c line 1634

Quoted 6 lines

drivers/i2c/busses/i2c-ast2600.c new file +6 -0

+	ret = devm_request_irq(&pdev->dev, i2c_bus->irq, ast2600_i2c_bus_irq, 0,
+			       dev_name(&pdev->dev), i2c_bus);
+	if (ret < 0)
+		goto unmap;
+
+	if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) {

There is no such property. Don't add undocumented properties to your code.

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Monday, February 20, 2023 4:44 PM
To: Ryan Chen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Joel Stanley <[email protected]>; Andrew Jeffery <[email protected]>; Philipp Zabel <[email protected]>; openbmc at lists.ozlabs.org; linux-arm-kernel at lists.infradead.org; linux-aspeed at lists.ozlabs.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH v5 2/2] i2c: aspeed: support ast2600 i2cv2 new register mode driver

MAINTAINERS F:

Quoted 21 lines · Ryan Chen

Add i2cv2 new register mode driver to support AST2600 i2c new register mode. AST2600 i2c controller have legacy and new register mode. The new register mode have global register support 4 base clock for scl clock selection, and new clock divider mode. The i2c new register mode have separate register set to control i2c master and slave.

Signed-off-by Ryan Chen <[email protected]>

---
 MAINTAINERS                      |    9 +
 drivers/i2c/busses/Kconfig       |   11 +
 drivers/i2c/busses/Makefile      |    1 +
 drivers/i2c/busses/i2c-ast2600.c | 1703
++++++++++++++++++++++++++++++
 4 files changed, 1724 insertions(+)
 create mode 100644 drivers/i2c/busses/i2c-ast2600.c

MAINTAINERS index renamed from MAINTAINERS +0 -0

749710e22b4d..c9841568cb24 100644

MAINTAINERS +0 -0

@@ -1924,6 +1924,15 @@ F:

Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-
i2c-ic.

Quoted 42 lines

MAINTAINERS +9 -0

 F:	drivers/i2c/busses/i2c-aspeed.c
 F:	drivers/irqchip/irq-aspeed-i2c-ic.c
 
+ARM/ASPEED I2CV2 DRIVER
+M:      Ryan Chen <[email protected]>
+R:      Andrew Jeffery <[email protected]>
+L:      linux-i2c at vger.kernel.org
+L:      openbmc at lists.ozlabs.org (moderated for non-subscribers)
+S:      Maintained
+F:      Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml
+F:      drivers/i2c/busses/i2c-ast2600.c
+
 ARM/ASPEED MACHINE SUPPORT
 M:	Joel Stanley <[email protected]>
 R:	Andrew Jeffery <[email protected]>

drivers/i2c/busses/Kconfig +11 -0

index 7284206b278b..f3f7500ce768 100644
@@ -389,6 +389,17 @@ config I2C_ALTERA
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-altera.
 
+config I2C_AST2600
+	tristate "Aspeed I2C v2 Controller"
+	depends on ARCH_ASPEED || COMPILE_TEST
+	select I2C_SMBUS
+	help
+	  If you say yes to this option, support will be included for the
+	  Aspeed I2C controller with new register set.
+
+	  This driver can also be built as a module.  If so, the module
+	  will be called i2c-new-aspeed.
+
 config I2C_ASPEED
 	tristate "Aspeed I2C Controller"
 	depends on ARCH_ASPEED || COMPILE_TEST diff --git

a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index c5cac15f075c..d0ab4d45781c 100644

drivers/i2c/busses/Makefile obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o · line 39

Quoted 2 lines

drivers/i2c/busses/Makefile +0 -0

@@ -38,6 +38,7 @@ obj-$(CONFIG_I2C_POWERMAC)	+= i2c-powermac.o
 obj-$(CONFIG_I2C_ALTERA)	+= i2c-altera.o
 obj-$(CONFIG_I2C_AMD_MP2)	+= i2c-amd-mp2-pci.o

i2c-amd-mp2-plat.o

Quoted 63 lines

drivers/i2c/busses/Makefile +1 -0

 obj-$(CONFIG_I2C_ASPEED)	+= i2c-aspeed.o
+obj-$(CONFIG_I2C_AST2600)	+= i2c-ast2600.o
 obj-$(CONFIG_I2C_AT91)		+= i2c-at91.o
 i2c-at91-objs			:= i2c-at91-core.o i2c-at91-master.o
 ifeq ($(CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL),y)

drivers/i2c/busses/i2c-ast2600.c new file +51 -0

new file mode 100644
index 000000000000..b5fe0af57d11
@@ -0,0 +1,1703 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * ASPEED AST2600 new register set I2C controller driver
+ *
+ * Copyright (C) ASPEED Technology Inc.
+ */
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/reset.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/of_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/i2c-smbus.h>
+
+/*
+ * APB clk : 100Mhz
+ * div	: scl		: baseclk [APB/((div/2) + 1)] : tBuf [1/bclk * 16]
+ * I2CG10[31:24] base clk4 for i2c auto recovery timeout counter
+(0xC6)
+ * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
+ * 0x3c : 100.8Khz	: 3.225Mhz					  : 4.96us
+ * 0x3d : 99.2Khz	: 3.174Mhz					  : 5.04us
+ * 0x3e : 97.65Khz	: 3.125Mhz					  : 5.12us
+ * 0x40 : 97.75Khz	: 3.03Mhz					  : 5.28us
+ * 0x41 : 99.5Khz	: 2.98Mhz					  : 5.36us (default)
+ * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
+ * 0x12 : 400Khz	: 10Mhz						  : 1.6us
+ * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us
+ * 0x08 : 1Mhz		: 20Mhz						  : 0.8us
+ */
+#define AST2600_I2CG_ISR			0x00
+#define AST2600_I2CG_SLAVE_ISR		0x04
+#define AST2600_I2CG_OWNER		0x08
+#define AST2600_I2CG_CTRL		0x0C
+#define AST2600_I2CG_CLK_DIV_CTRL	0x10
+
+#define AST2600_I2CG_SLAVE_PKT_NAK	BIT(4)
+#define AST2600_I2CG_M_S_SEPARATE_INTR	BIT(3)
+#define AST2600_I2CG_CTRL_NEW_REG	BIT(2)
+#define AST2600_I2CG_CTRL_NEW_CLK_DIV	BIT(1)
+

drivers/i2c/busses/i2c-ast2600.c line 61

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drivers/i2c/busses/i2c-ast2600.c new file +10 -0

+#define AST2600_GLOBAL_INIT				\
+			(AST2600_I2CG_CTRL_NEW_REG |	\
+			AST2600_I2CG_CTRL_NEW_CLK_DIV)
+#define I2CCG_DIV_CTRL 0xC6411208
+
+/* 0x00 : I2CC Master/Slave Function Control Register  */
+#define AST2600_I2CC_FUN_CTRL		0x00
+#define AST2600_I2CC_SLAVE_ADDR_RX_EN		BIT(20)
+#define AST2600_I2CC_MASTER_RETRY_MASK		GENMASK(19, 18)
+#define AST2600_I2CC_MASTER_RETRY(x)		(((x) & GENMASK(1, 0))

<< 18)

Quoted 5 lines

drivers/i2c/busses/i2c-ast2600.c new file +5 -0

+#define AST2600_I2CC_BUS_AUTO_RELEASE		BIT(17)
+#define AST2600_I2CC_M_SDA_LOCK_EN			BIT(16)
+#define AST2600_I2CC_MULTI_MASTER_DIS		BIT(15)
+#define AST2600_I2CC_M_SCL_DRIVE_EN			BIT(14)
+#define AST2600_I2CC_MSB_STS				BIT(9)

drivers/i2c/busses/i2c-ast2600.c

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drivers/i2c/busses/i2c-ast2600.c new file +10 -0

+#define AST2600_I2CC_SDA_DRIVE_1T_EN		BIT(8)
+#define AST2600_I2CC_M_SDA_DRIVE_1T_EN		BIT(7)
+#define AST2600_I2CC_M_HIGH_SPEED_EN		BIT(6)
+/* reserver 5 : 2 */
+#define AST2600_I2CC_SLAVE_EN			BIT(1)
+#define AST2600_I2CC_MASTER_EN			BIT(0)
+
+/* 0x04 : I2CC Master/Slave Clock and AC Timing Control Register #1 */
+#define AST2600_I2CC_AC_TIMING		0x04
+#define AST2600_I2CC_TTIMEOUT(x)			(((x) & GENMASK(4, 0))

<< 24)

drivers/i2c/busses/i2c-ast2600.c line 77

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drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+#define AST2600_I2CC_TCKHIGHMIN(x)			(((x) & GENMASK(3, 0))

<< 20)

drivers/i2c/busses/i2c-ast2600.c line 78

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drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+#define AST2600_I2CC_TCKHIGH(x)			(((x) & GENMASK(3, 0)) <<

16)

drivers/i2c/busses/i2c-ast2600.c line 79

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drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+#define AST2600_I2CC_TCKLOW(x)			(((x) & GENMASK(3, 0)) <<

12)

drivers/i2c/busses/i2c-ast2600.c line 80

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drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+#define AST2600_I2CC_THDDAT(x)			(((x) & GENMASK(1, 0)) <<

10)

drivers/i2c/busses/i2c-ast2600.c line 81

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drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+#define AST2600_I2CC_TOUTBASECLK(x)			(((x) & GENMASK(1, 0))

<< 8)

Quoted 5 lines

drivers/i2c/busses/i2c-ast2600.c new file +5 -0

+#define AST2600_I2CC_TBASECLK(x)			((x) & GENMASK(3, 0))
+
+/* 0x08 : I2CC Master/Slave Transmit/Receive Byte Buffer Register */
+#define AST2600_I2CC_STS_AND_BUFF		0x08
+#define AST2600_I2CC_TX_DIR_MASK			GENMASK(31, 29)

drivers/i2c/busses/i2c-ast2600.c

Quoted 10 lines

drivers/i2c/busses/i2c-ast2600.c new file +10 -0

+#define AST2600_I2CC_SDA_OE				BIT(28)
+#define AST2600_I2CC_SDA_O				BIT(27)
+#define AST2600_I2CC_SCL_OE				BIT(26)
+#define AST2600_I2CC_SCL_O				BIT(25)
+
+#define AST2600_I2CC_SCL_LINE_STS			BIT(18)
+#define AST2600_I2CC_SDA_LINE_STS			BIT(17)
+#define AST2600_I2CC_BUS_BUSY_STS			BIT(16)
+
+#define AST2600_I2CC_GET_RX_BUFF(x)			(((x) >> 8) &

GENMASK(7, 0))

drivers/i2c/busses/i2c-ast2600.c

Quoted 4 lines

drivers/i2c/busses/i2c-ast2600.c new file +4 -0

+
+/* 0x0C : I2CC Master/Slave Pool Buffer Control Register  */
+#define AST2600_I2CC_BUFF_CTRL		0x0C
+#define AST2600_I2CC_GET_RX_BUF_LEN(x)		(((x) >> 24) &

GENMASK(5, 0))

drivers/i2c/busses/i2c-ast2600.c line 101

Quoted 1 line

drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+#define AST2600_I2CC_SET_RX_BUF_LEN(x)		(((((x) - 1) & GENMASK(4,

0)) << 16) | BIT(0))

drivers/i2c/busses/i2c-ast2600.c line 102

Quoted 1 line

drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+#define AST2600_I2CC_SET_TX_BUF_LEN(x)		(((((x) - 1) & GENMASK(4,

0)) << 8) | BIT(0))

drivers/i2c/busses/i2c-ast2600.c line 103

Quoted 1 line

drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+#define AST2600_I2CC_GET_TX_BUF_LEN(x)		((((x) >> 8) &

GENMASK(4, 0)) + 1)

Quoted 16 lines

drivers/i2c/busses/i2c-ast2600.c new file +16 -0

+
+/* 0x10 : I2CM Master Interrupt Control Register */
+#define AST2600_I2CM_IER			0x10
+/* 0x14 : I2CM Master Interrupt Status Register   : WC */
+#define AST2600_I2CM_ISR			0x14
+
+#define AST2600_I2CM_PKT_TIMEOUT			BIT(18)
+#define AST2600_I2CM_PKT_ERROR			BIT(17)
+#define AST2600_I2CM_PKT_DONE			BIT(16)
+
+#define AST2600_I2CM_BUS_RECOVER_FAIL		BIT(15)
+#define AST2600_I2CM_SDA_DL_TO			BIT(14)
+#define AST2600_I2CM_BUS_RECOVER			BIT(13)
+#define AST2600_I2CM_SMBUS_ALT			BIT(12)
+
+#define AST2600_I2CM_SCL_LOW_TO			BIT(6)

drivers/i2c/busses/i2c-ast2600.c

Quoted 10 lines

drivers/i2c/busses/i2c-ast2600.c new file +10 -0

+#define AST2600_I2CM_ABNORMAL			BIT(5)
+#define AST2600_I2CM_NORMAL_STOP			BIT(4)
+#define AST2600_I2CM_ARBIT_LOSS			BIT(3)
+#define AST2600_I2CM_RX_DONE			BIT(2)
+#define AST2600_I2CM_TX_NAK				BIT(1)
+#define AST2600_I2CM_TX_ACK				BIT(0)
+
+/* 0x18 : I2CM Master Command/Status Register   */
+#define AST2600_I2CM_CMD_STS		0x18
+#define AST2600_I2CM_PKT_ADDR(x)			(((x) & GENMASK(6, 0))

<< 24)

Quoted 13 lines

drivers/i2c/busses/i2c-ast2600.c new file +13 -0

+#define AST2600_I2CM_PKT_EN				BIT(16)
+#define AST2600_I2CM_SDA_OE_OUT_DIR			BIT(15)
+#define AST2600_I2CM_SDA_O_OUT_DIR			BIT(14)
+#define AST2600_I2CM_SCL_OE_OUT_DIR			BIT(13)
+#define AST2600_I2CM_SCL_O_OUT_DIR			BIT(12)
+#define AST2600_I2CM_RECOVER_CMD_EN			BIT(11)
+
+#define AST2600_I2CM_RX_DMA_EN			BIT(9)
+#define AST2600_I2CM_TX_DMA_EN			BIT(8)
+/* Command Bit */
+#define AST2600_I2CM_RX_BUFF_EN			BIT(7)
+#define AST2600_I2CM_TX_BUFF_EN			BIT(6)
+#define AST2600_I2CM_STOP_CMD			BIT(5)

drivers/i2c/busses/i2c-ast2600.c

Quoted 10 lines

drivers/i2c/busses/i2c-ast2600.c new file +10 -0

+#define AST2600_I2CM_RX_CMD_LAST			BIT(4)
+#define AST2600_I2CM_RX_CMD				BIT(3)
+
+#define AST2600_I2CM_TX_CMD				BIT(1)
+#define AST2600_I2CM_START_CMD			BIT(0)
+
+/* 0x1C : I2CM Master DMA Transfer Length Register	 */
+#define AST2600_I2CM_DMA_LEN		0x1C
+/* Tx Rx support length 1 ~ 4096 */
+#define AST2600_I2CM_SET_RX_DMA_LEN(x)	((((x) & GENMASK(11, 0))

<< 16) | BIT(31))

drivers/i2c/busses/i2c-ast2600.c line 153

Quoted 1 line

drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+#define AST2600_I2CM_SET_TX_DMA_LEN(x)	(((x) & GENMASK(11, 0)) |

BIT(15))

Quoted 37 lines

drivers/i2c/busses/i2c-ast2600.c new file +37 -0

+
+/* 0x20 : I2CS Slave Interrupt Control Register   */
+#define AST2600_I2CS_IER			0x20
+/* 0x24 : I2CS Slave Interrupt Status Register	 */
+#define AST2600_I2CS_ISR			0x24
+
+#define AST2600_I2CS_ADDR_INDICATE_MASK	GENMASK(31, 30)
+#define AST2600_I2CS_SLAVE_PENDING			BIT(29)
+
+#define AST2600_I2CS_WAIT_TX_DMA			BIT(25)
+#define AST2600_I2CS_WAIT_RX_DMA			BIT(24)
+
+#define AST2600_I2CS_ADDR3_NAK			BIT(22)
+#define AST2600_I2CS_ADDR2_NAK			BIT(21)
+#define AST2600_I2CS_ADDR1_NAK			BIT(20)
+
+#define AST2600_I2CS_ADDR_MASK			GENMASK(19, 18)
+#define AST2600_I2CS_PKT_ERROR			BIT(17)
+#define AST2600_I2CS_PKT_DONE			BIT(16)
+#define AST2600_I2CS_INACTIVE_TO			BIT(15)
+
+#define AST2600_I2CS_SLAVE_MATCH			BIT(7)
+#define AST2600_I2CS_ABNOR_STOP			BIT(5)
+#define AST2600_I2CS_STOP				BIT(4)
+#define AST2600_I2CS_RX_DONE_NAK			BIT(3)
+#define AST2600_I2CS_RX_DONE			BIT(2)
+#define AST2600_I2CS_TX_NAK				BIT(1)
+#define AST2600_I2CS_TX_ACK				BIT(0)
+
+/* 0x28 : I2CS Slave CMD/Status Register   */
+#define AST2600_I2CS_CMD_STS		0x28
+#define AST2600_I2CS_ACTIVE_ALL			GENMASK(18, 17)
+#define AST2600_I2CS_PKT_MODE_EN			BIT(16)
+#define AST2600_I2CS_AUTO_NAK_NOADDR		BIT(15)
+#define AST2600_I2CS_AUTO_NAK_EN			BIT(14)
+
+#define AST2600_I2CS_ALT_EN				BIT(10)

drivers/i2c/busses/i2c-ast2600.c

Quoted 10 lines

drivers/i2c/busses/i2c-ast2600.c new file +10 -0

+#define AST2600_I2CS_RX_DMA_EN			BIT(9)
+#define AST2600_I2CS_TX_DMA_EN			BIT(8)
+#define AST2600_I2CS_RX_BUFF_EN			BIT(7)
+#define AST2600_I2CS_TX_BUFF_EN			BIT(6)
+#define AST2600_I2CS_RX_CMD_LAST			BIT(4)
+
+#define AST2600_I2CS_TX_CMD				BIT(2)
+
+#define AST2600_I2CS_DMA_LEN		0x2C
+#define AST2600_I2CS_SET_RX_DMA_LEN(x)	(((((x) - 1) & GENMASK(11, 0))

<< 16) | BIT(31))

drivers/i2c/busses/i2c-ast2600.c

Quoted 3 lines

drivers/i2c/busses/i2c-ast2600.c new file +3 -0

+#define AST2600_I2CS_RX_DMA_LEN_MASK	(GENMASK(11, 0) << 16)
+
+#define AST2600_I2CS_SET_TX_DMA_LEN(x)	((((x) - 1) & GENMASK(11, 0))

| BIT(15))

Quoted 10 lines

drivers/i2c/busses/i2c-ast2600.c new file +10 -0

+#define AST2600_I2CS_TX_DMA_LEN_MASK	GENMASK(11, 0)
+
+/* I2CM Master DMA Tx Buffer Register   */
+#define AST2600_I2CM_TX_DMA			0x30
+/* I2CM Master DMA Rx Buffer Register	*/
+#define AST2600_I2CM_RX_DMA			0x34
+/* I2CS Slave DMA Tx Buffer Register   */
+#define AST2600_I2CS_TX_DMA			0x38
+/* I2CS Slave DMA Rx Buffer Register   */
+#define AST2600_I2CS_RX_DMA			0x3C

drivers/i2c/busses/i2c-ast2600.c line 218

Quoted 6 lines

drivers/i2c/busses/i2c-ast2600.c new file +6 -0

+
+#define AST2600_I2CS_ADDR_CTRL		0x40
+
+#define	AST2600_I2CS_ADDR3_MASK		GENMASK(22, 16)
+#define	AST2600_I2CS_ADDR2_MASK		GENMASK(14, 8)
+#define	AST2600_I2CS_ADDR1_MASK		GENMASK(6, 0)

Drop indent after #define

drivers/i2c/busses/i2c-ast2600.c

Quoted 7 lines

drivers/i2c/busses/i2c-ast2600.c new file +6 -0

+
+#define AST2600_I2CM_DMA_LEN_STS		0x48
+#define AST2600_I2CS_DMA_LEN_STS		0x4C
+
+#define AST2600_I2C_GET_TX_DMA_LEN(x)		((x) & GENMASK(12, 0))
+#define AST2600_I2C_GET_RX_DMA_LEN(x)		(((x) >> 16) &

GENMASK(12, 0))

Quoted 5 lines

drivers/i2c/busses/i2c-ast2600.c new file +5 -0

+
+/* 0x40 : Slave Device Address Register */
+#define AST2600_I2CS_ADDR3_ENABLE			BIT(23)
+#define AST2600_I2CS_ADDR3(x)			((x) << 16)
+

drivers/i2c/busses/i2c-ast2600.c

Quoted 10 lines

drivers/i2c/busses/i2c-ast2600.c new file +10 -0

+#define AST2600_I2CS_ADDR2_ENABLE			BIT(15)
+#define AST2600_I2CS_ADDR2(x)			((x) << 8)
+#define AST2600_I2CS_ADDR1_ENABLE			BIT(7)
+#define AST2600_I2CS_ADDR1(x)			(x)
+
+#define I2C_SLAVE_MSG_BUF_SIZE		256
+
+#define AST2600_I2C_DMA_SIZE		4096
+
+#define MASTER_TRIGGER_LAST_STOP	(AST2600_I2CM_RX_CMD_LAST |

AST2600_I2CM_STOP_CMD)

drivers/i2c/busses/i2c-ast2600.c line 241

Quoted 1 line

drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+#define SLAVE_TRIGGER_CMD	(AST2600_I2CS_ACTIVE_ALL |

AST2600_I2CS_PKT_MODE_EN)

Quoted 61 lines

drivers/i2c/busses/i2c-ast2600.c new file +61 -0

+
+/* i2c timeout counter: use base clk4 1Mhz
+ * 1/(1000/4096) = 4.096ms * 8 = 32.768ms  */
+#define AST_I2C_TIMEOUT_CLK		0x2
+#define AST_I2C_TIMEOUT_COUNT	0x8
+
+struct ast2600_i2c_timing_table {
+	u32 divisor;
+	u32 timing;
+};
+
+enum xfer_mode {
+	BYTE_MODE = 0,
+	BUFF_MODE,
+	DMA_MODE,
+};
+
+struct ast2600_i2c_bus {
+	struct i2c_adapter		adap;
+	struct device			*dev;
+	void __iomem			*reg_base;
+	struct regmap			*gr_regmap;
+	struct reset_control		*rst;
+	int				irq;
+	enum xfer_mode			mode;
+	struct clk			*clk;
+	u32				apb_clk;
+	u32				bus_frequency;
+	int				slave_operate;
+	int				timeout_enable;
+	/* smbus alert */
+	int				alert_enable;
+	struct i2c_smbus_alert_setup	alert_data;
+	struct i2c_client		*ara;
+	/* Multi-master */
+	bool				multi_master;
+	/* master structure */
+	int				cmd_err;
+	struct completion		cmd_complete;
+	struct i2c_msg			*msgs;
+	size_t				buf_index;
+	/* cur xfer msgs index*/
+	int				msgs_index;
+	int				msgs_count;
+	u8				*master_safe_buf;
+	dma_addr_t			master_dma_addr;
+	/*total xfer count */
+	int				master_xfer_cnt;
+	/* Buffer mode */
+	void __iomem			*buf_base;
+	size_t				buf_size;
+	/* Slave structure */
+	int				slave_xfer_len;
+	int				slave_xfer_cnt;
+#ifdef CONFIG_I2C_SLAVE
+	unsigned char			*slave_dma_buf;
+	dma_addr_t			slave_dma_addr;
+	struct i2c_client		*slave;
+#endif
+};
+

(...)

drivers/i2c/busses/i2c-ast2600.c line 385

Quoted 2 lines

drivers/i2c/busses/i2c-ast2600.c new file +2 -0

+
+	//Check 0x14's SDA and SCL status

Use Linux coding style. See Coding style document.

drivers/i2c/busses/i2c-ast2600.c

Quoted 3 lines

drivers/i2c/busses/i2c-ast2600.c new file +2 -0

+	state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
+	if (!(state & AST2600_I2CC_SDA_LINE_STS) && (state &

AST2600_I2CC_SCL_LINE_STS)) {

drivers/i2c/busses/i2c-ast2600.c

Quoted 1 line

drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+		writel(AST2600_I2CM_RECOVER_CMD_EN, i2c_bus->reg_base +

AST2600_I2CM_CMD_STS);

drivers/i2c/busses/i2c-ast2600.c

Quoted 1 line

drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+		r = wait_for_completion_timeout(&i2c_bus->cmd_complete,

i2c_bus->adap.timeout);

Quoted 4 lines

drivers/i2c/busses/i2c-ast2600.c new file +4 -0

+		if (r == 0) {
+			dev_dbg(i2c_bus->dev, "recovery timed out\n");
+			ret = -ETIMEDOUT;
+		} else {

drivers/i2c/busses/i2c-ast2600.c

Quoted 10 lines

drivers/i2c/busses/i2c-ast2600.c new file +10 -0

+			if (i2c_bus->cmd_err) {
+				dev_dbg(i2c_bus->dev, "recovery error\n");
+				ret = -EPROTO;
+			}
+		}
+	}
+
+	dev_dbg(i2c_bus->dev, "Recovery done [%x]\n",
+		readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
+	if (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) &

AST2600_I2CC_BUS_BUSY_STS) {

Quoted 12 lines

drivers/i2c/busses/i2c-ast2600.c new file +12 -0

+		dev_dbg(i2c_bus->dev, "Can't recovery bus [%x]\n",
+			readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
+	}
+
+	writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+	return ret;
+}
+
+#ifdef CONFIG_I2C_SLAVE
+static void ast2600_i2c_slave_packet_dma_irq(struct ast2600_i2c_bus
+*i2c_bus, u32 sts) {
+	int slave_rx_len;

drivers/i2c/busses/i2c-ast2600.c line 431

Quoted 10 lines

drivers/i2c/busses/i2c-ast2600.c new file +10 -0

+	u32 cmd = 0;
+	u8 value;
+	int i = 0;
+
+	sts &= ~(AST2600_I2CS_SLAVE_PENDING);
+	/* Handle i2c slave timeout condition */
+	if (AST2600_I2CS_INACTIVE_TO & sts) {
+		cmd = SLAVE_TRIGGER_CMD;
+		cmd |= AST2600_I2CS_RX_DMA_EN;
+

	writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE),

drivers/i2c/busses/i2c-ast2600.c

Quoted 10 lines

drivers/i2c/busses/i2c-ast2600.c new file +10 -0

+		       i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value);
+		return;
+	}
+
+	sts &= ~(AST2600_I2CS_PKT_DONE | AST2600_I2CS_PKT_ERROR);
+
+	switch (sts) {
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE |

AST2600_I2CS_WAIT_RX_DMA:

drivers/i2c/busses/i2c-ast2600.c

Quoted 2 lines

drivers/i2c/busses/i2c-ast2600.c new file +2 -0

+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_WAIT_RX_DMA:
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_REQUESTED,

&value);

drivers/i2c/busses/i2c-ast2600.c

Quoted 1 line

drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+		slave_rx_len =

AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +

drivers/i2c/busses/i2c-ast2600.c line 465

Quoted 6 lines

drivers/i2c/busses/i2c-ast2600.c new file +6 -0

+						      AST2600_I2CS_DMA_LEN_STS));
+		for (i = 0; i < slave_rx_len; i++) {
+			i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED,
+					&i2c_bus->slave_dma_buf[i]);
+		}
+

	writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE),

drivers/i2c/busses/i2c-ast2600.c line 465

Quoted 6 lines

drivers/i2c/busses/i2c-ast2600.c new file +6 -0

+				i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN;
+		break;
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_STOP:
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value);
+

	writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE),

drivers/i2c/busses/i2c-ast2600.c

Quoted 8 lines

drivers/i2c/busses/i2c-ast2600.c new file +8 -0

+				i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN;
+		break;
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE_NAK |
+			AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_WAIT_RX_DMA |
+			AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+	case AST2600_I2CS_RX_DONE_NAK | AST2600_I2CS_RX_DONE |

AST2600_I2CS_STOP:

drivers/i2c/busses/i2c-ast2600.c

Quoted 1 line

drivers/i2c/busses/i2c-ast2600.c new file +1 -0

+	case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_RX_DMA |

AST2600_I2CS_STOP:

drivers/i2c/busses/i2c-ast2600.c

Quoted 3 lines

drivers/i2c/busses/i2c-ast2600.c new file +3 -0

+	case AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+	case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_RX_DMA:
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE |

AST2600_I2CS_STOP:

drivers/i2c/busses/i2c-ast2600.c

Quoted 2 lines

drivers/i2c/busses/i2c-ast2600.c new file +2 -0

+		if (sts & AST2600_I2CS_SLAVE_MATCH)
+			i2c_slave_event(i2c_bus->slave,

I2C_SLAVE_WRITE_REQUESTED,

drivers/i2c/busses/i2c-ast2600.c

Quoted 3 lines

+&value);

drivers/i2c/busses/i2c-ast2600.c new file +2 -0

+
+		slave_rx_len =

AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +

drivers/i2c/busses/i2c-ast2600.c line 465

Quoted 6 lines

drivers/i2c/busses/i2c-ast2600.c new file +6 -0

+						      AST2600_I2CS_DMA_LEN_STS));
+		for (i = 0; i < slave_rx_len; i++) {
+			i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED,
+					&i2c_bus->slave_dma_buf[i]);
+		}
+

	writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE),

drivers/i2c/busses/i2c-ast2600.c

Quoted 9 lines

drivers/i2c/busses/i2c-ast2600.c new file +9 -0

+		       i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		if (sts & AST2600_I2CS_STOP)
+			i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN;
+		break;
+
+	/* it is Mw data Mr coming -> it need send tx */
+	case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_TX_DMA:
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE |

AST2600_I2CS_WAIT_TX_DMA:

drivers/i2c/busses/i2c-ast2600.c

Quoted 3 lines

drivers/i2c/busses/i2c-ast2600.c new file +3 -0

+		/* it should be repeat start read */
+		if (sts & AST2600_I2CS_SLAVE_MATCH)
+			i2c_slave_event(i2c_bus->slave,

I2C_SLAVE_WRITE_REQUESTED,

drivers/i2c/busses/i2c-ast2600.c

Quoted 3 lines

+&value);

drivers/i2c/busses/i2c-ast2600.c new file +2 -0

+
+		slave_rx_len =

AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +

Quoted 25 lines

drivers/i2c/busses/i2c-ast2600.c new file +25 -0

+						      AST2600_I2CS_DMA_LEN_STS));
+		for (i = 0; i < slave_rx_len; i++) {
+			i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED,
+					&i2c_bus->slave_dma_buf[i]);
+		}
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_REQUESTED,
+				&i2c_bus->slave_dma_buf[0]);
+		writel(0, i2c_bus->reg_base + AST2600_I2CS_DMA_LEN_STS);
+		writel(AST2600_I2CS_SET_TX_DMA_LEN(1),
+				i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_TX_DMA_EN;
+		break;
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_WAIT_TX_DMA:
+		/* First Start read */
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_REQUESTED,
+				&i2c_bus->slave_dma_buf[0]);
+		writel(AST2600_I2CS_SET_TX_DMA_LEN(1),
+				i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_TX_DMA_EN;
+		break;
+	case AST2600_I2CS_WAIT_TX_DMA:
+		/* it should be next start read */
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_PROCESSED,
+				&i2c_bus->slave_dma_buf[0]);
+		writel(0, i2c_bus->reg_base + AST2600_I2CS_DMA_LEN_STS);

drivers/i2c/busses/i2c-ast2600.c line 538

Quoted 10 lines

drivers/i2c/busses/i2c-ast2600.c new file +10 -0

+		writel(AST2600_I2CS_SET_TX_DMA_LEN(1),
+				i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_TX_DMA_EN;
+		break;
+
+	case AST2600_I2CS_TX_NAK | AST2600_I2CS_STOP:
+		/* it just tx complete */
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value);
+		writel(0, i2c_bus->reg_base + AST2600_I2CS_DMA_LEN_STS);
+

	writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE),

drivers/i2c/busses/i2c-ast2600.c

Quoted 6 lines

drivers/i2c/busses/i2c-ast2600.c new file +6 -0

+		       i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+		cmd = SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN;
+		break;
+	case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE:
+		cmd = 0;
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_REQUESTED,

&value);

Quoted 4 lines

drivers/i2c/busses/i2c-ast2600.c new file +4 -0

+		break;
+	case AST2600_I2CS_STOP:
+		cmd = 0;
+		i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value);

drivers/i2c/busses/i2c-ast2600.c

Quoted 10 lines

drivers/i2c/busses/i2c-ast2600.c new file +10 -0

+		break;
+	default:
+		dev_dbg(i2c_bus->dev, "todo slave isr case %x, sts %x\n", sts,
+			readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
+		break;
+	}
+
+	if (cmd)
+		writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+	writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base +

AST2600_I2CS_ISR);

drivers/i2c/busses/i2c-ast2600.c

Quoted 12 lines

drivers/i2c/busses/i2c-ast2600.c new file +12 -0

+	readl(i2c_bus->reg_base + AST2600_I2CS_ISR);
+	dev_dbg(i2c_bus->dev, "cmd %x\n", cmd); }
+
+static void ast2600_i2c_slave_packet_buff_irq(struct ast2600_i2c_bus
+*i2c_bus, u32 sts) {
+	int slave_rx_len = 0;
+	u32 cmd = 0;
+	u8 value;
+	int i = 0;
+
+	//due to master slave is common buffer, so need force the master
+stop not issue

Ditto... and everywhere else.

(...)

drivers/i2c/busses/i2c-ast2600.c line 1248

Quoted 7 lines

drivers/i2c/busses/i2c-ast2600.c new file +7 -0

+
+static int ast2600_i2c_master_irq(struct ast2600_i2c_bus *i2c_bus) {
+	u32 sts = readl(i2c_bus->reg_base + AST2600_I2CM_ISR);
+	u32 ier = readl(i2c_bus->reg_base + AST2600_I2CM_IER);
+	u32 ctrl = 0;
+
+	dev_dbg(i2c_bus->dev, "M sts %x\n", sts);

NAK. Don't drop debugs to interrupt handlers. This might flood the log and is unusable.

drivers/i2c/busses/i2c-ast2600.c

Quoted 5 lines

drivers/i2c/busses/i2c-ast2600.c new file +5 -0

+	if (!i2c_bus->alert_enable)
+		sts &= ~AST2600_I2CM_SMBUS_ALT;
+
+	if (AST2600_I2CM_BUS_RECOVER_FAIL & sts) {
+		dev_dbg(i2c_bus->dev, "M clear isr:

AST2600_I2CM_BUS_RECOVER_FAIL=