Update Colibri iMX8X Devicetrees

PATCH Applied Philippe Schenker 2 participants 25 messages Mar 14, 2023 – Mar 27, 2023

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Philippe Schenker

author

2023-03-14 10:25 UTC #0 lore raw

v2 cover Update Colibri iMX8X Devicetrees

From: Philippe Schenker <[email protected]>

This patch series does update the device-trees for Colibri iMX8X to the latest state of development.

Adds the Carrier Board device-trees for:

- Aster
- Iris
- Iris v2

It as well changes the pinmuxing bracket format together with some minor fixes.

Changes in v2:
- Add -B flag to format-patch for readability
- Change clock-16mhz-fixed to clock-16mhz
- Remove status="okay"
- Added Krzysztof's Acked-by, thanks!
- Drop patch
"arm64: dts: colibri-imx8x: Sort fec1 node alphabetically"
- Drop patch
"arm64: dts: colibri-imx8x: Sort properties"
- Adapted cover-letter

Philippe Schenker (23):
arm64: dts: colibri-imx8x: Prepare for qxp and dx variants
arm64: dts: colibri-imx8x: Update spdx license
arm64: dts: colibri-imx8x: Use new bracket format
arm64: dts: colibri-imx8x: Add atmel pinctrl groups
arm64: dts: colibri-imx8x: Add pinctrl group for csi_mclk
arm64: dts: colibri-imx8x: Split pinctrl_hog1
arm64: dts: colibri-imx8x: Correct pull on lcdif
arm64: dts: colibri-imx8x: Add separate pinctrl group for cs2
arm64: dts: colibri-imx8x: Add pinctrl group for hdmi hpd
arm64: dts: colibri-imx8x: Add SPI
arm64: dts: colibri-imx8x: Add gpio-line-names
arm64: dts: colibri-imx8x: Disable touchscreen by default
arm64: dts: colibri-imx8x: Add jpegenc/dec
arm64: dts: colibri-imx8x: Add colibri pwm b, c, d
arm64: dts: colibri-imx8x: eval: Add spi-to-can
arm64: dts: colibri-imx8x: Add no-1-8-v to sd-card
arm64: dts: colibri-imx8x: Set thermal thresholds
arm64: dts: colibri-imx8x: Move gpio-keys to som level
arm64: dts: colibri-imx8x: Add todo comments
dt-bindings: arm: fsl: Add colibri-imx8x carrier boards
arm64: dts: colibri-imx8x: Add aster carrier board
arm64: dts: colibri-imx8x: Add iris carrier board
arm64: dts: colibri-imx8x: Add iris v2 carrier board

 .../devicetree/bindings/arm/fsl.yaml          |   5 +-
 arch/arm64/boot/dts/freescale/Makefile        |   3 +
 .../dts/freescale/imx8qxp-colibri-aster.dts   |  16 +
 .../dts/freescale/imx8qxp-colibri-eval-v3.dts |   6 +-
 .../freescale/imx8qxp-colibri-eval-v3.dtsi    |  62 --
 .../dts/freescale/imx8qxp-colibri-iris-v2.dts |  16 +
 .../dts/freescale/imx8qxp-colibri-iris.dts    |  16 +
 .../boot/dts/freescale/imx8qxp-colibri.dtsi   | 610 +-------------
 .../dts/freescale/imx8x-colibri-aster.dtsi    |  44 +
 .../dts/freescale/imx8x-colibri-eval-v3.dtsi  |  90 ++
 .../dts/freescale/imx8x-colibri-iris-v2.dtsi  |  45 +
 .../dts/freescale/imx8x-colibri-iris.dtsi     | 115 +++
 .../boot/dts/freescale/imx8x-colibri.dtsi     | 776 ++++++++++++++++++
 13 files changed, 1140 insertions(+), 664 deletions(-)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts
 delete mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts
 rewrite arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi (99%)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #1 lore raw

PATCH v2 1/23 arm64: dts: colibri-imx8x: Prepare for qxp and dx variants

From: Philippe Schenker <[email protected]>

Toradex sells the Colibri iMX8X module in variants with the i.MX 8QXP and i.MX8DX SoC. Prepare for this by moving majority of stuff from imx8qxp-colibri.dtsi into imx8x-colibri.dtsi.

Remove DX from the model string.

This commit intends no functional change.

Signed-off-by Philippe Schenker <[email protected]>

---

Changes in v2:
- Add -B flag to format-patch for readability

 .../dts/freescale/imx8qxp-colibri-eval-v3.dts |   4 +-
 .../boot/dts/freescale/imx8qxp-colibri.dtsi   | 610 +-----------------
 ...val-v3.dtsi => imx8x-colibri-eval-v3.dtsi} |   0
 ...mx8qxp-colibri.dtsi => imx8x-colibri.dtsi} |   5 -
 4 files changed, 14 insertions(+), 605 deletions(-)
 rewrite arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi (99%)
 rename arch/arm64/boot/dts/freescale/{imx8qxp-colibri-eval-v3.dtsi => imx8x-colibri-eval-v3.dtsi} (100%)
 copy arch/arm64/boot/dts/freescale/{imx8qxp-colibri.dtsi => imx8x-colibri.dtsi} (99%)

arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts +2 -2

index 6b21a295c126..413a9e9d6c28 100644
@@ -6,10 +6,10 @@
 /dts-v1/;
 
 #include "imx8qxp-colibri.dtsi"
-#include "imx8qxp-colibri-eval-v3.dtsi"
+#include "imx8x-colibri-eval-v3.dtsi"
 
 / {
-	model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3";
+	model = "Toradex Colibri iMX8QXP on Colibri Evaluation Board V3";
 	compatible = "toradex,colibri-imx8x-eval-v3",
 		     "toradex,colibri-imx8x", "fsl,imx8qxp";
 };

arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi +12 ~~-598~~

610 lines not on this page · raw message

arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi renamed from arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi +0 -0

similarity index 100%
rename from arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
rename to arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi renamed from arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi +0 -5

similarity index 99%
copy from arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
copy to arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 89d70e030433..cb22bde19ea0 100644
@@ -3,12 +3,7 @@
  * Copyright 2019 Toradex
  */
 
-#include "imx8qxp.dtsi"
-
 / {
-	model = "Toradex Colibri iMX8QXP/DX Module";
-	compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";
-
 	chosen {
 		stdout-path = &lpuart3;
 	};

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #2 lore raw

PATCH v2 2/23 arm64: dts: colibri-imx8x: Update spdx license

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

GPL-2.0+ is deprecated, update it to GPL-2.0-or-later.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts | 2 +-
 arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi        | 2 +-
 arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi  | 2 +-
 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi          | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts +1 -1

index 413a9e9d6c28..fe4597a6f7e0 100644
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright 2019 Toradex
  */

arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi +1 -1

index 1ffc42f4a4b3..0f1aa31dd3e5 100644
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright 2019 Toradex
  */

arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi +1 -1

index 7c334b93db3b..dc0339b35a3c 100644
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright 2019 Toradex
  */

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +1 -1

index cb22bde19ea0..12056b77d22e 100644
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright 2019 Toradex
  */

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #3 lore raw

PATCH v2 3/23 arm64: dts: colibri-imx8x: Use new bracket format

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Use the new bracket format as described by Rob since this seems the format that we're heading in the future.

https://lore.kernel.org/all/CAL_JsqKqQdRZC08-BGJqTjzJZ8aWA41LHMbv0QyyVePVm0co7A@mail.gmail.com/

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 .../boot/dts/freescale/imx8x-colibri.dtsi     | 1093 ++++++++---------
 1 file changed, 500 insertions(+), 593 deletions(-)

rewrite arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi (68%)

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +500 ~~-593~~

dissimilarity index 68%
index 12056b77d22e..4e0d5762b76c 100644
@@ -1,593 +1,500 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright 2019 Toradex
- */
-
-/ {
-	chosen {
-		stdout-path = &lpuart3;
-	};
-
-	reg_module_3v3: regulator-module-3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "+V3.3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-};
-
-/* On-module I2C */
-&i2c0 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
-	status = "okay";
-
-	/* Touch controller */
-	touchscreen@2c {
-		compatible = "adi,ad7879-1";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ad7879_int>;
-		reg = <0x2c>;
-		interrupt-parent = <&lsio_gpio3>;
-		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
-		touchscreen-max-pressure = <4096>;
-		adi,resistance-plate-x = <120>;
-		adi,first-conversion-delay = /bits/ 8 <3>;
-		adi,acquisition-time = /bits/ 8 <1>;
-		adi,median-filter-size = /bits/ 8 <2>;
-		adi,averaging = /bits/ 8 <1>;
-		adi,conversion-interval = /bits/ 8 <255>;
-	};
-};
-
-/* Colibri I2C */
-&i2c1 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c1>;
-};
-
-/* Colibri UART_B */
-&lpuart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpuart0>;
-};
-
-/* Colibri UART_C */
-&lpuart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpuart2>;
-};
-
-/* Colibri UART_A */
-&lpuart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
-};
-
-/* Colibri FastEthernet */
-&fec1 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_fec1>;
-	pinctrl-1 = <&pinctrl_fec1_sleep>;
-	phy-mode = "rmii";
-	phy-handle = <&ethphy0>;
-	fsl,magic-packet;
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy0: ethernet-phy@2 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			max-speed = <100>;
-			reg = <2>;
-		};
-	};
-};
-
-/* On-module eMMC */
-&usdhc1 {
-	bus-width = <8>;
-	non-removable;
-	no-sd;
-	no-sdio;
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
-	status = "okay";
-};
-
-/* Colibri SD/MMC Card */
-&usdhc2 {
-	bus-width = <4>;
-	cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
-	vmmc-supply = <&reg_module_3v3>;
-	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
-	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
-	disable-wp;
-};
-
-&iomuxc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>;
-
-	/* On-module touch pen-down interrupt */
-	pinctrl_ad7879_int: ad7879intgrp {
-		fsl,pins = <
-			IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05	0x21
-		>;
-	};
-
-	/* Colibri Analogue Inputs */
-	pinctrl_adc0: adc0grp {
-		fsl,pins = <
-			IMX8QXP_ADC_IN0_ADMA_ADC_IN0			0x60		/* SODIMM   8 */
-			IMX8QXP_ADC_IN1_ADMA_ADC_IN1			0x60		/* SODIMM   6 */
-			IMX8QXP_ADC_IN4_ADMA_ADC_IN4			0x60		/* SODIMM   4 */
-			IMX8QXP_ADC_IN5_ADMA_ADC_IN5			0x60		/* SODIMM   2 */
-		>;
-	};
-
-	pinctrl_can_int: canintgrp {
-		fsl,pins = <
-			IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13		0x40		/* SODIMM  73 */
-		>;
-	};
-
-	pinctrl_csi_ctl: csictlgrp {
-		fsl,pins = <
-			IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14		0x20		/* SODIMM  77 */
-			IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15		0x20		/* SODIMM  89 */
-		>;
-	};
-
-	pinctrl_ext_io0: extio0grp {
-		fsl,pins = <
-			IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08	0x06000040	/* SODIMM 135 */
-		>;
-	};
-
-	/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
-	pinctrl_fec1: fec1grp {
-		fsl,pins = <
-			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020
-			IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
-			IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x61
-			IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT		0x06000061
-			IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x61
-			IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x61
-			IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x61
-			IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x61
-			IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x61
-			IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER		0x61
-		>;
-	};
-
-	pinctrl_fec1_sleep: fec1slpgrp {
-		fsl,pins = <
-			IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11		0x06000041
-			IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10		0x06000041
-			IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x41
-			IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29		0x41
-			IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31	0x41
-			IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x41
-			IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04	0x41
-			IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05	0x41
-			IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06	0x41
-			IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07	0x41
-		>;
-	};
-
-	/* Colibri optional CAN on UART_B RTS/CTS */
-	pinctrl_flexcan1: flexcan0grp {
-		fsl,pins = <
-			IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX		0x21		/* SODIMM  32 */
-			IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX		0x21		/* SODIMM  34 */
-		>;
-	};
-
-	/* Colibri optional CAN on PS2 */
-	pinctrl_flexcan2: flexcan1grp {
-		fsl,pins = <
-			IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX		0x21		/* SODIMM  55 */
-			IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX		0x21		/* SODIMM  63 */
-		>;
-	};
-
-	/* Colibri optional CAN on UART_A TXD/RXD */
-	pinctrl_flexcan3: flexcan2grp {
-		fsl,pins = <
-			IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX		0x21		/* SODIMM  35 */
-			IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX		0x21		/* SODIMM  33 */
-		>;
-	};
-
-	/* Colibri LCD Back-Light GPIO */
-	pinctrl_gpio_bl_on: gpioblongrp {
-		fsl,pins = <
-			IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12		0x60		/* SODIMM  71 */
-		>;
-	};
-
-	pinctrl_gpiokeys: gpiokeysgrp {
-		fsl,pins = <
-			IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10		0x06700041	/* SODIMM  45 */
-		>;
-	};
-
-	pinctrl_hog0: hog0grp {
-		fsl,pins = <
-			IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02	0x06000020	/* SODIMM  65 */
-			IMX8QXP_CSI_D07_CI_PI_D09			0x61		/* SODIMM  65 */
-			IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11		0x20		/* SODIMM  69 */
-			IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26		0x20		/* SODIMM  79 */
-			IMX8QXP_CSI_D02_CI_PI_D04			0x61		/* SODIMM  79 */
-			IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03		0x06000020	/* SODIMM  85 */
-			IMX8QXP_CSI_D06_CI_PI_D08			0x61		/* SODIMM  85 */
-			IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17		0x20		/* SODIMM  95 */
-			IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27		0x20		/* SODIMM  97 */
-			IMX8QXP_CSI_D03_CI_PI_D05			0x61		/* SODIMM  97 */
-			IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18		0x20		/* SODIMM  99 */
-			IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28		0x20		/* SODIMM 101 */
-			IMX8QXP_CSI_D00_CI_PI_D02			0x61		/* SODIMM 101 */
-			IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25		0x20		/* SODIMM 103 */
-			IMX8QXP_CSI_D01_CI_PI_D03			0x61		/* SODIMM 103 */
-			IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19		0x20		/* SODIMM 105 */
-			IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x20		/* SODIMM 107 */
-			IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05		0x20		/* SODIMM 127 */
-			IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06		0x20		/* SODIMM 131 */
-			IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04		0x20		/* SODIMM 133 */
-			IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00		0x20		/* SODIMM  96 */
-			IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21		0x20		/* SODIMM  98 */
-			IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31		0x20		/* SODIMM 100 */
-			IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22		0x20		/* SODIMM 102 */
-			IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23		0x20		/* SODIMM 104 */
-			IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24		0x20		/* SODIMM 106 */
-		>;
-	};
-
-	pinctrl_hog1: hog1grp {
-		fsl,pins = <
-			IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01		0x20		/* SODIMM  75 */
-			IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16		0x20		/* SODIMM  93 */
-		>;
-	};
-
-	/*
-	 * This pin is used in the SCFW as a UART. Using it from
-	 * Linux would require rewritting the SCFW board file.
-	 */
-	pinctrl_hog_scfw: hogscfwgrp {
-		fsl,pins = <
-			IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03		0x20		/* SODIMM 144 */
-		>;
-	};
-
-	/* On Module I2C */
-	pinctrl_i2c0: i2c0grp {
-		fsl,pins = <
-			IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL	0x06000021
-			IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA	0x06000021
-		>;
-	};
-
-	/* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
-	pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
-		fsl,pins = <
-			IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL	0xc6000020	/* SODIMM 140 */
-			IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA	0xc6000020	/* SODIMM 142 */
-		>;
-	};
-
-	/* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
-	pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
-		fsl,pins = <
-			IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL	0xc6000020	/* SODIMM 186 */
-			IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA	0xc6000020	/* SODIMM 188 */
-		>;
-	};
-
-	/* Colibri I2C */
-	pinctrl_i2c1: i2c1grp {
-		fsl,pins = <
-			IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x06000021	/* SODIMM 196 */
-			IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x06000021	/* SODIMM 194 */
-		>;
-	};
-
-	/* Colibri Parallel RGB LCD Interface */
-	pinctrl_lcdif: lcdifgrp {
-		fsl,pins = <
-			IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK		0x60		/* SODIMM  56 */
-			IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC		0x60		/* SODIMM  68 */
-			IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC		0x60		/* SODIMM  82 */
-			IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN			0x60		/* SODIMM  44 */
-			IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19		0x60		/* SODIMM  44 */
-			IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00		0x60		/* SODIMM  76 */
-			IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21		0x60		/* SODIMM  76 */
-			IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01		0x60		/* SODIMM  70 */
-			IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02		0x60		/* SODIMM  60 */
-			IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03		0x60		/* SODIMM  58 */
-			IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04		0x60		/* SODIMM  78 */
-			IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05		0x60		/* SODIMM  72 */
-			IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06		0x60		/* SODIMM  80 */
-			IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07		0x60		/* SODIMM  46 */
-			IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08		0x60		/* SODIMM  62 */
-			IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09		0x60		/* SODIMM  48 */
-			IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10		0x60		/* SODIMM  74 */
-			IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11		0x60		/* SODIMM  50 */
-			IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12		0x60		/* SODIMM  52 */
-			IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13			0x60		/* SODIMM  54 */
-			IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14			0x60		/* SODIMM  66 */
-			IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15			0x60		/* SODIMM  64 */
-			IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16			0x60		/* SODIMM  57 */
-			IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x60		/* SODIMM  57 */
-			IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17		0x60		/* SODIMM  61 */
-		>;
-	};
-
-	/* Colibri SPI */
-	pinctrl_lpspi2: lpspi2grp {
-		fsl,pins = <
-			IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00		0x21		/* SODIMM  86 */
-			IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO			0x06000040	/* SODIMM  92 */
-			IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI			0x06000040	/* SODIMM  90 */
-			IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK			0x06000040	/* SODIMM  88 */
-		>;
-	};
-
-	/* Colibri UART_B */
-	pinctrl_lpuart0: lpuart0grp {
-		fsl,pins = <
-			IMX8QXP_UART0_RX_ADMA_UART0_RX			0x06000020	/* SODIMM  36 */
-			IMX8QXP_UART0_TX_ADMA_UART0_TX			0x06000020	/* SODIMM  38 */
-			IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B		0x06000020	/* SODIMM  34 */
-			IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B		0x06000020	/* SODIMM  32 */
-		>;
-	};
-
-	/* Colibri UART_C */
-	pinctrl_lpuart2: lpuart2grp {
-		fsl,pins = <
-			IMX8QXP_UART2_RX_ADMA_UART2_RX			0x06000020	/* SODIMM  19 */
-			IMX8QXP_UART2_TX_ADMA_UART2_TX			0x06000020	/* SODIMM  21 */
-		>;
-	};
-
-	/* Colibri UART_A */
-	pinctrl_lpuart3: lpuart3grp {
-		fsl,pins = <
-			IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX		0x06000020	/* SODIMM  33 */
-			IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX		0x06000020	/* SODIMM  35 */
-		>;
-	};
-
-	/* Colibri UART_A Control */
-	pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
-		fsl,pins = <
-			IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00	0x20		/* SODIMM  23 */
-			IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29		0x20		/* SODIMM  25 */
-			IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30		0x20		/* SODIMM  27 */
-			IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03		0x20		/* SODIMM  29 */
-			IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22		0x20		/* SODIMM  31 */
-			IMX8QXP_CSI_EN_LSIO_GPIO3_IO02			0x20		/* SODIMM  37 */
-		>;
-	};
-
-	/* On module wifi module */
-	pinctrl_pcieb: pciebgrp {
-		fsl,pins = <
-			IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x04000061	/* SODIMM 178 */
-			IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02	0x04000061	/* SODIMM  94 */
-			IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00	0x60		/* SODIMM  81 */
-		>;
-	};
-
-	/* Colibri PWM_A */
-	pinctrl_pwm_a: pwmagrp {
-	/* both pins are connected together, reserve the unused CSI_D05 */
-		fsl,pins = <
-			IMX8QXP_CSI_D05_CI_PI_D07			0x61		/* SODIMM  59 */
-			IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT		0x60		/* SODIMM  59 */
-		>;
-	};
-
-	/* Colibri PWM_B */
-	pinctrl_pwm_b: pwmbgrp {
-		fsl,pins = <
-			IMX8QXP_UART1_TX_LSIO_PWM0_OUT			0x60		/* SODIMM  28 */
-		>;
-	};
-
-	/* Colibri PWM_C */
-	pinctrl_pwm_c: pwmcgrp {
-		fsl,pins = <
-			IMX8QXP_UART1_RX_LSIO_PWM1_OUT			0x60		/* SODIMM  30 */
-		>;
-	};
-
-	/* Colibri PWM_D */
-	pinctrl_pwm_d: pwmdgrp {
-	/* both pins are connected together, reserve the unused CSI_D04 */
-		fsl,pins = <
-			IMX8QXP_CSI_D04_CI_PI_D06			0x61		/* SODIMM  67 */
-			IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT		0x60		/* SODIMM  67 */
-		>;
-	};
-
-	/* On-module I2S */
-	pinctrl_sai0: sai0grp {
-		fsl,pins = <
-			IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD			0x06000040
-			IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD			0x06000040
-			IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC			0x06000040
-			IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS			0x06000040
-		>;
-	};
-
-	/* Colibri Audio Analogue Microphone GND */
-	pinctrl_sgtl5000: sgtl5000grp {
-		fsl,pins = <
-			/* MIC GND EN */
-			IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06	0x41
-		>;
-	};
-
-	/* On-module SGTL5000 clock */
-	pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
-		fsl,pins = <
-			IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0		0x21
-		>;
-	};
-
-	/* On-module USB interrupt */
-	pinctrl_usb3503a: usb3503agrp {
-		fsl,pins = <
-			IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04	0x61
-		>;
-	};
-
-	/* Colibri USB Client Cable Detect */
-	pinctrl_usbc_det: usbcdetgrp {
-		fsl,pins = <
-			IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000040	/* SODIMM 137 */
-		>;
-	};
-
-	/* USB Host Power Enable */
-	pinctrl_usbh1_reg: usbh1reggrp {
-		fsl,pins = <
-			IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03		0x06000040	/* SODIMM 129 */
-		>;
-	};
-
-	/* On-module eMMC */
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
-			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21
-			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
-			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
-			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
-			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
-			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
-			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
-			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
-			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
-			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
-			IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21
-		>;
-	};
-
-	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
-		fsl,pins = <
-			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
-			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21
-			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
-			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
-			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
-			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
-			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
-			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
-			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
-			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
-			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
-			IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21
-		>;
-	};
-
-	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
-		fsl,pins = <
-			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
-			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21
-			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
-			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
-			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
-			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
-			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
-			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
-			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
-			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
-			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
-			IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21
-		>;
-	};
-
-	/* Colibri SD/MMC Card Detect */
-	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
-		fsl,pins = <
-			IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x06000021	/* SODIMM  43 */
-		>;
-	};
-
-	pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
-		fsl,pins = <
-			IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x60		/* SODIMM  43 */
-		>;
-	};
-
-	/* Colibri SD/MMC Card */
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */
-			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */
-			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */
-			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */
-			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */
-			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */
-			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
-		>;
-	};
-
-	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
-		fsl,pins = <
-			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */
-			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */
-			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */
-			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */
-			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */
-			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */
-			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
-		>;
-	};
-
-	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
-		fsl,pins = <
-			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */
-			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */
-			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */
-			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */
-			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */
-			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */
-			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
-		>;
-	};
-
-	pinctrl_usdhc2_sleep: usdhc2slpgrp {
-		fsl,pins = <
-			IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23		0x60		/* SODIMM  47 */
-			IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24		0x60		/* SODIMM 190 */
-			IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25		0x60		/* SODIMM 192 */
-			IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26		0x60		/* SODIMM  49 */
-			IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27		0x60		/* SODIMM  51 */
-			IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28		0x60		/* SODIMM  53 */
-			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
-		>;
-	};
-
-	pinctrl_wifi: wifigrp {
-		fsl,pins = <
-			IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x20
-		>;
-	};
-};
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2019 Toradex
+ */
+
+/ {
+	chosen {
+		stdout-path = &lpuart3;
+	};
+
+	reg_module_3v3: regulator-module-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "+V3.3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+/* On-module I2C */
+&i2c0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
+	status = "okay";
+
+	/* Touch controller */
+	touchscreen@2c {
+		compatible = "adi,ad7879-1";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ad7879_int>;
+		reg = <0x2c>;
+		interrupt-parent = <&lsio_gpio3>;
+		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-max-pressure = <4096>;
+		adi,resistance-plate-x = <120>;
+		adi,first-conversion-delay = /bits/ 8 <3>;
+		adi,acquisition-time = /bits/ 8 <1>;
+		adi,median-filter-size = /bits/ 8 <2>;
+		adi,averaging = /bits/ 8 <1>;
+		adi,conversion-interval = /bits/ 8 <255>;
+	};
+};
+
+/* Colibri I2C */
+&i2c1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+};
+
+/* Colibri UART_B */
+&lpuart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+};
+
+/* Colibri UART_C */
+&lpuart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart2>;
+};
+
+/* Colibri UART_A */
+&lpuart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
+};
+
+/* Colibri FastEthernet */
+&fec1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_fec1>;
+	pinctrl-1 = <&pinctrl_fec1_sleep>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			max-speed = <100>;
+			reg = <2>;
+		};
+	};
+};
+
+/* On-module eMMC */
+&usdhc1 {
+	bus-width = <8>;
+	non-removable;
+	no-sd;
+	no-sdio;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	status = "okay";
+};
+
+/* Colibri SD/MMC Card */
+&usdhc2 {
+	bus-width = <4>;
+	cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_module_3v3>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+	disable-wp;
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>;
+
+	/* On-module touch pen-down interrupt */
+	pinctrl_ad7879_int: ad7879intgrp {
+		fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05	0x21>;
+	};
+
+	/* Colibri Analogue Inputs */
+	pinctrl_adc0: adc0grp {
+		fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0			0x60>,		/* SODIMM   8 */
+			   <IMX8QXP_ADC_IN1_ADMA_ADC_IN1			0x60>,		/* SODIMM   6 */
+			   <IMX8QXP_ADC_IN4_ADMA_ADC_IN4			0x60>,		/* SODIMM   4 */
+			   <IMX8QXP_ADC_IN5_ADMA_ADC_IN5			0x60>;		/* SODIMM   2 */
+	};
+
+	pinctrl_can_int: canintgrp {
+		fsl,pins = <IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13			0x40>;		/* SODIMM  73 */
+	};
+
+	pinctrl_csi_ctl: csictlgrp {
+		fsl,pins = <IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14		0x20>,		/* SODIMM  77 */
+			   <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15		0x20>;		/* SODIMM  89 */
+	};
+
+	pinctrl_ext_io0: extio0grp {
+		fsl,pins = <IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08		0x06000040>;	/* SODIMM 135 */
+	};
+
+	/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020>,
+			   <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020>,
+			   <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x61>,
+			   <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000061>,
+			   <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x61>,
+			   <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x61>,
+			   <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x61>,
+			   <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x61>,
+			   <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x61>,
+			   <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x61>;
+	};
+
+	pinctrl_fec1_sleep: fec1slpgrp {
+		fsl,pins = <IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11			0x06000041>,
+			   <IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10			0x06000041>,
+			   <IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30		0x41>,
+			   <IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29		0x41>,
+			   <IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31		0x41>,
+			   <IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00		0x41>,
+			   <IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04		0x41>,
+			   <IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05		0x41>,
+			   <IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06		0x41>,
+			   <IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07		0x41>;
+	};
+
+	/* Colibri optional CAN on UART_B RTS/CTS */
+	pinctrl_flexcan1: flexcan0grp {
+		fsl,pins = <IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX		0x21>,		/* SODIMM  32 */
+			   <IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX		0x21>;		/* SODIMM  34 */
+	};
+
+	/* Colibri optional CAN on PS2 */
+	pinctrl_flexcan2: flexcan1grp {
+		fsl,pins = <IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX		0x21>,		/* SODIMM  55 */
+			   <IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX		0x21>;		/* SODIMM  63 */
+	};
+
+	/* Colibri optional CAN on UART_A TXD/RXD */
+	pinctrl_flexcan3: flexcan2grp {
+		fsl,pins = <IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX		0x21>,		/* SODIMM  35 */
+			   <IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX		0x21>;		/* SODIMM  33 */
+	};
+
+	/* Colibri LCD Back-Light GPIO */
+	pinctrl_gpio_bl_on: gpioblongrp {
+		fsl,pins = <IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12		0x60>;		/* SODIMM  71 */
+	};
+
+	pinctrl_gpiokeys: gpiokeysgrp {
+		fsl,pins = <IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10		0x06700041>;	/* SODIMM  45 */
+	};
+
+	pinctrl_hog0: hog0grp {
+		fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02		0x06000020>,	/* SODIMM  65 */
+			   <IMX8QXP_CSI_D07_CI_PI_D09				0x61>,		/* SODIMM  65 */
+			   <IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11		0x20>,		/* SODIMM  69 */
+			   <IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26			0x20>,		/* SODIMM  79 */
+			   <IMX8QXP_CSI_D02_CI_PI_D04				0x61>,		/* SODIMM  79 */
+			   <IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03		0x06000020>,	/* SODIMM  85 */
+			   <IMX8QXP_CSI_D06_CI_PI_D08				0x61>,		/* SODIMM  85 */
+			   <IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17			0x20>,		/* SODIMM  95 */
+			   <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27			0x20>,		/* SODIMM  97 */
+			   <IMX8QXP_CSI_D03_CI_PI_D05				0x61>,		/* SODIMM  97 */
+			   <IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18		0x20>,		/* SODIMM  99 */
+			   <IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28			0x20>,		/* SODIMM 101 */
+			   <IMX8QXP_CSI_D00_CI_PI_D02				0x61>,		/* SODIMM 101 */
+			   <IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25			0x20>,		/* SODIMM 103 */
+			   <IMX8QXP_CSI_D01_CI_PI_D03				0x61>,		/* SODIMM 103 */
+			   <IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19		0x20>,		/* SODIMM 105 */
+			   <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x20>,		/* SODIMM 107 */
+			   <IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05			0x20>,		/* SODIMM 127 */
+			   <IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06			0x20>,		/* SODIMM 131 */
+			   <IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04			0x20>,		/* SODIMM 133 */
+			   <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00			0x20>,		/* SODIMM  96 */
+			   <IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21		0x20>,		/* SODIMM  98 */
+			   <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31			0x20>,		/* SODIMM 100 */
+			   <IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22			0x20>,		/* SODIMM 102 */
+			   <IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23		0x20>,		/* SODIMM 104 */
+			   <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24		0x20>;		/* SODIMM 106 */
+	};
+
+	pinctrl_hog1: hog1grp {
+		fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01			0x20>,		/* SODIMM  75 */
+			   <IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16			0x20>;		/* SODIMM  93 */
+	};
+
+	/*
+	 * This pin is used in the SCFW as a UART. Using it from
+	 * Linux would require rewritting the SCFW board file.
+	 */
+	pinctrl_hog_scfw: hogscfwgrp {
+		fsl,pins = <IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03		0x20>;		/* SODIMM 144 */
+	};
+
+	/* On Module I2C */
+	pinctrl_i2c0: i2c0grp {
+		fsl,pins = <IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL		0x06000021>,
+			   <IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA		0x06000021>;
+	};
+
+	/* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
+	pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
+		fsl,pins = <IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL	0xc6000020>,	/* SODIMM 140 */
+			   <IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA	0xc6000020>;	/* SODIMM 142 */
+	};
+
+	/* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
+	pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
+		fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL	0xc6000020>,	/* SODIMM 186 */
+			   <IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA	0xc6000020>;	/* SODIMM 188 */
+	};
+
+	/* Colibri I2C */
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL		0x06000021>,	/* SODIMM 196 */
+			   <IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA		0x06000021>;	/* SODIMM 194 */
+	};
+
+	/* Colibri Parallel RGB LCD Interface */
+	pinctrl_lcdif: lcdifgrp {
+		fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK			0x60>,		/* SODIMM  56 */
+			   <IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC			0x60>,		/* SODIMM  68 */
+			   <IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC			0x60>,		/* SODIMM  82 */
+			   <IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN			0x60>,		/* SODIMM  44 */
+			   <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19		0x60>,		/* SODIMM  44 */
+			   <IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00			0x60>,		/* SODIMM  76 */
+			   <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21			0x60>,		/* SODIMM  76 */
+			   <IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01			0x60>,		/* SODIMM  70 */
+			   <IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02			0x60>,		/* SODIMM  60 */
+			   <IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03			0x60>,		/* SODIMM  58 */
+			   <IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04			0x60>,		/* SODIMM  78 */
+			   <IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05			0x60>,		/* SODIMM  72 */
+			   <IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06		0x60>,		/* SODIMM  80 */
+			   <IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07		0x60>,		/* SODIMM  46 */
+			   <IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08		0x60>,		/* SODIMM  62 */
+			   <IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09		0x60>,		/* SODIMM  48 */
+			   <IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10			0x60>,		/* SODIMM  74 */
+			   <IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11			0x60>,		/* SODIMM  50 */
+			   <IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12		0x60>,		/* SODIMM  52 */
+			   <IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13			0x60>,		/* SODIMM  54 */
+			   <IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14			0x60>,		/* SODIMM  66 */
+			   <IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15			0x60>,		/* SODIMM  64 */
+			   <IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16			0x60>,		/* SODIMM  57 */
+			   <IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01		0x60>,		/* SODIMM  57 */
+			   <IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17			0x60>;		/* SODIMM  61 */
+	};
+
+	/* Colibri SPI */
+	pinctrl_lpspi2: lpspi2grp {
+		fsl,pins = <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00			0x21>,		/* SODIMM  86 */
+			   <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO			0x06000040>,	/* SODIMM  92 */
+			   <IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI			0x06000040>,	/* SODIMM  90 */
+			   <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK			0x06000040>;	/* SODIMM  88 */
+	};
+
+	/* Colibri UART_B */
+	pinctrl_lpuart0: lpuart0grp {
+		fsl,pins = <IMX8QXP_UART0_RX_ADMA_UART0_RX			0x06000020>,	/* SODIMM  36 */
+			   <IMX8QXP_UART0_TX_ADMA_UART0_TX			0x06000020>,	/* SODIMM  38 */
+			   <IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B		0x06000020>,	/* SODIMM  34 */
+			   <IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B		0x06000020>;	/* SODIMM  32 */
+	};
+
+	/* Colibri UART_C */
+	pinctrl_lpuart2: lpuart2grp {
+		fsl,pins = <IMX8QXP_UART2_RX_ADMA_UART2_RX			0x06000020>,	/* SODIMM  19 */
+			   <IMX8QXP_UART2_TX_ADMA_UART2_TX			0x06000020>;	/* SODIMM  21 */
+	};
+
+	/* Colibri UART_A */
+	pinctrl_lpuart3: lpuart3grp {
+		fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX			0x06000020>,	/* SODIMM  33 */
+			   <IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX			0x06000020>;	/* SODIMM  35 */
+	};
+
+	/* Colibri UART_A Control */
+	pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
+		fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00		0x20>,		/* SODIMM  23 */
+			   <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29			0x20>,		/* SODIMM  25 */
+			   <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30			0x20>,		/* SODIMM  27 */
+			   <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03			0x20>,		/* SODIMM  29 */
+			   <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22			0x20>,		/* SODIMM  31 */
+			   <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02			0x20>;		/* SODIMM  37 */
+	};
+
+	/* On module wifi module */
+	pinctrl_pcieb: pciebgrp {
+		fsl,pins = <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01		0x04000061>,	/* SODIMM 178 */
+			   <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000061>,	/* SODIMM  94 */
+			   <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x60>;		/* SODIMM  81 */
+	};
+
+	/* Colibri PWM_A */
+	pinctrl_pwm_a: pwmagrp {
+	/* both pins are connected together, reserve the unused CSI_D05 */
+		fsl,pins = <IMX8QXP_CSI_D05_CI_PI_D07				0x61>,		/* SODIMM  59 */
+			   <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT			0x60>;		/* SODIMM  59 */
+	};
+
+	/* Colibri PWM_B */
+	pinctrl_pwm_b: pwmbgrp {
+		fsl,pins = <IMX8QXP_UART1_TX_LSIO_PWM0_OUT			0x60>;		/* SODIMM  28 */
+	};
+
+	/* Colibri PWM_C */
+	pinctrl_pwm_c: pwmcgrp {
+		fsl,pins = <IMX8QXP_UART1_RX_LSIO_PWM1_OUT			0x60>;		/* SODIMM  30 */
+	};
+
+	/* Colibri PWM_D */
+	pinctrl_pwm_d: pwmdgrp {
+	/* both pins are connected together, reserve the unused CSI_D04 */
+		fsl,pins = <IMX8QXP_CSI_D04_CI_PI_D06				0x61>,		/* SODIMM  67 */
+			   <IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT			0x60>;		/* SODIMM  67 */
+	};
+
+	/* On-module I2S */
+	pinctrl_sai0: sai0grp {
+		fsl,pins = <IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD			0x06000040>,
+			   <IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD			0x06000040>,
+			   <IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC			0x06000040>,
+			   <IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS			0x06000040>;
+	};
+
+	/* Colibri Audio Analogue Microphone GND */
+	pinctrl_sgtl5000: sgtl5000grp {
+		fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06		0x41>;
+	};
+
+	/* On-module SGTL5000 clock */
+	pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
+		fsl,pins = <IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0			0x21>;
+	};
+
+	/* On-module USB interrupt */
+	pinctrl_usb3503a: usb3503agrp {
+		fsl,pins = <IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04		0x61>;
+	};
+
+	/* Colibri USB Client Cable Detect */
+	pinctrl_usbc_det: usbcdetgrp {
+		fsl,pins = <IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000040>;	/* SODIMM 137 */
+	};
+
+	/* USB Host Power Enable */
+	pinctrl_usbh1_reg: usbh1reggrp {
+		fsl,pins = <IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03			0x06000040>;	/* SODIMM 129 */
+	};
+
+	/* On-module eMMC */
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041>,
+			   <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x21>,
+			   <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21>,
+			   <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21>,
+			   <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21>,
+			   <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21>,
+			   <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21>,
+			   <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21>,
+			   <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21>,
+			   <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21>,
+			   <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41>,
+			   <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041>,
+			   <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x21>,
+			   <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21>,
+			   <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21>,
+			   <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21>,
+			   <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21>,
+			   <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21>,
+			   <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21>,
+			   <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21>,
+			   <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21>,
+			   <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41>,
+			   <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041>,
+			   <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x21>,
+			   <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21>,
+			   <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21>,
+			   <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21>,
+			   <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21>,
+			   <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21>,
+			   <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21>,
+			   <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21>,
+			   <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21>,
+			   <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41>,
+			   <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21>;
+	};
+
+	/* Colibri SD/MMC Card Detect */
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x06000021>;	/* SODIMM  43 */
+	};
+
+	pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
+		fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x60>;		/* SODIMM  43 */
+	};
+
+	/* Colibri SD/MMC Card */
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041>,	/* SODIMM  47 */
+			   <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x21>,		/* SODIMM 190 */
+			   <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21>,		/* SODIMM 192 */
+			   <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21>,		/* SODIMM  49 */
+			   <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21>,		/* SODIMM  51 */
+			   <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21>,		/* SODIMM  53 */
+			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041>,	/* SODIMM  47 */
+			   <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x21>,		/* SODIMM 190 */
+			   <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21>,		/* SODIMM 192 */
+			   <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21>,		/* SODIMM  49 */
+			   <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21>,		/* SODIMM  51 */
+			   <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21>,		/* SODIMM  53 */
+			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041>,	/* SODIMM  47 */
+			   <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x21>,		/* SODIMM 190 */
+			   <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21>,		/* SODIMM 192 */
+			   <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21>,		/* SODIMM  49 */
+			   <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21>,		/* SODIMM  51 */
+			   <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21>,		/* SODIMM  53 */
+			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21>;
+	};
+
+	pinctrl_usdhc2_sleep: usdhc2slpgrp {
+		fsl,pins = <IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23			0x60>,		/* SODIMM  47 */
+			   <IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24			0x60>,		/* SODIMM 190 */
+			   <IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25		0x60>,		/* SODIMM 192 */
+			   <IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26		0x60>,		/* SODIMM  49 */
+			   <IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27		0x60>,		/* SODIMM  51 */
+			   <IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28		0x60>,		/* SODIMM  53 */
+			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21>;
+	};
+
+	pinctrl_wifi: wifigrp {
+		fsl,pins = <IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x20>;
+	};
+};

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #4 lore raw

PATCH v2 4/23 arm64: dts: colibri-imx8x: Add atmel pinctrl groups

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Add pinctrl groups for enabling atmel touchscreen support. Remove the pads out of pinctrl_hog0 as they now can be enabled more specific using pinctrl_atmel_conn label.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 .../boot/dts/freescale/imx8x-colibri.dtsi     | 20 ++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +17 -3

index 4e0d5762b76c..5019439a3a75 100644
@@ -134,6 +134,22 @@ pinctrl_adc0: adc0grp {
 			   <IMX8QXP_ADC_IN5_ADMA_ADC_IN5			0x60>;		/* SODIMM   2 */
 	};
 
+	/* Atmel MXT touchsceen + Capacitive Touch Adapter */
+	/* NOTE: This pingroup conflicts with pingroups
+	 * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them
+	 * simultaneously.
+	 */
+	pinctrl_atmel_adap: atmeladaptergrp {
+		fsl,pins = <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22			0x21>,		/* SODIMM  30 */
+			   <IMX8QXP_UART1_TX_LSIO_GPIO0_IO21			0x4000021>;	/* SODIMM  28 */
+	};
+
+	/* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
+	pinctrl_atmel_conn: atmelconnectorgrp {
+		fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x4000021>,	/* SODIMM 107 */
+			   <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24		0x21>;		/* SODIMM 106 */
+	};
+
 	pinctrl_can_int: canintgrp {
 		fsl,pins = <IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13			0x40>;		/* SODIMM  73 */
 	};

@@ -218,7 +234,6 @@ pinctrl_hog0: hog0grp {
 			   <IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25			0x20>,		/* SODIMM 103 */
 			   <IMX8QXP_CSI_D01_CI_PI_D03				0x61>,		/* SODIMM 103 */
 			   <IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19		0x20>,		/* SODIMM 105 */
-			   <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x20>,		/* SODIMM 107 */
 			   <IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05			0x20>,		/* SODIMM 127 */
 			   <IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06			0x20>,		/* SODIMM 131 */
 			   <IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04			0x20>,		/* SODIMM 133 */

@@ -226,8 +241,7 @@ pinctrl_hog0: hog0grp {
 			   <IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21		0x20>,		/* SODIMM  98 */
 			   <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31			0x20>,		/* SODIMM 100 */
 			   <IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22			0x20>,		/* SODIMM 102 */
-			   <IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23		0x20>,		/* SODIMM 104 */
-			   <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24		0x20>;		/* SODIMM 106 */
+			   <IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23		0x20>;		/* SODIMM 104 */
 	};
 
 	pinctrl_hog1: hog1grp {

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #5 lore raw

PATCH v2 5/23 arm64: dts: colibri-imx8x: Add pinctrl group for csi_mclk

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Add missing pinctrl groups that can be used to enable the correct muxing if csi_mclk is needed on SODIMM 75.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +4 -0

index 5019439a3a75..a352246aa1f3 100644
@@ -159,6 +159,10 @@ pinctrl_csi_ctl: csictlgrp {
 			   <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15		0x20>;		/* SODIMM  89 */
 	};
 
+	pinctrl_csi_mclk: csimclkgrp {
+		fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK				0xC0000041>;	/* SODIMM  75 / X3-12 */
+	};
+
 	pinctrl_ext_io0: extio0grp {
 		fsl,pins = <IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08		0x06000040>;	/* SODIMM 135 */
 	};

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:27 UTC #6 lore raw

PATCH v2 6/23 arm64: dts: colibri-imx8x: Split pinctrl_hog1

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Split pinctrl_hog1 into a second group so CSI_MCLK can be muxed to a gpio on its own.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +6 -1

index a352246aa1f3..10dce84dc153 100644
@@ -119,7 +119,8 @@ &usdhc2 {
 
 &iomuxc {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>;
+	pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>,
+		    <&pinctrl_hog2>;
 
 	/* On-module touch pen-down interrupt */
 	pinctrl_ad7879_int: ad7879intgrp {

@@ -253,6 +254,10 @@ pinctrl_hog1: hog1grp {
 			   <IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16			0x20>;		/* SODIMM  93 */
 	};
 
+	pinctrl_hog2: hog2grp {
+		fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01			0x20>;		/* SODIMM  75 */
+	};
+
 	/*
 	 * This pin is used in the SCFW as a UART. Using it from
 	 * Linux would require rewritting the SCFW board file.

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #7 lore raw

PATCH v2 7/23 arm64: dts: colibri-imx8x: Correct pull on lcdif

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

The pads USDHC1_RESET_B and MCLK_IN1 need a pull-down instead of pull-disabled. Correct this.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +2 -2

index 10dce84dc153..26bf14cf5343 100644
@@ -295,8 +295,8 @@ pinctrl_lcdif: lcdifgrp {
 		fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK			0x60>,		/* SODIMM  56 */
 			   <IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC			0x60>,		/* SODIMM  68 */
 			   <IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC			0x60>,		/* SODIMM  82 */
-			   <IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN			0x60>,		/* SODIMM  44 */
-			   <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19		0x60>,		/* SODIMM  44 */
+			   <IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN			0x40>,		/* SODIMM  44 */
+			   <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19		0x40>,		/* SODIMM  44 */
 			   <IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00			0x60>,		/* SODIMM  76 */
 			   <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21			0x60>,		/* SODIMM  76 */
 			   <IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01			0x60>,		/* SODIMM  70 */

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #8 lore raw

PATCH v2 8/23 arm64: dts: colibri-imx8x: Add separate pinctrl group for cs2

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Add a separate pinctrl group for chip-select 2 for Colibri SPI. That way one is able to use it separately.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +6 -3

index 26bf14cf5343..1d4e127ffa7e 100644
@@ -120,7 +120,7 @@ &usdhc2 {
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>,
-		    <&pinctrl_hog2>;
+		    <&pinctrl_hog2>, <&pinctrl_lpspi2_cs2>;
 
 	/* On-module touch pen-down interrupt */
 	pinctrl_ad7879_int: ad7879intgrp {

@@ -223,8 +223,7 @@ pinctrl_gpiokeys: gpiokeysgrp {
 	};
 
 	pinctrl_hog0: hog0grp {
-		fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02		0x06000020>,	/* SODIMM  65 */
-			   <IMX8QXP_CSI_D07_CI_PI_D09				0x61>,		/* SODIMM  65 */
+		fsl,pins = <IMX8QXP_CSI_D07_CI_PI_D09				0x61>,		/* SODIMM  65 */
 			   <IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11		0x20>,		/* SODIMM  69 */
 			   <IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26			0x20>,		/* SODIMM  79 */
 			   <IMX8QXP_CSI_D02_CI_PI_D04				0x61>,		/* SODIMM  79 */

@@ -327,6 +326,10 @@ pinctrl_lpspi2: lpspi2grp {
 			   <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK			0x06000040>;	/* SODIMM  88 */
 	};
 
+	pinctrl_lpspi2_cs2: lpspi2cs2grp {
+		fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02		0x21>;		/* SODIMM  65 */
+	};
+
 	/* Colibri UART_B */
 	pinctrl_lpuart0: lpuart0grp {
 		fsl,pins = <IMX8QXP_UART0_RX_ADMA_UART0_RX			0x06000020>,	/* SODIMM  36 */

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #9 lore raw

PATCH v2 9/23 arm64: dts: colibri-imx8x: Add pinctrl group for hdmi hpd

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

The colibri imx8x contains a dedicated gpio meant for HDMI hot-plug-detect. Add a pinctrl group to make this usable.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +5 -0

index 1d4e127ffa7e..cd7de71c6d73 100644
@@ -218,6 +218,11 @@ pinctrl_gpio_bl_on: gpioblongrp {
 		fsl,pins = <IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12		0x60>;		/* SODIMM  71 */
 	};
 
+	/* HDMI Hot Plug Detect on FFC (X2) */
+	pinctrl_gpio_hpd: gpiohpdgrp {
+		fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31		0x20>;		/* SODIMM 138 */
+	};
+
 	pinctrl_gpiokeys: gpiokeysgrp {
 		fsl,pins = <IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10		0x06700041>;	/* SODIMM  45 */
 	};

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #10 lore raw

PATCH v2 10/23 arm64: dts: colibri-imx8x: Add SPI

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Add Colibri SPI to the board. lpspi2 is being exposed on the SoM edge. Add settings to the module-level but finally enable it on the eval-board dtsi.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi | 5 +++++
 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi         | 7 +++++++
 2 files changed, 12 insertions(+)

arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi +5 -0

index dc0339b35a3c..1d0bad085ad4 100644
@@ -36,6 +36,11 @@ rtc_i2c: rtc@68 {
 	};
 };
 
+/* Colibri SPI */
+&lpspi2 {
+	status = "okay";
+};
+
 /* Colibri UART_B */
 &lpuart0 {
 	status = "okay";

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +7 -0

index cd7de71c6d73..a2364845e976 100644
@@ -91,6 +91,13 @@ ethphy0: ethernet-phy@2 {
 	};
 };
 
+/* Colibri SPI */
+&lpspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpspi2>;
+	cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
+};
+
 /* On-module eMMC */
 &usdhc1 {
 	bus-width = <8>;

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #11 lore raw

PATCH v2 11/23 arm64: dts: colibri-imx8x: Add gpio-line-names

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

This commit adds gpio-line-names in line with other SoM from Toradex.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 .../boot/dts/freescale/imx8x-colibri.dtsi     | 152 ++++++++++++++++++
 1 file changed, 152 insertions(+)

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +152 -0

index a2364845e976..26f46fe56aa2 100644
@@ -98,6 +98,158 @@ &lpspi2 {
 	cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
 };
 
+&lsio_gpio0 {
+	gpio-line-names = "",
+			  "SODIMM_70",
+			  "SODIMM_60",
+			  "SODIMM_58",
+			  "SODIMM_78",
+			  "SODIMM_72",
+			  "SODIMM_80",
+			  "SODIMM_46",
+			  "SODIMM_62",
+			  "SODIMM_48",
+			  "SODIMM_74",
+			  "SODIMM_50",
+			  "SODIMM_52",
+			  "SODIMM_54",
+			  "SODIMM_66",
+			  "SODIMM_64",
+			  "SODIMM_68",
+			  "",
+			  "",
+			  "SODIMM_82",
+			  "SODIMM_56",
+			  "SODIMM_28",
+			  "SODIMM_30",
+			  "",
+			  "SODIMM_61",
+			  "SODIMM_103",
+			  "",
+			  "",
+			  "",
+			  "SODIMM_25",
+			  "SODIMM_27",
+			  "SODIMM_100";
+};
+
+&lsio_gpio1 {
+	gpio-line-names = "SODIMM_86",
+			  "SODIMM_92",
+			  "SODIMM_90",
+			  "SODIMM_88",
+			  "",
+			  "",
+			  "",
+			  "SODIMM_59",
+			  "",
+			  "SODIMM_6",
+			  "SODIMM_8",
+			  "",
+			  "",
+			  "SODIMM_2",
+			  "SODIMM_4",
+			  "SODIMM_34",
+			  "SODIMM_32",
+			  "SODIMM_63",
+			  "SODIMM_55",
+			  "SODIMM_33",
+			  "SODIMM_35",
+			  "SODIMM_36",
+			  "SODIMM_38",
+			  "SODIMM_21",
+			  "SODIMM_19",
+			  "SODIMM_140",
+			  "SODIMM_142",
+			  "SODIMM_196",
+			  "SODIMM_194",
+			  "SODIMM_186",
+			  "SODIMM_188",
+			  "SODIMM_138";
+};
+
+&lsio_gpio2 {
+	gpio-line-names = "SODIMM_23",
+			  "",
+			  "",
+			  "SODIMM_144";
+};
+
+&lsio_gpio3 {
+	gpio-line-names = "SODIMM_96",
+			  "SODIMM_75",
+			  "SODIMM_37",
+			  "SODIMM_29",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "SODIMM_43",
+			  "SODIMM_45",
+			  "SODIMM_69",
+			  "SODIMM_71",
+			  "SODIMM_73",
+			  "SODIMM_77",
+			  "SODIMM_89",
+			  "SODIMM_93",
+			  "SODIMM_95",
+			  "SODIMM_99",
+			  "SODIMM_105",
+			  "SODIMM_107",
+			  "SODIMM_98",
+			  "SODIMM_102",
+			  "SODIMM_104",
+			  "SODIMM_106";
+};
+
+&lsio_gpio4 {
+	gpio-line-names = "",
+			  "",
+			  "",
+			  "SODIMM_129",
+			  "SODIMM_133",
+			  "SODIMM_127",
+			  "SODIMM_131",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "SODIMM_44",
+			  "",
+			  "SODIMM_76",
+			  "SODIMM_31",
+			  "SODIMM_47",
+			  "SODIMM_190",
+			  "SODIMM_192",
+			  "SODIMM_49",
+			  "SODIMM_51",
+			  "SODIMM_53";
+};
+
+&lsio_gpio5 {
+	gpio-line-names = "",
+			  "SODIMM_57",
+			  "SODIMM_65",
+			  "SODIMM_85",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "SODIMM_135",
+			  "SODIMM_137",
+			  "UNUSABLE_SODIMM_180",
+			  "UNUSABLE_SODIMM_184";
+};
+
 /* On-module eMMC */
 &usdhc1 {
 	bus-width = <8>;

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #12 lore raw

PATCH v2 12/23 arm64: dts: colibri-imx8x: Disable touchscreen by default

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Do not enable the touchscreen. By default it is not used but should be kept to enable it from a file that includes imx8x-colibri.dtsi.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 1 +
 1 file changed, 1 insertion(+)

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +1 -0

index 26f46fe56aa2..2fd7f3483b3a 100644
@@ -40,6 +40,7 @@ touchscreen@2c {
 		adi,median-filter-size = /bits/ 8 <2>;
 		adi,averaging = /bits/ 8 <1>;
 		adi,conversion-interval = /bits/ 8 <255>;
+		status = "disabled";
 	};
 };

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #13 lore raw

PATCH v2 13/23 arm64: dts: colibri-imx8x: Add jpegenc/dec

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

jpeg encoder and decoder are available. Do enable them in the module level device-tree since those are self-contained.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +8 -0

index 2fd7f3483b3a..778f2f43a8c0 100644
@@ -53,6 +53,14 @@ &i2c1 {
 	pinctrl-0 = <&pinctrl_i2c1>;
 };
 
+&jpegdec {
+	status = "okay";
+};
+
+&jpegenc {
+	status = "okay";
+};
+
 /* Colibri UART_B */
 &lpuart0 {
 	pinctrl-names = "default";

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #14 lore raw

PATCH v2 14/23 arm64: dts: colibri-imx8x: Add colibri pwm b, c, d

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Add Colibri PWM_B, PWM_C, PWM_D to the module-level device-tree and set the status to ok on the eval-board.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 .../dts/freescale/imx8x-colibri-eval-v3.dtsi  | 15 +++++++++++++
 .../boot/dts/freescale/imx8x-colibri.dtsi     | 21 +++++++++++++++++++
 2 files changed, 36 insertions(+)

arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi +15 -0

index 1d0bad085ad4..68e34516961a 100644
@@ -51,6 +51,21 @@ &lpuart2 {
 	status = "okay";
 };
 
+/* Colibri PWM_B */
+&lsio_pwm0 {
+	status = "okay";
+};
+
+/* Colibri PWM_C */
+&lsio_pwm1 {
+	status = "okay";
+};
+
+/* Colibri PWM_D */
+&lsio_pwm2 {
+	status = "okay";
+};
+
 /* Colibri UART_A */
 &lpuart3 {
 	status = "okay";

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +21 -0

index 778f2f43a8c0..61033b79e44e 100644
@@ -259,6 +259,27 @@ &lsio_gpio5 {
 			  "UNUSABLE_SODIMM_184";
 };
 
+/* Colibri PWM_B */
+&lsio_pwm0 {
+	#pwm-cells = <3>;
+	pinctrl-0 = <&pinctrl_pwm_b>;
+	pinctrl-names = "default";
+};
+
+/* Colibri PWM_C */
+&lsio_pwm1 {
+	#pwm-cells = <3>;
+	pinctrl-0 = <&pinctrl_pwm_c>;
+	pinctrl-names = "default";
+};
+
+/* Colibri PWM_D */
+&lsio_pwm2 {
+	#pwm-cells = <3>;
+	pinctrl-0 = <&pinctrl_pwm_d>;
+	pinctrl-names = "default";
+};
+
 /* On-module eMMC */
 &usdhc1 {
 	bus-width = <8>;

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:27 UTC #15 lore raw

PATCH v2 15/23 arm64: dts: colibri-imx8x: eval: Add spi-to-can

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Add mcp2515 spi-to-can to &lpspi2.

Signed-off-by Philippe Schenker <[email protected]>

---

Changes in v2:
- Change clock-16mhz-fixed to clock-16mhz
- Remove status="okay"

 .../dts/freescale/imx8x-colibri-eval-v3.dtsi   | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi +18 -0

index 68e34516961a..14d479b50656 100644
@@ -11,6 +11,13 @@ aliases {
 		rtc1 = &rtc;
 	};
 
+	/* fixed crystal dedicated to mcp25xx */
+	clk16m: clock-16mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <16000000>;
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		pinctrl-names = "default";

@@ -39,6 +46,17 @@ rtc_i2c: rtc@68 {
 /* Colibri SPI */
 &lpspi2 {
 	status = "okay";
+
+	mcp2515: can@0 {
+		compatible = "microchip,mcp2515";
+		reg = <0>;
+		interrupt-parent = <&lsio_gpio3>;
+		interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-0 = <&pinctrl_can_int>;
+		pinctrl-names = "default";
+		clocks = <&clk16m>;
+		spi-max-frequency = <10000000>;
+	};
 };
 
 /* Colibri UART_B */

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:26 UTC #16 lore raw

PATCH v2 16/23 arm64: dts: colibri-imx8x: Add no-1-8-v to sd-card

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Many Colibri carrier boards are using 3.3V pull-up resistors on the SD-Card connector. Letting it switch to 1.8V is an invalid state.

Do prevent this from happening by keeping the signaling voltage at 3.3V.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 1 +
 1 file changed, 1 insertion(+)

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +1 -0

index 61033b79e44e..2e228c5b8109 100644
@@ -304,6 +304,7 @@ &usdhc2 {
 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
 	disable-wp;
+	no-1-8-v;
 };
 
 &iomuxc {

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #17 lore raw

PATCH v2 17/23 arm64: dts: colibri-imx8x: Set thermal thresholds

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Set critical/alert thermal thresholds for all relevant SOC temperature trips to the IT value (max T_junction 105 degree Celsius) in accordance with the IT grade of the SOM.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +12 -0

index 2e228c5b8109..1e41965e2d01 100644
@@ -16,6 +16,18 @@ reg_module_3v3: regulator-module-3v3 {
 	};
 };
 
+&cpu_alert0 {
+	hysteresis = <2000>;
+	temperature = <90000>;
+	type = "passive";
+};
+
+&cpu_crit0 {
+	hysteresis = <2000>;
+	temperature = <105000>;
+	type = "critical";
+};
+
 /* On-module I2C */
 &i2c0 {
 	#address-cells = <1>;

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:26 UTC #18 lore raw

PATCH v2 18/23 arm64: dts: colibri-imx8x: Move gpio-keys to som level

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

SODIMM_45 that is connected to "&lsio_gpio3 10" is defined in the Colibri standard to be a wakeup pin.
Move this to the SoM level device-tree and keep it disabled by default but do enable it again on the carrier-board.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 .../dts/freescale/imx8x-colibri-eval-v3.dtsi     | 16 +++-------------
 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 15 +++++++++++++++
 2 files changed, 18 insertions(+), 13 deletions(-)

arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi +3 ~~-13~~

index 14d479b50656..7264d784ae72 100644
@@ -17,20 +17,10 @@ clk16m: clock-16mhz {
 		#clock-cells = <0>;
 		clock-frequency = <16000000>;
 	};
+};
 
-	gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpiokeys>;
-
-		key-wakeup {
-			label = "Wake-Up";
-			gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
-			linux,code = <KEY_WAKEUP>;
-			debounce-interval = <10>;
-			wakeup-source;
-		};
-	};
+&colibri_gpio_keys {
+	status = "okay";
 };
 
 &i2c1 {

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +15 -0

index 1e41965e2d01..ff5ad88febc8 100644
@@ -8,6 +8,21 @@ chosen {
 		stdout-path = &lpuart3;
 	};
 
+	colibri_gpio_keys: gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpiokeys>;
+		status = "disabled";
+
+		key-wakeup {
+			debounce-interval = <10>;
+			gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
+			label = "Wake-Up";
+			linux,code = <KEY_WAKEUP>;
+			wakeup-source;
+		};
+	};
+
 	reg_module_3v3: regulator-module-3v3 {
 		compatible = "regulator-fixed";
 		regulator-name = "+V3.3";

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:26 UTC #19 lore raw

PATCH v2 19/23 arm64: dts: colibri-imx8x: Add todo comments

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Highlight what is still missing.

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 .../boot/dts/freescale/imx8x-colibri.dtsi     | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +28 -0

index ff5ad88febc8..7cad79102e1a 100644
@@ -31,6 +31,10 @@ reg_module_3v3: regulator-module-3v3 {
 	};
 };
 
+/* TODO Analogue Inputs */
+
+/* TODO Cooling maps for DX */
+
 &cpu_alert0 {
 	hysteresis = <2000>;
 	temperature = <90000>;

@@ -43,6 +47,10 @@ &cpu_crit0 {
 	type = "critical";
 };
 
+/* TODO flexcan1 - 3 */
+
+/* TODO GPU */
+
 /* On-module I2C */
 &i2c0 {
 	#address-cells = <1>;

@@ -71,6 +79,10 @@ touchscreen@2c {
 	};
 };
 
+/* TODO i2c lvds0 accessible on FFC (X2) */
+
+/* TODO i2c lvds1 accessible on FFC (X3) */
+
 /* Colibri I2C */
 &i2c1 {
 	#address-cells = <1>;

@@ -88,6 +100,8 @@ &jpegenc {
 	status = "okay";
 };
 
+/* TODO Parallel RRB */
+
 /* Colibri UART_B */
 &lpuart0 {
 	pinctrl-names = "default";

@@ -307,6 +321,14 @@ &lsio_pwm2 {
 	pinctrl-names = "default";
 };
 
+/* TODO MIPI CSI */
+
+/* TODO MIPI DSI with DSI-to-HDMI bridge lt8912 */
+
+/* TODO on-module PCIe for Wi-Fi */
+
+/* TODO On-module i2s / Audio */
+
 /* On-module eMMC */
 &usdhc1 {
 	bus-width = <8>;

@@ -334,6 +356,12 @@ &usdhc2 {
 	no-1-8-v;
 };
 
+/* TODO USB Client/Host */
+
+/* TODO USB Host */
+
+/* TODO VPU Encoder/Decoder */
+
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>,

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:25 UTC #20 lore raw

PATCH v2 20/23 dt-bindings: arm: fsl: Add colibri-imx8x carrier boards

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Prepare the dt-bindings for the new colibri-imx8x carrier-boards Aster and Iris.

The Toradex SoM standard is called Colibri, fix the typo.

Signed-off-by Philippe Schenker <[email protected]>

Acked-by Krzysztof Kozlowski <[email protected]>

---

Changes in v2:
- Added Krzysztof's Acked-by, thanks!

 Documentation/devicetree/bindings/arm/fsl.yaml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/arm/fsl.yaml +4 -1

index 2c90455722f0..750b8b949219 100644
@@ -1154,10 +1154,13 @@ properties:
               - fsl,imx8dxl-evk           # i.MX8DXL EVK Board
           - const: fsl,imx8dxl
 
-      - description: i.MX8QXP Boards with Toradex Coilbri iMX8X Modules
+      - description: i.MX8QXP Boards with Toradex Colibri iMX8X Modules
         items:
           - enum:
+              - toradex,colibri-imx8x-aster   # Colibri iMX8X Module on Aster Board
               - toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3
+              - toradex,colibri-imx8x-iris    # Colibri iMX8X Module on Iris Board
+              - toradex,colibri-imx8x-iris-v2 # Colibri iMX8X Module on Iris Board V2
           - const: toradex,colibri-imx8x
           - const: fsl,imx8qxp

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:26 UTC #21 lore raw

PATCH v2 21/23 arm64: dts: colibri-imx8x: Add aster carrier board

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Add the Toradex Aster Carrier Board for Colibri iMX8X, small form-factor with header compatible with Arduino Uno and Raspberry Pi (RPi) maker boards.

Additional details available at:
https://www.toradex.com/products/carrier-boards/aster-carrier-board

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 arch/arm64/boot/dts/freescale/Makefile        |  1 +
 .../dts/freescale/imx8qxp-colibri-aster.dts   | 16 +++++++
 .../dts/freescale/imx8x-colibri-aster.dtsi    | 44 +++++++++++++++++++
 3 files changed, 61 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi

arch/arm64/boot/dts/freescale/Makefile +1 -0

index 836dcc501e6f..9f49e47589ab 100644
@@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb

arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts new file +16 -0

new file mode 100644
index 000000000000..966ecfb2a17e
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2021 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8qxp-colibri.dtsi"
+#include "imx8x-colibri-aster.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX8QXP on Aster Board";
+	compatible = "toradex,colibri-imx8x-aster",
+		     "toradex,colibri-imx8x",
+		     "fsl,imx8qxp";
+};

arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi new file +44 -0

44 lines not on this page · raw message

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:26 UTC #22 lore raw

PATCH v2 22/23 arm64: dts: colibri-imx8x: Add iris carrier board

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Add the Toradex Iris Carrier Board for Colibri iMX8X, small form-factor production ready board.

Additional details available at:
https://www.toradex.com/products/carrier-boards/iris-carrier-board

Signed-off-by Philippe Schenker <[email protected]>

---

(no changes since v1)

 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../dts/freescale/imx8qxp-colibri-iris.dts    |  16 +++
 .../dts/freescale/imx8x-colibri-iris.dtsi     | 115 ++++++++++++++++++
 3 files changed, 132 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi

arch/arm64/boot/dts/freescale/Makefile +1 -0

index 9f49e47589ab..48bb0fe4a616 100644
@@ -131,6 +131,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb

arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts new file +16 -0

new file mode 100644
index 000000000000..fed75b5d4a1c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2021 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8qxp-colibri.dtsi"
+#include "imx8x-colibri-iris.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX8QXP on Colibri Iris Board";
+	compatible = "toradex,colibri-imx8x-iris",
+		     "toradex,colibri-imx8x",
+		     "fsl,imx8qxp";
+};

arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi new file +115 -0

115 lines not on this page · raw message

Signature · 1 line

2.39.2

Philippe Schenker

author

2023-03-14 10:27 UTC #23 lore raw

PATCH v2 23/23 arm64: dts: colibri-imx8x: Add iris v2 carrier board

In reply to Philippe Schenker

From: Philippe Schenker <[email protected]>

Add the Toradex Iris V2 Carrier Board for Colibri iMX8X, small form-factor production ready board.

Additional details available at:
https://www.toradex.com/products/carrier-boards/iris-carrier-board

Signed-off-by Philippe Schenker <[email protected]>

---

Changes in v2:
- Drop patch
"arm64: dts: colibri-imx8x: Sort fec1 node alphabetically"
- Drop patch
"arm64: dts: colibri-imx8x: Sort properties"
- Adapted cover-letter

 arch/arm64/boot/dts/freescale/Makefile        |  1 +
 .../dts/freescale/imx8qxp-colibri-iris-v2.dts | 16 +++++++
 .../dts/freescale/imx8x-colibri-iris-v2.dtsi  | 45 +++++++++++++++++++
 3 files changed, 62 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi

arch/arm64/boot/dts/freescale/Makefile +1 -0

index 48bb0fe4a616..2eb746f6a2c2 100644
@@ -132,6 +132,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb

arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts new file +16 -0

new file mode 100644
index 000000000000..cca33213fa9b
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2021 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8qxp-colibri.dtsi"
+#include "imx8x-colibri-iris-v2.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX8QXP on Colibri Iris V2 Board";
+	compatible = "toradex,colibri-imx8x-iris-v2",
+		     "toradex,colibri-imx8x",
+		     "fsl,imx8qxp";
+};

arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi new file +45 -0

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Signature · 1 line

2.39.2

Shawn Guo

Applied

2023-03-27 02:11 UTC #24 lore raw

In reply to Philippe Schenker

Quoted 41 lines · Philippe Schenker

From: Philippe Schenker <[email protected]>
This patch series does update the device-trees for Colibri iMX8X to the latest state of development.
Adds the Carrier Board device-trees for:
- Aster
- Iris
- Iris v2
It as well changes the pinmuxing bracket format together with some minor fixes.
Changes in v2:
- Add -B flag to format-patch for readability
- Change clock-16mhz-fixed to clock-16mhz
- Remove status="okay"
- Added Krzysztof's Acked-by, thanks!
- Drop patch
"arm64: dts: colibri-imx8x: Sort fec1 node alphabetically"
- Drop patch
"arm64: dts: colibri-imx8x: Sort properties"
- Adapted cover-letter
Philippe Schenker (23):
arm64: dts: colibri-imx8x: Prepare for qxp and dx variants
arm64: dts: colibri-imx8x: Update spdx license
arm64: dts: colibri-imx8x: Use new bracket format
arm64: dts: colibri-imx8x: Add atmel pinctrl groups
arm64: dts: colibri-imx8x: Add pinctrl group for csi_mclk
arm64: dts: colibri-imx8x: Split pinctrl_hog1
arm64: dts: colibri-imx8x: Correct pull on lcdif
arm64: dts: colibri-imx8x: Add separate pinctrl group for cs2
arm64: dts: colibri-imx8x: Add pinctrl group for hdmi hpd
arm64: dts: colibri-imx8x: Add SPI
arm64: dts: colibri-imx8x: Add gpio-line-names
arm64: dts: colibri-imx8x: Disable touchscreen by default
arm64: dts: colibri-imx8x: Add jpegenc/dec
arm64: dts: colibri-imx8x: Add colibri pwm b, c, d
arm64: dts: colibri-imx8x: eval: Add spi-to-can

Quoted 8 lines

arm64: dts: colibri-imx8x: Add no-1-8-v to sd-card
arm64: dts: colibri-imx8x: Set thermal thresholds
arm64: dts: colibri-imx8x: Move gpio-keys to som level
arm64: dts: colibri-imx8x: Add todo comments
dt-bindings: arm: fsl: Add colibri-imx8x carrier boards
arm64: dts: colibri-imx8x: Add aster carrier board
arm64: dts: colibri-imx8x: Add iris carrier board
arm64: dts: colibri-imx8x: Add iris v2 carrier board

Applied all, thanks!