FAILED: patch "[PATCH] pinctrl: amd: Disable and mask interrupts on resume" failed to apply to 4.14-stable tree
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[email protected]
maintainerThe patch below does not apply to the 4.14-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-4.14.y
git checkout FETCH_HEAD
git cherry-pick -x b26cd9325be4c1fcd331b77f10acb627c560d4d7
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2023040315-prodigal-chief-ace2@gregkh' --subject-prefix 'PATCH 4.14.y' HEAD^..
Possible dependencies:
b26cd9325be4 ("pinctrl: amd: Disable and mask interrupts on resume") 4e5a04be88fe ("pinctrl: amd: disable and mask interrupts on probe") e81376ebbafc ("pinctrl: amd: Use irqchip template") 279ffafaf39d ("pinctrl: Added IRQF_SHARED flag for amd-pinctrl driver")
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From b26cd9325be4c1fcd331b77f10acb627c560d4d7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Kornel=20Dul=C4=99ba?= <[email protected]>
Date: Mon, 20 Mar 2023 09:32:59 +0000
Subject: [PATCH] pinctrl: amd: Disable and mask interrupts on resume
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This fixes a similar problem to the one observed in:
commit 4e5a04be88fe ("pinctrl: amd: disable and mask interrupts on probe").
On some systems, during suspend/resume cycle firmware leaves an interrupt enabled on a pin that is not used by the kernel. This confuses the AMD pinctrl driver and causes spurious interrupts.
The driver already has logic to detect if a pin is used by the kernel. Leverage it to re-initialize interrupt fields of a pin only if it's not used by us.
drivers/pinctrl/pinctrl-amd.c +20 -16
@@ -872,32 +872,34 @@ static const struct pinconf_ops amd_pinconf_ops = { .pin_config_group_set = amd_pinconf_group_set, }; -static void amd_gpio_irq_init (struct amd_gpio *gpio_dev) +static void amd_gpio_irq_init_pin (struct amd_gpio *gpio_dev,int pin) { -struct pinctrl_desc *desc = gpio_dev->pctrl->desc; +const struct pin_desc *pd;unsigned long flags;u32 pin_reg, mask; -int i; mask =BIT (WAKE_CNTRL_OFF_S0I3 ) |BIT (WAKE_CNTRL_OFF_S3 ) |BIT (INTERRUPT_MASK_OFF ) |BIT (INTERRUPT_ENABLE_OFF ) |BIT (WAKE_CNTRL_OFF_S4 ); -for (i =0 ; i < desc->npins; i++) { -int pin = desc->pins[i].number; -const struct pin_desc *pd =pin_desc_get (gpio_dev->pctrl, pin); - -if (!pd) -continue ; + pd =pin_desc_get (gpio_dev->pctrl, pin); +if (!pd) +return ; -raw_spin_lock_irqsave (&gpio_dev->lock, flags); +raw_spin_lock_irqsave (&gpio_dev->lock, flags); + pin_reg =readl (gpio_dev->base + pin *4 ); + pin_reg &= ~mask; +writel (pin_reg, gpio_dev->base + pin *4 ); +raw_spin_unlock_irqrestore (&gpio_dev->lock, flags); +} - pin_reg =readl (gpio_dev->base + i *4 ); - pin_reg &= ~mask; -writel (pin_reg, gpio_dev->base + i *4 ); +static void amd_gpio_irq_init (struct amd_gpio *gpio_dev) +{ +struct pinctrl_desc *desc = gpio_dev->pctrl->desc; +int i; -raw_spin_unlock_irqrestore (&gpio_dev->lock, flags); - } +for (i =0 ; i < desc->npins; i++) +amd_gpio_irq_init_pin (gpio_dev, i); }#ifdef CONFIG_PM_SLEEP
@@ -950,8 +952,10 @@ static int amd_gpio_resume(struct device *dev)for (i =0 ; i < desc->npins; i++) {int pin = desc->pins[i].number; -if (!amd_gpio_should_save (gpio_dev, pin)) +if (!amd_gpio_should_save (gpio_dev, pin)) { +amd_gpio_irq_init_pin (gpio_dev, pin);continue ; + }raw_spin_lock_irqsave (&gpio_dev->lock, flags); gpio_dev->saved_regs[i] |=readl (gpio_dev->base + pin *4 ) &PIN_IRQ_PENDING ;