net/ice/base: share code update

index 23b6c608be..fd9c6d5c14 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_acl.h"

index b5f2ec04a4..ac703be0a1 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_ACL_H_

index 3a912f2aa0..2223a8313b 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_acl.h"

index 5a817982b4..65cba9ab37 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_ADMINQ_CMD_H_

index dca502ab25..6487cdc210 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_ALLOC_H_

index c4ae2b9c8e..5384e99415 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_BITOPS_H_

index 5cc0d12251..fbe106df60 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index 292444c919..2fb2c8421e 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_BST_TCAM_H_

index 6b9a359c5b..c44bfc1846 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_CGU_REGS_H_

index 1a02aad869..fa30c50ca1 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index 58260afb93..e1febfb0c4 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_COMMON_H_

index 8971a140ef..c34407b48c 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index 45fe70450e..986604ec3c 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_CONTROLQ_H_

index 0e604df541..2a308b02bf 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index d010c539a6..bae033a460 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_DCB_H_

index d1cae48047..93ff2608d4 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_ddp.h"

index 53bbbe2a5a..4896e85b91 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_DDP_H_

index 6e886f6aac..210ce6263b 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_DEFS_H_

index 13a4b16402..f80789ebc5 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_DEVIDS_H_

index 85ca29bae5..3ed2a63b68 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index f338da38c2..81ba6008e4 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_FDIR_H_

index b6bc0062a3..f9266447d9 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index 9ba337e1fa..422d09becc 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_FLEX_PIPE_H_

index 7b8f6f9049..c83479d6fa 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_FLEX_TYPE_H_

index f320958bd3..97f62e6cc4 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index 8cd375f89f..c194a4f462 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_FLG_RD_H_

index 3483a5ed4f..5254ee27ed 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index dba71aab74..57e8e1f1df 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_FLOW_H_

index 6dc77bf7cb..4610cec6a7 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 /* Machine generated file. Do not edit. */

index 277311fd20..f193aaf836 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index 06d3d5a96d..0328830b94 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_IMEM_H_

index be6d88f0ca..d816df0ff6 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_LAN_TX_RX_H_

index b75d68c010..1e990c9aa0 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index dad4faf4d4..440932ae30 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_METAINIT_H_

index cafe51544d..9de4527b58 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index 9401647ef0..161dd724cb 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_MK_GRP_H_

index 6550dda557..cb45cb8134 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index a8cda452db..c3e61a301f 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_NVM_H_

index a1b906d369..79c97f7903 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index b4c5e7b14d..0f64584898 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_PARSER_H_

index 215e11abd2..68c0f5d7fb 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index c1e1af0059..de851643b4 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_PARSER_RT_H_

index a33d6bf11c..9949b985ee 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_PARSER_UTIL_H_

index f06a3581a0..e6324945fb 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index ac0863afb0..0412ac5ae2 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_PG_CAM_H_

index a9ed9e051f..94f4df0aaa 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index 762d32464b..dc6d8a32a4 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_PROTO_GRP_H_

index d17ab54bd3..eeaf044059 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_PROTOCOL_TYPE_H_

index ddf6242d8e..546bf8ba91 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_PTP_CONSTS_H_

index a0b8af1b94..548ef5e820 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_type.h"

index 09c236e7e0..3667c9882d 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_PTP_HW_H_

index 4cd8396167..6814095dbd 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index 3efe294dda..66427c6866 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_PTYPE_MK_H_

index a215303a56..4da16caf70 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_SBQ_CMD_H_

index a526c8f32c..83cd152388 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_sched.h"

index 3724ef33a8..a71619ebf0 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_SCHED_H_

index f52121c3a3..1965347a8b 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_STATUS_H_

index e4eed66406..cd6237136e 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index 949c94c0c3..7a12619459 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_SWITCH_H_

index e70926acd1..a2df0c4367 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_TMATCH_H_

index bfec317b57..da813c8307 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_TYPE_H_

index 74d414b3b8..7ee00df124 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index 5e3f454a25..d2380eb94b 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_VLAN_MODE_H_

index 59472a08d4..b8240946b4 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #include "ice_common.h"

index f870f18ed6..0cce33142a 100644
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
+ * Copyright(c) 2001-2023 Intel Corporation
  */
 
 #ifndef _ICE_XLT_KB_H_

index 65cba9ab37..69e528a8c9 100644
@@ -813,12 +813,30 @@ struct ice_aqc_sw_rules {
 	__le32 addr_low;
 };
 
+/* Add switch rule response:
+ * Content of return buffer is same as the input buffer. The status field and
+ * LUT index are updated as part of the response
+ */
+struct ice_aqc_sw_rules_elem_hdr {
+	__le16 type; /* Switch rule type, one of T_... */
+#define ICE_AQC_SW_RULES_T_LKUP_RX		0x0
+#define ICE_AQC_SW_RULES_T_LKUP_TX		0x1
+#define ICE_AQC_SW_RULES_T_LG_ACT		0x2
+#define ICE_AQC_SW_RULES_T_VSI_LIST_SET		0x3
+#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR	0x4
+#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET	0x5
+#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR	0x6
+	__le16 status;
+};
+
 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
  * This structures describes the lookup rules and associated actions. "index"
  * is returned as part of a response to a successful Add command, and can be
  * used to identify the rule for Update/Get/Remove commands.
  */
 struct ice_sw_rule_lkup_rx_tx {
+	struct ice_aqc_sw_rules_elem_hdr hdr;
+
 	__le16 recipe_id;
 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD		10
 	/* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */

@@ -866,6 +884,8 @@ struct ice_sw_rule_lkup_rx_tx {
 #define ICE_SINGLE_ACT_PTR		0x2
 #define ICE_SINGLE_ACT_PTR_VAL_S	4
 #define ICE_SINGLE_ACT_PTR_VAL_M	(0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
+	/* Bit 17 should be set if pointed action includes a FWD cmd */
+#define ICE_SINGLE_ACT_PTR_HAS_FWD	BIT(17)
 	/* Bit 18 should be set to 1 */
 #define ICE_SINGLE_ACT_PTR_BIT		BIT(18)
 

@@ -895,14 +915,17 @@ struct ice_sw_rule_lkup_rx_tx {
 	 * lookup-type
 	 */
 	__le16 hdr_len;
-	u8 hdr[STRUCT_HACK_VAR_LEN];
+	u8 hdr_data[STRUCT_HACK_VAR_LEN];
 };
 
+#pragma pack(1)
 /* Add/Update/Remove large action command/response entry
  * "index" is returned as part of a response to a successful Add command, and
  * can be used to identify the action for Update/Get/Remove commands.
  */
 struct ice_sw_rule_lg_act {
+	struct ice_aqc_sw_rules_elem_hdr hdr;
+
 	__le16 index; /* Index in large action table */
 	__le16 size;
 	/* Max number of large actions */

@@ -957,16 +980,21 @@ struct ice_sw_rule_lg_act {
 #define ICE_LG_ACT_STAT_COUNT_M		(0x7F << ICE_LG_ACT_STAT_COUNT_S)
 	__le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */
 };
+#pragma pack()
 
+#pragma pack(1)
 /* Add/Update/Remove VSI list command/response entry
  * "index" is returned as part of a response to a successful Add command, and
  * can be used to identify the VSI list for Update/Get/Remove commands.
  */
 struct ice_sw_rule_vsi_list {
+	struct ice_aqc_sw_rules_elem_hdr hdr;
+
 	__le16 index; /* Index of VSI/Prune list */
 	__le16 number_vsi;
 	__le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */
 };
+#pragma pack()
 
 #pragma pack(1)
 /* Query VSI list command/response entry */

@@ -976,31 +1004,6 @@ struct ice_sw_rule_vsi_list_query {
 };
 #pragma pack()
 
-#pragma pack(1)
-/* Add switch rule response:
- * Content of return buffer is same as the input buffer. The status field and
- * LUT index are updated as part of the response
- */
-struct ice_aqc_sw_rules_elem {
-	__le16 type; /* Switch rule type, one of T_... */
-#define ICE_AQC_SW_RULES_T_LKUP_RX		0x0
-#define ICE_AQC_SW_RULES_T_LKUP_TX		0x1
-#define ICE_AQC_SW_RULES_T_LG_ACT		0x2
-#define ICE_AQC_SW_RULES_T_VSI_LIST_SET		0x3
-#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR	0x4
-#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET	0x5
-#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR	0x6
-	__le16 status;
-	union {
-		struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
-		struct ice_sw_rule_lg_act lg_act;
-		struct ice_sw_rule_vsi_list vsi_list;
-		struct ice_sw_rule_vsi_list_query vsi_list_query;
-	} pdata;
-};
-
-#pragma pack()
-
 /* PFC Ignore (direct 0x0301)
  * The command and response use the same descriptor structure
  */

@@ -2771,7 +2774,7 @@ struct ice_aqc_move_txqs_data {
 };
 
 /* Download Package (indirect 0x0C40) */
-/* Also used for Update Package (indirect 0x0C42 and 0x0C41) */
+/* Also used for Update Package (indirect 0x0C41 and 0x0C42) */
 struct ice_aqc_download_pkg {
 	u8 flags;
 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF	0x01

641 lines not on this page · raw message

index 7a12619459..c55ef19a8c 100644
@@ -71,18 +71,6 @@
 #define ICE_PROFID_IPV6_PFCP_SESSION	82
 
 #define DUMMY_ETH_HDR_LEN		16
-#define ICE_SW_RULE_RX_TX_ETH_HDR_SIZE \
-	(offsetof(struct ice_aqc_sw_rules_elem, pdata.lkup_tx_rx.hdr) + \
-	 (DUMMY_ETH_HDR_LEN * \
-	  sizeof(((struct ice_sw_rule_lkup_rx_tx *)0)->hdr[0])))
-#define ICE_SW_RULE_RX_TX_NO_HDR_SIZE \
-	(offsetof(struct ice_aqc_sw_rules_elem, pdata.lkup_tx_rx.hdr))
-#define ICE_SW_RULE_LG_ACT_SIZE(n) \
-	(offsetof(struct ice_aqc_sw_rules_elem, pdata.lg_act.act) + \
-	 ((n) * sizeof(((struct ice_sw_rule_lg_act *)0)->act[0])))
-#define ICE_SW_RULE_VSI_LIST_SIZE(n) \
-	(offsetof(struct ice_aqc_sw_rules_elem, pdata.vsi_list.vsi) + \
-	 ((n) * sizeof(((struct ice_sw_rule_vsi_list *)0)->vsi[0])))
 
 /* Worst case buffer length for ice_aqc_opc_get_res_alloc */
 #define ICE_MAX_RES_TYPES 0x80

index c34407b48c..acd6ad249b 100644
@@ -101,13 +101,6 @@ ice_alloc_ctrlq_sq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 	if (!cq->sq.desc_buf.va)
 		return ICE_ERR_NO_MEMORY;
 
-	cq->sq.cmd_buf = ice_calloc(hw, cq->num_sq_entries,
-				    sizeof(struct ice_sq_cd));
-	if (!cq->sq.cmd_buf) {
-		ice_free_dma_mem(hw, &cq->sq.desc_buf);
-		return ICE_ERR_NO_MEMORY;
-	}
-
 	return ICE_SUCCESS;
 }
 

@@ -176,7 +169,7 @@ ice_alloc_rq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 		if (cq->rq_buf_size > ICE_AQ_LG_BUF)
 			desc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_LB);
 		desc->opcode = 0;
-		/* This is in accordance with Admin queue design, there is no
+		/* This is in accordance with control queue design, there is no
 		 * register for buffer size configuration
 		 */
 		desc->datalen = CPU_TO_LE16(bi->size);

@@ -309,9 +302,6 @@ do {									\
 				ice_free_dma_mem((hw),			\
 					&(qi)->ring.r.ring##_bi[i]);	\
 	}								\
-	/* free the buffer info list */					\
-	if ((qi)->ring.cmd_buf)						\
-		ice_free(hw, (qi)->ring.cmd_buf);			\
 	/* free DMA head */						\
 	ice_free(hw, (qi)->ring.dma_head);				\
 } while (0)

@@ -379,11 +369,11 @@ static enum ice_status ice_init_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 }
 
 /**
- * ice_init_rq - initialize ARQ
+ * ice_init_rq - initialize receive side of a control queue
  * @hw: pointer to the hardware structure
  * @cq: pointer to the specific Control queue
  *
- * The main initialization routine for the Admin Receive (Event) Queue.
+ * The main initialization routine for Receive side of a control queue.
  * Prior to calling this function, the driver *MUST* set the following fields
  * in the cq->structure:
  *     - cq->num_rq_entries

@@ -441,7 +431,7 @@ static enum ice_status ice_init_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 }
 
 /**
- * ice_shutdown_sq - shutdown the Control ATQ
+ * ice_shutdown_sq - shutdown the transmit side of a control queue
  * @hw: pointer to the hardware structure
  * @cq: pointer to the specific Control queue
  *

@@ -461,7 +451,7 @@ ice_shutdown_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 		goto shutdown_sq_out;
 	}
 
-	/* Stop firmware AdminQ processing */
+	/* Stop processing of the control queue */
 	wr32(hw, cq->sq.head, 0);
 	wr32(hw, cq->sq.tail, 0);
 	wr32(hw, cq->sq.len, 0);

@@ -834,7 +824,7 @@ void ice_destroy_all_ctrlq(struct ice_hw *hw)
 }
 
 /**
- * ice_clean_sq - cleans Admin send queue (ATQ)
+ * ice_clean_sq - cleans send side of a control queue
  * @hw: pointer to the hardware structure
  * @cq: pointer to the specific Control queue
  *

@@ -844,21 +834,17 @@ static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 {
 	struct ice_ctl_q_ring *sq = &cq->sq;
 	u16 ntc = sq->next_to_clean;
-	struct ice_sq_cd *details;
 	struct ice_aq_desc *desc;
 
 	desc = ICE_CTL_Q_DESC(*sq, ntc);
-	details = ICE_CTL_Q_DETAILS(*sq, ntc);
 
 	while (rd32(hw, cq->sq.head) != ntc) {
 		ice_debug(hw, ICE_DBG_AQ_MSG, "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head));
 		ice_memset(desc, 0, sizeof(*desc), ICE_DMA_MEM);
-		ice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM);
 		ntc++;
 		if (ntc == sq->count)
 			ntc = 0;
 		desc = ICE_CTL_Q_DESC(*sq, ntc);
-		details = ICE_CTL_Q_DETAILS(*sq, ntc);
 	}
 
 	sq->next_to_clean = ntc;

@@ -866,16 +852,42 @@ static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 	return ICE_CTL_Q_DESC_UNUSED(sq);
 }
 
+/**
+ * ice_ctl_q_str - Convert control queue type to string
+ * @qtype: the control queue type
+ *
+ * Returns: A string name for the given control queue type.
+ */
+static const char *ice_ctl_q_str(enum ice_ctl_q qtype)
+{
+	switch (qtype) {
+	case ICE_CTL_Q_UNKNOWN:
+		return "Unknown CQ";
+	case ICE_CTL_Q_ADMIN:
+		return "AQ";
+	case ICE_CTL_Q_MAILBOX:
+		return "MBXQ";
+	case ICE_CTL_Q_SB:
+		return "SBQ";
+	default:
+		return "Unrecognized CQ";
+	}
+}
+
 /**
  * ice_debug_cq
  * @hw: pointer to the hardware structure
+ * @cq: pointer to the specific Control queue
  * @desc: pointer to control queue descriptor
  * @buf: pointer to command buffer
  * @buf_len: max length of buf
+ * @response: true if this is the writeback response
  *
  * Dumps debug log about control command with descriptor contents.
  */
-static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)
+static void
+ice_debug_cq(struct ice_hw *hw, struct ice_ctl_q_info *cq,
+	     void *desc, void *buf, u16 buf_len, bool response)
 {
 	struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;
 	u16 datalen, flags;

@@ -889,7 +901,8 @@ static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)
 	datalen = LE16_TO_CPU(cq_desc->datalen);
 	flags = LE16_TO_CPU(cq_desc->flags);
 
-	ice_debug(hw, ICE_DBG_AQ_DESC, "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
+	ice_debug(hw, ICE_DBG_AQ_DESC, "%s %s: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
+		  ice_ctl_q_str(cq->qtype), response ? "Response" : "Command",
 		  LE16_TO_CPU(cq_desc->opcode), flags, datalen,
 		  LE16_TO_CPU(cq_desc->retval));
 	ice_debug(hw, ICE_DBG_AQ_DESC, "\tcookie (h,l) 0x%08X 0x%08X\n",

@@ -914,23 +927,23 @@ static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)
 }
 
 /**
- * ice_sq_done - check if FW has processed the Admin Send Queue (ATQ)
+ * ice_sq_done - check if the last send on a control queue has completed
  * @hw: pointer to the HW struct
  * @cq: pointer to the specific Control queue
  *
- * Returns true if the firmware has processed all descriptors on the
- * admin send queue. Returns false if there are still requests pending.
+ * Returns: true if all the descriptors on the send side of a control queue
+ *          are finished processing, false otherwise.
  */
 static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 {
-	/* AQ designers suggest use of head for better
+	/* control queue designers suggest use of head for better
 	 * timing reliability than DD bit
 	 */
 	return rd32(hw, cq->sq.head) == cq->sq.next_to_use;
 }
 
 /**
- * ice_sq_send_cmd_nolock - send command to Control Queue (ATQ)
+ * ice_sq_send_cmd_nolock - send command to a control queue
  * @hw: pointer to the HW struct
  * @cq: pointer to the specific Control queue
  * @desc: prefilled descriptor describing the command (non DMA mem)

@@ -938,8 +951,9 @@ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
  * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
  * @cd: pointer to command details structure
  *
- * This is the main send command routine for the ATQ. It runs the queue,
- * cleans the queue, etc.
+ * This is the main send command routine for a control queue. It prepares the
+ * command into a descriptor, bumps the send queue tail, waits for the command
+ * to complete, captures status and data for the command, etc.
  */
 enum ice_status
 ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,

@@ -950,7 +964,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
 	struct ice_aq_desc *desc_on_ring;
 	bool cmd_completed = false;
 	enum ice_status status = ICE_SUCCESS;
-	struct ice_sq_cd *details;
 	u32 total_delay = 0;
 	u16 retval = 0;
 	u32 val = 0;

@@ -993,12 +1006,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
 		goto sq_send_command_error;
 	}
 
-	details = ICE_CTL_Q_DETAILS(cq->sq, cq->sq.next_to_use);
-	if (cd)
-		*details = *cd;
-	else
-		ice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM);
-
 	/* Call clean and check queue available function to reclaim the
 	 * descriptors that were processed by FW/MBX; the function returns the
 	 * number of desc available. The clean function called here could be

@@ -1035,8 +1042,7 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
 
 	/* Debug desc and buffer */
 	ice_debug(hw, ICE_DBG_AQ_DESC, "ATQ: Control Send queue desc and buffer:\n");
-
-	ice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size);
+	ice_debug_cq(hw, cq, (void *)desc_on_ring, buf, buf_size, false);
 
 	(cq->sq.next_to_use)++;
 	if (cq->sq.next_to_use == cq->sq.count)

@@ -1084,13 +1090,12 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
 	}
 
 	ice_debug(hw, ICE_DBG_AQ_MSG, "ATQ: desc and buffer writeback:\n");
-
-	ice_debug_cq(hw, (void *)desc, buf, buf_size);
+	ice_debug_cq(hw, cq, (void *)desc, buf, buf_size, true);
 
 	/* save writeback AQ if requested */
-	if (details->wb_desc)
-		ice_memcpy(details->wb_desc, desc_on_ring,
-			   sizeof(*details->wb_desc), ICE_DMA_TO_NONDMA);
+	if (cd && cd->wb_desc)
+		ice_memcpy(cd->wb_desc, desc_on_ring,
+			   sizeof(*cd->wb_desc), ICE_DMA_TO_NONDMA);
 
 	/* update the error if time out occurred */
 	if (!cmd_completed) {

@@ -1109,7 +1114,7 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
 }
 
 /**
- * ice_sq_send_cmd - send command to Control Queue (ATQ)
+ * ice_sq_send_cmd - send command to a control queue
  * @hw: pointer to the HW struct
  * @cq: pointer to the specific Control queue
  * @desc: prefilled descriptor describing the command

@@ -1117,8 +1122,9 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
  * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
  * @cd: pointer to command details structure
  *
- * This is the main send command routine for the ATQ. It runs the queue,
- * cleans the queue, etc.
+ * Main command for the transmit side of a control queue. It puts the command
+ * on the queue, bumps the tail, waits for processing of the command, captures
+ * command status and results, etc.
  */
 enum ice_status
 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,

@@ -1160,9 +1166,9 @@ void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode)
  * @e: event info from the receive descriptor, includes any buffers
  * @pending: number of events that could be left to process
  *
- * This function cleans one Admin Receive Queue element and returns
- * the contents through e. It can also return how many events are
- * left to process through 'pending'.
+ * Clean one element from the receive side of a control queue. On return 'e'
+ * contains contents of the message, and 'pending' contains the number of
+ * events left to process.
  */
 enum ice_status
 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,

@@ -1218,8 +1224,7 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
 			   e->msg_len, ICE_DMA_TO_NONDMA);
 
 	ice_debug(hw, ICE_DBG_AQ_DESC, "ARQ: desc and buffer:\n");
-
-	ice_debug_cq(hw, (void *)desc, e->msg_buf, cq->rq_buf_size);
+	ice_debug_cq(hw, cq, (void *)desc, e->msg_buf, cq->rq_buf_size, true);
 
 	/* Restore the original datalen and buffer address in the desc,
 	 * FW updates datalen to indicate the event message size

index 986604ec3c..5c60469693 100644
@@ -43,7 +43,6 @@ enum ice_ctl_q {
 struct ice_ctl_q_ring {
 	void *dma_head;			/* Virtual address to DMA head */
 	struct ice_dma_mem desc_buf;	/* descriptor ring memory */
-	void *cmd_buf;			/* command buffer memory */
 
 	union {
 		struct ice_dma_mem *sq_bi;

@@ -73,8 +72,6 @@ struct ice_sq_cd {
 	struct ice_aq_desc *wb_desc;
 };
 
-#define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
-
 /* rq event information */
 struct ice_rq_event_info {
 	struct ice_aq_desc desc;

index c34407b48c..acd6ad249b 100644
@@ -101,13 +101,6 @@ ice_alloc_ctrlq_sq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)
         if (!cq->sq.desc_buf.va)
                 return ICE_ERR_NO_MEMORY;
 
-       cq->sq.cmd_buf = ice_calloc(hw, cq->num_sq_entries,
-                                   sizeof(struct ice_sq_cd));
-       if (!cq->sq.cmd_buf) {
-               ice_free_dma_mem(hw, &cq->sq.desc_buf);
-               return ICE_ERR_NO_MEMORY;
-       }
-
         return ICE_SUCCESS;
 }
 

@@ -176,7 +169,7 @@ ice_alloc_rq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
                 if (cq->rq_buf_size > ICE_AQ_LG_BUF)
                         desc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_LB);
                 desc->opcode = 0;
-               /* This is in accordance with Admin queue design, there is no
+               /* This is in accordance with control queue design, there is no
                  * register for buffer size configuration
                  */
                 desc->datalen = CPU_TO_LE16(bi->size);

@@ -309,9 +302,6 @@ do {                                                                        \
                                 ice_free_dma_mem((hw),                  \
                                         &(qi)->ring.r.ring##_bi[i]);    \
         }                                                               \
-       /* free the buffer info list */                                 \
-       if ((qi)->ring.cmd_buf)                                         \
-               ice_free(hw, (qi)->ring.cmd_buf);                       \
         /* free DMA head */                                             \
         ice_free(hw, (qi)->ring.dma_head);                              \
 } while (0)

@@ -379,11 +369,11 @@ static enum ice_status ice_init_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 }
 
 /**
- * ice_init_rq - initialize ARQ
+ * ice_init_rq - initialize receive side of a control queue
  * @hw: pointer to the hardware structure
  * @cq: pointer to the specific Control queue
  *
- * The main initialization routine for the Admin Receive (Event) Queue.
+ * The main initialization routine for Receive side of a control queue.
  * Prior to calling this function, the driver *MUST* set the following fields
  * in the cq->structure:
  *     - cq->num_rq_entries

@@ -441,7 +431,7 @@ static enum ice_status ice_init_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 }
 
 /**
- * ice_shutdown_sq - shutdown the Control ATQ
+ * ice_shutdown_sq - shutdown the transmit side of a control queue
  * @hw: pointer to the hardware structure
  * @cq: pointer to the specific Control queue
  *

@@ -461,7 +451,7 @@ ice_shutdown_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
                 goto shutdown_sq_out;
         }
 
-       /* Stop firmware AdminQ processing */
+       /* Stop processing of the control queue */
         wr32(hw, cq->sq.head, 0);
         wr32(hw, cq->sq.tail, 0);
         wr32(hw, cq->sq.len, 0);

@@ -834,7 +824,7 @@ void ice_destroy_all_ctrlq(struct ice_hw *hw)
 }
 
 /**
- * ice_clean_sq - cleans Admin send queue (ATQ)
+ * ice_clean_sq - cleans send side of a control queue
  * @hw: pointer to the hardware structure
  * @cq: pointer to the specific Control queue
  *

@@ -844,21 +834,17 @@ static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 {
         struct ice_ctl_q_ring *sq = &cq->sq;
         u16 ntc = sq->next_to_clean;
-       struct ice_sq_cd *details;
         struct ice_aq_desc *desc;
 
         desc = ICE_CTL_Q_DESC(*sq, ntc);
-       details = ICE_CTL_Q_DETAILS(*sq, ntc);
 
         while (rd32(hw, cq->sq.head) != ntc) {
                 ice_debug(hw, ICE_DBG_AQ_MSG, "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head));
                 ice_memset(desc, 0, sizeof(*desc), ICE_DMA_MEM);
-               ice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM);
                 ntc++;
                 if (ntc == sq->count)
                         ntc = 0;
                 desc = ICE_CTL_Q_DESC(*sq, ntc);
-               details = ICE_CTL_Q_DETAILS(*sq, ntc);
         }
 
         sq->next_to_clean = ntc;

@@ -866,16 +852,42 @@ static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
         return ICE_CTL_Q_DESC_UNUSED(sq);
 }
 
+/**
+ * ice_ctl_q_str - Convert control queue type to string
+ * @qtype: the control queue type
+ *
+ * Returns: A string name for the given control queue type.
+ */
+static const char *ice_ctl_q_str(enum ice_ctl_q qtype)
+{
+       switch (qtype) {
+       case ICE_CTL_Q_UNKNOWN:
+               return "Unknown CQ";
+       case ICE_CTL_Q_ADMIN:
+               return "AQ";
+       case ICE_CTL_Q_MAILBOX:
+               return "MBXQ";
+       case ICE_CTL_Q_SB:
+               return "SBQ";
+       default:
+               return "Unrecognized CQ";
+       }
+}
+
 /**
  * ice_debug_cq
  * @hw: pointer to the hardware structure
+ * @cq: pointer to the specific Control queue
  * @desc: pointer to control queue descriptor
  * @buf: pointer to command buffer
  * @buf_len: max length of buf
+ * @response: true if this is the writeback response
  *
  * Dumps debug log about control command with descriptor contents.
  */
-static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)
+static void
+ice_debug_cq(struct ice_hw *hw, struct ice_ctl_q_info *cq,
+            void *desc, void *buf, u16 buf_len, bool response)
 {
         struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;
         u16 datalen, flags;

@@ -889,7 +901,8 @@ static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)
         datalen = LE16_TO_CPU(cq_desc->datalen);
         flags = LE16_TO_CPU(cq_desc->flags);
 
-       ice_debug(hw, ICE_DBG_AQ_DESC, "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
+       ice_debug(hw, ICE_DBG_AQ_DESC, "%s %s: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
+                 ice_ctl_q_str(cq->qtype), response ? "Response" : "Command",
                   LE16_TO_CPU(cq_desc->opcode), flags, datalen,
                   LE16_TO_CPU(cq_desc->retval));
         ice_debug(hw, ICE_DBG_AQ_DESC, "\tcookie (h,l) 0x%08X 0x%08X\n",

@@ -914,23 +927,23 @@ static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)
 }
 
 /**
- * ice_sq_done - check if FW has processed the Admin Send Queue (ATQ)
+ * ice_sq_done - check if the last send on a control queue has completed
  * @hw: pointer to the HW struct
  * @cq: pointer to the specific Control queue
  *
- * Returns true if the firmware has processed all descriptors on the
- * admin send queue. Returns false if there are still requests pending.
+ * Returns: true if all the descriptors on the send side of a control queue
+ *          are finished processing, false otherwise.
  */
 static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 {
-       /* AQ designers suggest use of head for better
+       /* control queue designers suggest use of head for better
          * timing reliability than DD bit
          */
         return rd32(hw, cq->sq.head) == cq->sq.next_to_use;
 }
 
 /**
- * ice_sq_send_cmd_nolock - send command to Control Queue (ATQ)
+ * ice_sq_send_cmd_nolock - send command to a control queue
  * @hw: pointer to the HW struct
  * @cq: pointer to the specific Control queue
  * @desc: prefilled descriptor describing the command (non DMA mem)

@@ -938,8 +951,9 @@ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
  * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
  * @cd: pointer to command details structure
  *
- * This is the main send command routine for the ATQ. It runs the queue,
- * cleans the queue, etc.
+ * This is the main send command routine for a control queue. It prepares the
+ * command into a descriptor, bumps the send queue tail, waits for the command
+ * to complete, captures status and data for the command, etc.
  */
 enum ice_status
 ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,

@@ -950,7 +964,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
         struct ice_aq_desc *desc_on_ring;
         bool cmd_completed = false;
         enum ice_status status = ICE_SUCCESS;
-       struct ice_sq_cd *details;
         u32 total_delay = 0;
         u16 retval = 0;
         u32 val = 0;

@@ -993,12 +1006,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
                 goto sq_send_command_error;
         }
 
-       details = ICE_CTL_Q_DETAILS(cq->sq, cq->sq.next_to_use);
-       if (cd)
-               *details = *cd;
-       else
-               ice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM);
-
         /* Call clean and check queue available function to reclaim the
          * descriptors that were processed by FW/MBX; the function returns the
          * number of desc available. The clean function called here could be

@@ -1035,8 +1042,7 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
 
         /* Debug desc and buffer */
         ice_debug(hw, ICE_DBG_AQ_DESC, "ATQ: Control Send queue desc and buffer:\n");
-
-       ice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size);
+       ice_debug_cq(hw, cq, (void *)desc_on_ring, buf, buf_size, false);
 
         (cq->sq.next_to_use)++;
         if (cq->sq.next_to_use == cq->sq.count)

@@ -1084,13 +1090,12 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
         }
 
         ice_debug(hw, ICE_DBG_AQ_MSG, "ATQ: desc and buffer writeback:\n");
-
-       ice_debug_cq(hw, (void *)desc, buf, buf_size);
+       ice_debug_cq(hw, cq, (void *)desc, buf, buf_size, true);
 
         /* save writeback AQ if requested */
-       if (details->wb_desc)
-               ice_memcpy(details->wb_desc, desc_on_ring,
-                          sizeof(*details->wb_desc), ICE_DMA_TO_NONDMA);
+       if (cd && cd->wb_desc)
+               ice_memcpy(cd->wb_desc, desc_on_ring,
+                          sizeof(*cd->wb_desc), ICE_DMA_TO_NONDMA);
 
         /* update the error if time out occurred */
         if (!cmd_completed) {

@@ -1109,7 +1114,7 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
 }
 
 /**
- * ice_sq_send_cmd - send command to Control Queue (ATQ)
+ * ice_sq_send_cmd - send command to a control queue
  * @hw: pointer to the HW struct
  * @cq: pointer to the specific Control queue
  * @desc: prefilled descriptor describing the command

@@ -1117,8 +1122,9 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
  * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
  * @cd: pointer to command details structure
  *
- * This is the main send command routine for the ATQ. It runs the queue,
- * cleans the queue, etc.
+ * Main command for the transmit side of a control queue. It puts the command
+ * on the queue, bumps the tail, waits for processing of the command, captures
+ * command status and results, etc.
  */
 enum ice_status
 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,

@@ -1160,9 +1166,9 @@ void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode)
  * @e: event info from the receive descriptor, includes any buffers
  * @pending: number of events that could be left to process
  *
- * This function cleans one Admin Receive Queue element and returns
- * the contents through e. It can also return how many events are
- * left to process through 'pending'.
+ * Clean one element from the receive side of a control queue. On return 'e'
+ * contains contents of the message, and 'pending' contains the number of
+ * events left to process.
  */
 enum ice_status
 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,

@@ -1218,8 +1224,7 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
                            e->msg_len, ICE_DMA_TO_NONDMA);
 
         ice_debug(hw, ICE_DBG_AQ_DESC, "ARQ: desc and buffer:\n");
-
-       ice_debug_cq(hw, (void *)desc, e->msg_buf, cq->rq_buf_size);
+       ice_debug_cq(hw, cq, (void *)desc, e->msg_buf, cq->rq_buf_size, true);
 
         /* Restore the original datalen and buffer address in the desc,
          * FW updates datalen to indicate the event message size

index 986604ec3c..5c60469693 100644
@@ -43,7 +43,6 @@ enum ice_ctl_q {
 struct ice_ctl_q_ring {
         void *dma_head;                 /* Virtual address to DMA head */
         struct ice_dma_mem desc_buf;    /* descriptor ring memory */
-       void *cmd_buf;                  /* command buffer memory */
 
         union {
                 struct ice_dma_mem *sq_bi;

@@ -73,8 +72,6 @@ struct ice_sq_cd {
         struct ice_aq_desc *wb_desc;
 };
 
-#define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
-
 /* rq event information */
 struct ice_rq_event_info {
         struct ice_aq_desc desc;

index 5254ee27ed..8db394471c 100644
@@ -1132,6 +1132,7 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
 			ice_and_bitmap(params->ptypes, params->ptypes, src,
 				       ICE_FLOW_PTYPE_MAX);
 		}
+
 		if ((hdrs & ICE_FLOW_SEG_HDR_IPV4) &&
 		    (hdrs & ICE_FLOW_SEG_HDR_IPV_OTHER)) {
 			src = i ?

@@ -1371,7 +1372,7 @@ ice_flow_xtract_pkt_flags(struct ice_hw *hw,
  */
 static enum ice_status
 ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
-		    u8 seg, enum ice_flow_field fld, u64 match)
+		    u8 seg, enum ice_flow_field fld, ice_bitmap_t *match)
 {
 	enum ice_flow_field sib = ICE_FLOW_FIELD_IDX_MAX;
 	u8 fv_words = (u8)hw->blk[params->blk].es.fvw;

@@ -1420,7 +1421,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
 		/* If the sibling field is also included, that field's
 		 * mask needs to be included.
 		 */
-		if (match & BIT(sib))
+		if (ice_is_bit_set(match, sib))
 			sib_mask = ice_flds_info[sib].mask;
 		break;
 	case ICE_FLOW_FIELD_IDX_IPV6_TTL:

@@ -1451,7 +1452,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
 		/* If the sibling field is also included, that field's
 		 * mask needs to be included.
 		 */
-		if (match & BIT(sib))
+		if (ice_is_bit_set(match, sib))
 			sib_mask = ice_flds_info[sib].mask;
 		break;
 	case ICE_FLOW_FIELD_IDX_IPV4_SA:

@@ -1722,15 +1723,16 @@ ice_flow_create_xtrct_seq(struct ice_hw *hw,
 	}
 
 	for (i = 0; i < params->prof->segs_cnt; i++) {
-		u64 match = params->prof->segs[i].match;
+		ice_declare_bitmap(match, ICE_FLOW_FIELD_IDX_MAX);
 		enum ice_flow_field j;
 
-		ice_for_each_set_bit(j, (ice_bitmap_t *)&match,
-				     ICE_FLOW_FIELD_IDX_MAX) {
+		ice_cp_bitmap(match, params->prof->segs[i].match,
+			      ICE_FLOW_FIELD_IDX_MAX);
+		ice_for_each_set_bit(j, match, ICE_FLOW_FIELD_IDX_MAX) {
 			status = ice_flow_xtract_fld(hw, params, i, j, match);
 			if (status)
 				return status;
-			ice_clear_bit(j, (ice_bitmap_t *)&match);
+			ice_clear_bit(j, match);
 		}
 
 		/* Process raw matching bytes */

@@ -1789,7 +1791,7 @@ ice_flow_acl_def_entry_frmt(struct ice_flow_prof_params *params)
 		struct ice_flow_seg_info *seg = &params->prof->segs[i];
 		u16 j;
 
-		ice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,
+		ice_for_each_set_bit(j, seg->match,
 				     (u16)ICE_FLOW_FIELD_IDX_MAX) {
 			struct ice_flow_fld_info *fld = &seg->fields[j];
 

@@ -1932,7 +1934,10 @@ ice_flow_find_prof_conds(struct ice_hw *hw, enum ice_block blk,
 			for (i = 0; i < segs_cnt; i++)
 				if (segs[i].hdrs != p->segs[i].hdrs ||
 				    ((conds & ICE_FLOW_FIND_PROF_CHK_FLDS) &&
-				     segs[i].match != p->segs[i].match))
+				     (ice_cmp_bitmap(segs[i].match,
+						     p->segs[i].match,
+						     ICE_FLOW_FIELD_IDX_MAX) ==
+				       false)))
 					break;
 
 			/* A match is found if all segments are matched */

@@ -2432,7 +2437,7 @@ ice_flow_acl_set_xtrct_seq(struct ice_hw *hw, struct ice_flow_prof *prof)
 			struct ice_flow_seg_info *seg = &prof->segs[i];
 			u16 j;
 
-			ice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,
+			ice_for_each_set_bit(j, seg->match,
 					     ICE_FLOW_FIELD_IDX_MAX) {
 				info = &seg->fields[j];
 

@@ -2601,7 +2606,8 @@ ice_flow_set_hw_prof(struct ice_hw *hw, u16 dest_vsi_handle,
 			idx = i;
 		params->es[idx].prot_id = prof->fv[i].proto_id;
 		params->es[idx].off = prof->fv[i].offset;
-		params->mask[idx] = CPU_TO_BE16(prof->fv[i].msk);
+		params->mask[idx] = (((prof->fv[i].msk) << 8) & 0xff00) |
+				    (((prof->fv[i].msk) >> 8) & 0x00ff);
 	}
 
 	switch (prof->flags) {

@@ -3002,7 +3008,7 @@ ice_flow_acl_frmt_entry(struct ice_hw *hw, struct ice_flow_prof *prof,
 		struct ice_flow_seg_info *seg = &prof->segs[i];
 		u16 j;
 
-		ice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,
+		ice_for_each_set_bit(j, seg->match,
 				     (u16)ICE_FLOW_FIELD_IDX_MAX) {
 			struct ice_flow_fld_info *info = &seg->fields[j];
 

@@ -3534,7 +3540,7 @@ enum ice_status ice_flow_rem_entry(struct ice_hw *hw, enum ice_block blk,
 	if (entry_h == ICE_FLOW_ENTRY_HANDLE_INVAL)
 		return ICE_ERR_PARAM;
 
-	entry = ICE_FLOW_ENTRY_PTR((intptr_t)entry_h);
+	entry = ICE_FLOW_ENTRY_PTR(entry_h);
 
 	/* Retain the pointer to the flow profile as the entry will be freed */
 	prof = entry->prof;

@@ -3576,11 +3582,9 @@ ice_flow_set_fld_ext(struct ice_flow_seg_info *seg, enum ice_flow_field fld,
 		     enum ice_flow_fld_match_type field_type, u16 val_loc,
 		     u16 mask_loc, u16 last_loc)
 {
-	u64 bit = BIT_ULL(fld);
-
-	seg->match |= bit;
+	ice_set_bit(fld, seg->match);
 	if (field_type == ICE_FLOW_FLD_TYPE_RANGE)
-		seg->range |= bit;
+		ice_set_bit(fld, seg->range);
 
 	seg->fields[fld].type = field_type;
 	seg->fields[fld].src.val = val_loc;

@@ -3741,7 +3745,7 @@ enum ice_status ice_flow_rem_vsi_prof(struct ice_hw *hw, enum ice_block blk, u16
 }
 
 #define ICE_FLOW_RSS_SEG_HDR_L2_MASKS \
-(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_ETH_NON_IP | ICE_FLOW_SEG_HDR_VLAN)
+(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
 
 #define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \
 	(ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)

@@ -3856,6 +3860,7 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle)
 	const enum ice_block blk = ICE_BLK_RSS;
 	struct ice_flow_prof *p, *t;
 	enum ice_status status = ICE_SUCCESS;
+	u16 vsig;
 
 	if (!ice_is_vsi_valid(hw, vsi_handle))
 		return ICE_ERR_PARAM;

@@ -3865,7 +3870,16 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle)
 
 	ice_acquire_lock(&hw->rss_locks);
 	LIST_FOR_EACH_ENTRY_SAFE(p, t, &hw->fl_profs[blk], ice_flow_prof,
-				 l_entry)
+				 l_entry) {
+		int ret;
+
+		/* check if vsig is already removed */
+		ret = ice_vsig_find_vsi(hw, blk,
+					ice_get_hw_vsi_num(hw, vsi_handle),
+					&vsig);
+		if (!ret && !vsig)
+			break;
+
 		if (ice_is_bit_set(p->vsis, vsi_handle)) {
 			status = ice_flow_disassoc_prof(hw, blk, p, vsi_handle);
 			if (status)

@@ -3877,6 +3891,7 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle)
 					break;
 			}
 		}
+	}
 	ice_release_lock(&hw->rss_locks);
 
 	return status;

@@ -3918,6 +3933,14 @@ ice_rem_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)
 {
 	enum ice_rss_cfg_hdr_type hdr_type;
 	struct ice_rss_cfg *r, *tmp;
+	u64 seg_match = 0;
+	u16 i;
+
+	/* convert match bitmap to u64 for hash field comparison */
+	ice_for_each_set_bit(i, prof->segs[prof->segs_cnt - 1].match,
+			     ICE_FLOW_FIELD_IDX_MAX) {
+		seg_match |= 1ULL << i;
+	}
 
 	/* Search for RSS hash fields associated to the VSI that match the
 	 * hash configurations associated to the flow profile. If found

@@ -3926,7 +3949,7 @@ ice_rem_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)
 	hdr_type = ice_get_rss_hdr_type(prof);
 	LIST_FOR_EACH_ENTRY_SAFE(r, tmp, &hw->rss_list_head,
 				 ice_rss_cfg, l_entry)
-		if (r->hash.hash_flds == prof->segs[prof->segs_cnt - 1].match &&
+		if (r->hash.hash_flds == seg_match &&
 		    r->hash.addl_hdrs == prof->segs[prof->segs_cnt - 1].hdrs &&
 		    r->hash.hdr_type == hdr_type) {
 			ice_clear_bit(vsi_handle, r->vsis);

@@ -3951,11 +3974,18 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)
 {
 	enum ice_rss_cfg_hdr_type hdr_type;
 	struct ice_rss_cfg *r, *rss_cfg;
+	u64 seg_match = 0;
+	u16 i;
+
+	ice_for_each_set_bit(i, prof->segs[prof->segs_cnt - 1].match,
+			     ICE_FLOW_FIELD_IDX_MAX) {
+		seg_match |= 1ULL << i;
+	}
 
 	hdr_type = ice_get_rss_hdr_type(prof);
 	LIST_FOR_EACH_ENTRY(r, &hw->rss_list_head,
 			    ice_rss_cfg, l_entry)
-		if (r->hash.hash_flds == prof->segs[prof->segs_cnt - 1].match &&
+		if (r->hash.hash_flds == seg_match &&
 		    r->hash.addl_hdrs == prof->segs[prof->segs_cnt - 1].hdrs &&
 		    r->hash.hdr_type == hdr_type) {
 			ice_set_bit(vsi_handle, r->vsis);

@@ -3966,7 +3996,7 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)
 	if (!rss_cfg)
 		return ICE_ERR_NO_MEMORY;
 
-	rss_cfg->hash.hash_flds = prof->segs[prof->segs_cnt - 1].match;
+	rss_cfg->hash.hash_flds = seg_match;
 	rss_cfg->hash.addl_hdrs = prof->segs[prof->segs_cnt - 1].hdrs;
 	rss_cfg->hash.hdr_type = hdr_type;
 	rss_cfg->hash.symm = prof->cfg.symm;

index 57e8e1f1df..1415f5ba87 100644
@@ -452,8 +452,10 @@ struct ice_flow_seg_fld_raw {
 
 struct ice_flow_seg_info {
 	u32 hdrs;	/* Bitmask indicating protocol headers present */
-	u64 match;	/* Bitmask indicating header fields to be matched */
-	u64 range;	/* Bitmask indicating header fields matched as ranges */
+	/* Bitmask indicating header fields to be matched */
+	ice_declare_bitmap(match, ICE_FLOW_FIELD_IDX_MAX);
+	/* Bitmask indicating header fields matched as ranges */
+	ice_declare_bitmap(range, ICE_FLOW_FIELD_IDX_MAX);
 
 	struct ice_flow_fld_info fields[ICE_FLOW_FIELD_IDX_MAX];
 

index 69e528a8c9..8731f35022 100644
@@ -1401,7 +1401,18 @@ struct ice_aqc_get_phy_caps {
 #define ICE_PHY_TYPE_HIGH_100G_CAUI2		BIT_ULL(2)
 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC	BIT_ULL(3)
 #define ICE_PHY_TYPE_HIGH_100G_AUI2		BIT_ULL(4)
-#define ICE_PHY_TYPE_HIGH_MAX_INDEX		4
+#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4		BIT_ULL(5)
+#define ICE_PHY_TYPE_HIGH_200G_SR4		BIT_ULL(6)
+#define ICE_PHY_TYPE_HIGH_200G_FR4		BIT_ULL(7)
+#define ICE_PHY_TYPE_HIGH_200G_LR4		BIT_ULL(8)
+#define ICE_PHY_TYPE_HIGH_200G_DR4		BIT_ULL(9)
+#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4		BIT_ULL(10)
+#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC	BIT_ULL(11)
+#define ICE_PHY_TYPE_HIGH_200G_AUI4		BIT_ULL(12)
+#define ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC	BIT_ULL(13)
+#define ICE_PHY_TYPE_HIGH_200G_AUI8		BIT_ULL(14)
+#define ICE_PHY_TYPE_HIGH_400GBASE_FR8		BIT_ULL(15)
+#define ICE_PHY_TYPE_HIGH_MAX_INDEX		15
 
 struct ice_aqc_get_phy_caps_data {
 	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */

@@ -2191,6 +2202,19 @@ struct ice_aqc_get_set_rss_keys {
 	u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
 };
 
+enum ice_lut_type {
+	ICE_LUT_VSI = 0,
+	ICE_LUT_PF = 1,
+	ICE_LUT_GLOBAL = 2,
+	ICE_LUT_TYPE_MASK = 3
+};
+
+enum ice_lut_size {
+	ICE_LUT_VSI_SIZE = 64,
+	ICE_LUT_GLOBAL_SIZE = 512,
+	ICE_LUT_PF_SIZE = 2048,
+};
+
 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
 struct ice_aqc_get_set_rss_lut {
 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID	BIT(15)

@@ -2199,7 +2223,7 @@ struct ice_aqc_get_set_rss_lut {
 	__le16 vsi_id;
 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S	0
 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M	\
-				(0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
+	(ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
 
 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI	 0
 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF	 1

@@ -2207,7 +2231,7 @@ struct ice_aqc_get_set_rss_lut {
 
 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S	 2
 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M	 \
-				(0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
+	(ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
 
 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128	 128
 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0

439 lines not on this page · raw message

index e1febfb0c4..f612ce7c52 100644
@@ -100,6 +100,7 @@ ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
 			  struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
 			  u32 tx_drbell_q_index);
 
+int ice_lut_size_to_type(int lut_size);
 enum ice_status
 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params);
 enum ice_status

106 lines not on this page · raw message

index 006ffa802c..5bd40ece78 100644
@@ -2369,6 +2369,11 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
 			true : false;
 		ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
 			  caps->nvm_unified_update);
+		caps->netlist_auth =
+			(number & ICE_NVM_MGMT_NETLIST_AUTH_SUPPORT) ?
+			true : false;
+		ice_debug(hw, ICE_DBG_INIT, "%s: netlist_auth = %d\n", prefix,
+			  caps->netlist_auth);
 		break;
 	case ICE_AQC_CAPS_MAX_MTU:
 		caps->max_mtu = number;

@@ -3814,6 +3819,7 @@ enum ice_status
 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
 			   struct ice_sq_cd *cd)
 {
+	enum ice_status status = ICE_ERR_AQ_ERROR;
 	struct ice_aqc_restart_an *cmd;
 	struct ice_aq_desc desc;
 

@@ -3828,7 +3834,16 @@ ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
 	else
 		cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
 
-	return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
+	status = ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
+	if (status)
+		return status;
+
+	if (ena_link)
+		pi->phy.curr_user_phy_cfg.caps |= ICE_AQC_PHY_EN_LINK;
+	else
+		pi->phy.curr_user_phy_cfg.caps &= ~ICE_AQC_PHY_EN_LINK;
+
+	return ICE_SUCCESS;
 }
 
 /**

index 83cd152388..e3a638dcdd 100644
@@ -1057,11 +1057,11 @@ ice_sched_add_nodes_to_layer(struct ice_port_info *pi,
 	u32 *first_teid_ptr = first_node_teid;
 	u16 new_num_nodes = num_nodes;
 	enum ice_status status = ICE_SUCCESS;
+	u32 temp;
 
 	*num_nodes_added = 0;
 	while (*num_nodes_added < num_nodes) {
 		u16 max_child_nodes, num_added = 0;
-		u32 temp;
 
 		status = ice_sched_add_nodes_to_hw_layer(pi, tc_node, parent,
 							 layer,	new_num_nodes,

92 lines not on this page · raw message

index c55ef19a8c..49bd535c79 100644
@@ -207,19 +207,19 @@ struct ice_adv_lkup_elem {
 	union ice_prot_hdr m_u;	/* Mask of header values to match */
 };
 
-struct lg_entry_vsi_fwd {
+struct entry_vsi_fwd {
 	u16 vsi_list;
 	u8 list;
 	u8 valid;
 };
 
-struct lg_entry_to_q {
+struct entry_to_q {
 	u16 q_idx;
 	u8 q_region_sz;
 	u8 q_pri;
 };
 
-struct lg_entry_prune {
+struct entry_prune {
 	u16 vsi_list;
 	u8 list;
 	u8 egr;

@@ -227,28 +227,29 @@ struct lg_entry_prune {
 	u8 prune_t;
 };
 
-struct lg_entry_mirror {
+struct entry_mirror {
 	u16 mirror_vsi;
 };
 
-struct lg_entry_generic_act {
+struct entry_generic_act {
 	u16 generic_value;
 	u8 offset;
 	u8 priority;
 };
 
-struct lg_entry_statistics {
+struct entry_statistics {
 	u8 counter_idx;
 };
 
 union lg_act_entry {
-	struct lg_entry_vsi_fwd vsi_fwd;
-	struct lg_entry_to_q to_q;
-	struct lg_entry_prune prune;
-	struct lg_entry_mirror mirror;
-	struct lg_entry_generic_act generic_act;
-	struct lg_entry_statistics statistics;
+	struct entry_vsi_fwd vsi_fwd;
+	struct entry_to_q to_q;
+	struct entry_prune prune;
+	struct entry_mirror mirror;
+	struct entry_generic_act generic_act;
+	struct entry_statistics statistics;
 };
+
 struct ice_prof_type_entry {
 	u16 prof_id;
 	enum ice_sw_tunnel_type type;

@@ -301,6 +302,7 @@ struct ice_adv_rule_info {
 	u8 rx; /* true means LOOKUP_RX otherwise LOOKUP_TX */
 	u16 fltr_rule_id;
 	u16 lg_id;
+	u16 vlan_type;
 	struct ice_adv_rule_flags_info flags_info;
 };
 

index 3249e359de..b2df99e472 100644
@@ -693,9 +693,11 @@ struct ice_hw_common_caps {
 	bool sec_rev_disabled;
 	bool update_disabled;
 	bool nvm_unified_update;
+	bool netlist_auth;
 #define ICE_NVM_MGMT_SEC_REV_DISABLED		BIT(0)
 #define ICE_NVM_MGMT_UPDATE_DISABLED		BIT(1)
 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT	BIT(3)
+#define ICE_NVM_MGMT_NETLIST_AUTH_SUPPORT	BIT(5)
 	/* PCIe reset avoidance */
 	bool pcie_reset_avoidance; /* false: not supported, true: supported */
 	/* Post update reset restriction */

@@ -1458,6 +1460,7 @@ enum ice_sw_fwd_act_type {
 	ICE_FWD_TO_QGRP,
 	ICE_SET_MARK,
 	ICE_DROP_PACKET,
+	ICE_LG_ACTION,
 	ICE_INVAL_ACT
 };
 

index 8731f35022..4c4fd27865 100644
@@ -120,6 +120,7 @@ struct ice_aqc_list_caps_elem {
 #define ICE_AQC_CAPS_1588				0x0046
 #define ICE_AQC_CAPS_MAX_MTU				0x0047
 #define ICE_AQC_CAPS_IWARP				0x0051
+#define ICE_AQC_CAPS_SENSOR_READING			0x0067
 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE		0x0076
 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT		0x0077
 #define ICE_AQC_CAPS_NVM_MGMT				0x0080

61 lines not on this page · raw message

index b2df99e472..17383ae23f 100644
@@ -787,6 +787,15 @@ struct ice_ts_dev_info {
 	u8 ts_ll_read : 1;
 };
 
+#define ICE_NAC_TOPO_PRIMARY_M	BIT(0)
+#define ICE_NAC_TOPO_DUAL_M	BIT(1)
+#define ICE_NAC_TOPO_ID_M	MAKEMASK(0xf, 0)
+
+struct ice_nac_topology {
+	u32 mode;
+	u8 id;
+};
+
 /* Function specific capabilities */
 struct ice_hw_func_caps {
 	struct ice_hw_common_caps common_cap;

@@ -803,6 +812,10 @@ struct ice_hw_dev_caps {
 	u32 num_flow_director_fltr;	/* Number of FD filters available */
 	struct ice_ts_dev_info ts_dev_info;
 	u32 num_funcs;
+	struct ice_nac_topology nac_topo;
+	/* bitmap of supported sensors */
+	u32 supported_sensors;
+#define ICE_SENSOR_SUPPORT_E810_INT_TEMP	BIT(0)
 };
 
 /* Information about MAC such as address, etc... */

index 4c4fd27865..5a44ebbdc0 100644
@@ -1681,6 +1681,32 @@ struct ice_aqc_set_mac_lb {
 	u8 reserved[15];
 };
 
+/* Get sensor reading (direct 0x0632) */
+struct ice_aqc_get_sensor_reading {
+	u8 sensor;
+#define ICE_AQC_INT_TEMP_SENSOR		0x0
+	u8 format;
+#define ICE_AQC_INT_TEMP_FORMAT		0x0
+	u8 reserved[6];
+	__le32 addr_high;
+	__le32 addr_low;
+};
+
+/* Get sensor reading response (direct 0x0632) */
+struct ice_aqc_get_sensor_reading_resp {
+	union {
+		u8 raw[8];
+		/* Output data for sensor 0x00, format 0x00 */
+		struct {
+			s8 temp;
+			u8 temp_warning_threshold;
+			u8 temp_critical_threshold;
+			u8 temp_fatal_threshold;
+			u8 reserved[4];
+		} s0f0;
+	} data;
+};
+
 struct ice_aqc_link_topo_params {
 	u8 lport_num;
 	u8 lport_num_valid;

@@ -3032,6 +3058,8 @@ struct ice_aq_desc {
 		struct ice_aqc_get_phy_caps get_phy;
 		struct ice_aqc_set_phy_cfg set_phy;
 		struct ice_aqc_restart_an restart_an;
+		struct ice_aqc_get_sensor_reading get_sensor_reading;
+		struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp;
 		struct ice_aqc_i2c read_write_i2c;
 		struct ice_aqc_read_i2c_resp read_i2c_resp;
 		struct ice_aqc_gpio read_write_gpio;

@@ -3281,6 +3309,7 @@ enum ice_adminq_opc {
 	ice_aqc_opc_get_link_status			= 0x0607,
 	ice_aqc_opc_set_event_mask			= 0x0613,
 	ice_aqc_opc_set_mac_lb				= 0x0620,
+	ice_aqc_opc_get_sensor_reading			= 0x0632,
 	ice_aqc_opc_get_link_topo			= 0x06E0,
 	ice_aqc_opc_get_link_topo_pin			= 0x06E1,
 	ice_aqc_opc_read_i2c				= 0x06E2,

index a51a436df6..ed811e406d 100644
@@ -5278,6 +5278,42 @@ ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
 			      ICE_SCHED_NODE_OWNER_LAN);
 }
 
+/**
+ * ice_aq_get_sensor_reading
+ * @hw: pointer to the HW struct
+ * @sensor: sensor type
+ * @format: requested response format
+ * @data: pointer to data to be read from the sensor
+ * @cd: pointer to command details structure or NULL
+ *
+ * Get sensor reading (0x0632)
+ */
+enum ice_status
+ice_aq_get_sensor_reading(struct ice_hw *hw, u8 sensor, u8 format,
+			  struct ice_aqc_get_sensor_reading_resp *data,
+			  struct ice_sq_cd *cd)
+{
+	struct ice_aqc_get_sensor_reading *cmd;
+	struct ice_aq_desc desc;
+	enum ice_status status;
+
+	if (!data)
+		return ICE_ERR_PARAM;
+
+	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading);
+	cmd = &desc.params.get_sensor_reading;
+	cmd->sensor = sensor;
+	cmd->format = format;
+
+	status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
+
+	if (!status)
+		ice_memcpy(data, &desc.params.get_sensor_reading_resp,
+			   sizeof(*data), ICE_NONDMA_TO_NONDMA);
+
+	return status;
+}
+
 /**
  * ice_is_main_vsi - checks whether the VSI is main VSI
  * @hw: pointer to the HW struct

index f612ce7c52..ccefe85af7 100644
@@ -29,7 +29,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw);
 void ice_deinit_hw(struct ice_hw *hw);
 enum ice_status ice_check_reset(struct ice_hw *hw);
 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);
-
 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw);
 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);
 void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading);

@@ -61,7 +60,6 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
 		struct ice_aq_desc *desc, void *buf, u16 buf_size,
 		struct ice_sq_cd *cd);
 void ice_clear_pxe_mode(struct ice_hw *hw);
-
 enum ice_status ice_get_caps(struct ice_hw *hw);
 
 void ice_set_safe_mode_caps(struct ice_hw *hw);

@@ -247,6 +245,10 @@ enum ice_status ice_sbq_rw_reg_lp(struct ice_hw *hw,
 void ice_sbq_lock(struct ice_hw *hw);
 void ice_sbq_unlock(struct ice_hw *hw);
 enum ice_status ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in);
+enum ice_status
+ice_aq_get_sensor_reading(struct ice_hw *hw, u8 sensor, u8 format,
+			  struct ice_aqc_get_sensor_reading_resp *data,
+			  struct ice_sq_cd *cd);
 void
 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
 		  u64 *prev_stat, u64 *cur_stat);

index 5a44ebbdc0..cd4a6ffddf 100644
@@ -1120,9 +1120,9 @@ struct ice_aqc_txsched_elem {
 	u8 generic;
 #define ICE_AQC_ELEM_GENERIC_MODE_M		0x1
 #define ICE_AQC_ELEM_GENERIC_PRIO_S		0x1
-#define ICE_AQC_ELEM_GENERIC_PRIO_M	(0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
+#define ICE_AQC_ELEM_GENERIC_PRIO_M		(0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
 #define ICE_AQC_ELEM_GENERIC_SP_S		0x4
-#define ICE_AQC_ELEM_GENERIC_SP_M	(0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
+#define ICE_AQC_ELEM_GENERIC_SP_M		(0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S	0x5
 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M	\
 	(0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)

index ed811e406d..984830ea37 100644
@@ -5129,7 +5129,7 @@ ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
 	q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
 
 	/* add a leaf node into scheduler tree queue layer */
-	status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
+	status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL);
 	if (!status)
 		status = ice_sched_replay_q_bw(pi, q_ctx);
 

index 2a308b02bf..ca418090bc 100644
@@ -1370,7 +1370,7 @@ ice_add_dscp_tc_bw_tlv(struct ice_lldp_org_tlv *tlv,
 			   ICE_DSCP_SUBTYPE_TCBW);
 	tlv->ouisubtype = HTONL(ouisubtype);
 
-	/* First Octet after subtype
+	/* First Octect after subtype
 	 * ----------------------------
 	 * | RSV | CBS | RSV | Max TCs |
 	 * | 1b  | 1b  | 3b  | 3b      |

@@ -1624,7 +1624,7 @@ ice_update_port_tc_tree_cfg(struct ice_port_info *pi,
 		/* new TC */
 		status = ice_sched_query_elem(pi->hw, teid2, &elem);
 		if (!status)
-			status = ice_sched_add_node(pi, 1, &elem);
+			status = ice_sched_add_node(pi, 1, &elem, NULL);
 		if (status)
 			break;
 		/* update the TC number */

511 lines not on this page · raw message

107 lines not on this page · raw message

index 17383ae23f..ec4892179a 100644
@@ -992,9 +992,11 @@ struct ice_sched_node {
 	u8 num_children;
 	u8 tc_num;
 	u8 owner;
+	u8 cgd;				/* Valid only for Layer 2 */
 #define ICE_SCHED_NODE_OWNER_LAN	0
 #define ICE_SCHED_NODE_OWNER_AE		1
 #define ICE_SCHED_NODE_OWNER_RDMA	2
+#define ICE_MAX_CGD_PER_PORT		4
 };
 
 /* Access Macros for Tx Sched Elements data */

@@ -1213,6 +1215,7 @@ struct ice_port_info {
 	struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
 	struct ice_qos_cfg qos_cfg;
 	u8 is_vf:1;
+	u8 is_custom_tx_enabled:1;
 };
 
 struct ice_switch_info {

index 984830ea37..cebf1504f1 100644
@@ -11,6 +11,80 @@
 
 #define ICE_PF_RESET_WAIT_COUNT	300
 
+static const char * const ice_link_mode_str_low[] = {
+	ice_arr_elem_idx(0, "100BASE_TX"),
+	ice_arr_elem_idx(1, "100M_SGMII"),
+	ice_arr_elem_idx(2, "1000BASE_T"),
+	ice_arr_elem_idx(3, "1000BASE_SX"),
+	ice_arr_elem_idx(4, "1000BASE_LX"),
+	ice_arr_elem_idx(5, "1000BASE_KX"),
+	ice_arr_elem_idx(6, "1G_SGMII"),
+	ice_arr_elem_idx(7, "2500BASE_T"),
+	ice_arr_elem_idx(8, "2500BASE_X"),
+	ice_arr_elem_idx(9, "2500BASE_KX"),
+	ice_arr_elem_idx(10, "5GBASE_T"),
+	ice_arr_elem_idx(11, "5GBASE_KR"),
+	ice_arr_elem_idx(12, "10GBASE_T"),
+	ice_arr_elem_idx(13, "10G_SFI_DA"),
+	ice_arr_elem_idx(14, "10GBASE_SR"),
+	ice_arr_elem_idx(15, "10GBASE_LR"),
+	ice_arr_elem_idx(16, "10GBASE_KR_CR1"),
+	ice_arr_elem_idx(17, "10G_SFI_AOC_ACC"),
+	ice_arr_elem_idx(18, "10G_SFI_C2C"),
+	ice_arr_elem_idx(19, "25GBASE_T"),
+	ice_arr_elem_idx(20, "25GBASE_CR"),
+	ice_arr_elem_idx(21, "25GBASE_CR_S"),
+	ice_arr_elem_idx(22, "25GBASE_CR1"),
+	ice_arr_elem_idx(23, "25GBASE_SR"),
+	ice_arr_elem_idx(24, "25GBASE_LR"),
+	ice_arr_elem_idx(25, "25GBASE_KR"),
+	ice_arr_elem_idx(26, "25GBASE_KR_S"),
+	ice_arr_elem_idx(27, "25GBASE_KR1"),
+	ice_arr_elem_idx(28, "25G_AUI_AOC_ACC"),
+	ice_arr_elem_idx(29, "25G_AUI_C2C"),
+	ice_arr_elem_idx(30, "40GBASE_CR4"),
+	ice_arr_elem_idx(31, "40GBASE_SR4"),
+	ice_arr_elem_idx(32, "40GBASE_LR4"),
+	ice_arr_elem_idx(33, "40GBASE_KR4"),
+	ice_arr_elem_idx(34, "40G_XLAUI_AOC_ACC"),
+	ice_arr_elem_idx(35, "40G_XLAUI"),
+	ice_arr_elem_idx(36, "50GBASE_CR2"),
+	ice_arr_elem_idx(37, "50GBASE_SR2"),
+	ice_arr_elem_idx(38, "50GBASE_LR2"),
+	ice_arr_elem_idx(39, "50GBASE_KR2"),
+	ice_arr_elem_idx(40, "50G_LAUI2_AOC_ACC"),
+	ice_arr_elem_idx(41, "50G_LAUI2"),
+	ice_arr_elem_idx(42, "50G_AUI2_AOC_ACC"),
+	ice_arr_elem_idx(43, "50G_AUI2"),
+	ice_arr_elem_idx(44, "50GBASE_CP"),
+	ice_arr_elem_idx(45, "50GBASE_SR"),
+	ice_arr_elem_idx(46, "50GBASE_FR"),
+	ice_arr_elem_idx(47, "50GBASE_LR"),
+	ice_arr_elem_idx(48, "50GBASE_KR_PAM4"),
+	ice_arr_elem_idx(49, "50G_AUI1_AOC_ACC"),
+	ice_arr_elem_idx(50, "50G_AUI1"),
+	ice_arr_elem_idx(51, "100GBASE_CR4"),
+	ice_arr_elem_idx(52, "100GBASE_SR4"),
+	ice_arr_elem_idx(53, "100GBASE_LR4"),
+	ice_arr_elem_idx(54, "100GBASE_KR4"),
+	ice_arr_elem_idx(55, "100G_CAUI4_AOC_ACC"),
+	ice_arr_elem_idx(56, "100G_CAUI4"),
+	ice_arr_elem_idx(57, "100G_AUI4_AOC_ACC"),
+	ice_arr_elem_idx(58, "100G_AUI4"),
+	ice_arr_elem_idx(59, "100GBASE_CR_PAM4"),
+	ice_arr_elem_idx(60, "100GBASE_KR_PAM4"),
+	ice_arr_elem_idx(61, "100GBASE_CP2"),
+	ice_arr_elem_idx(62, "100GBASE_SR2"),
+	ice_arr_elem_idx(63, "100GBASE_DR"),
+};
+
+static const char * const ice_link_mode_str_high[] = {
+	ice_arr_elem_idx(0, "100GBASE_KR2_PAM4"),
+	ice_arr_elem_idx(1, "100G_CAUI2_AOC_ACC"),
+	ice_arr_elem_idx(2, "100G_CAUI2"),
+	ice_arr_elem_idx(3, "100G_AUI2_AOC_ACC"),
+	ice_arr_elem_idx(4, "100G_AUI2"),
+};
 /**
  * dump_phy_type - helper function that prints PHY type strings
  * @hw: pointer to the HW structure

index ccefe85af7..83ef438041 100644
@@ -81,6 +81,14 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
  */
 #define ICE_ALIGN(ptr, align)	(((ptr) + ((align) - 1)) & ~((align) - 1))
 
+/* Define a macro for initializing array using indexes. Due to limitation
+ * of MSVC compiler it is necessary to allow other projects to replace
+ * that macro and strip the index from initialization.
+ * Linux driver is using coccinelle to maintain source sync with upstream
+ * and is not requiring this macro.
+ */
+#define ice_arr_elem_idx(idx, val)	[(idx)] = (val)
+
 enum ice_status
 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
 		  u32 rxq_index);

index 93ff2608d4..ae0a03c8ba 100644
@@ -1579,6 +1579,9 @@ ice_get_sw_fv_list(struct ice_hw *hw, struct ice_prot_lkup_ext *lkups,
 	struct ice_fv *fv;
 	u32 offset;
 
+	if (!lkups->n_val_words)
+		return ICE_SUCCESS;
+
 	ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM);
 
 	if (!lkups->n_val_words || !hw->seg)

index 1415f5ba87..2e5a3b386e 100644
@@ -7,6 +7,7 @@
 
 #include "ice_flex_type.h"
 #include "ice_acl.h"
+#include "ice_parser.h"
 
 #define ICE_IPV4_MAKE_PREFIX_MASK(prefix) ((u32)(~0) << (32 - (prefix)))
 #define ICE_FLOW_PROF_ID_INVAL		0xfffffffffffffffful

index d816df0ff6..229db1041c 100644
@@ -162,7 +162,6 @@ struct ice_fltr_desc {
 
 #define ICE_FXD_FLTR_QW1_FDID_PRI_S	25
 #define ICE_FXD_FLTR_QW1_FDID_PRI_M	(0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S)
-#define ICE_FXD_FLTR_QW1_FDID_PRI_ZERO	0x0ULL
 #define ICE_FXD_FLTR_QW1_FDID_PRI_ONE	0x1ULL
 #define ICE_FXD_FLTR_QW1_FDID_PRI_THREE	0x3ULL
 

index dd4cc38114..b3d9847669 100644
@@ -7500,25 +7500,6 @@ ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm,
 	return status;
 }
 
-/**
- * ice_get_fv - get field vectors/extraction sequences for spec. lookup types
- * @hw: pointer to hardware structure
- * @lkups: lookup elements or match criteria for the advanced recipe, one
- *	   structure per protocol header
- * @bm: bitmap of field vectors to consider
- * @fv_list: pointer to a list that holds the returned field vectors
- */
-static enum ice_status
-ice_get_fv(struct ice_hw *hw, struct ice_prot_lkup_ext *lkups,
-	   ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list)
-{
-	if (!lkups->n_val_words)
-		return ICE_SUCCESS;
-
-	/* Find field vectors that include all specified protocol types */
-	return ice_get_sw_fv_list(hw, lkups, bm, fv_list);
-}
-
 /**
  * ice_tun_type_match_word - determine if tun type needs a match mask
  * @tun_type: tunnel type

@@ -7905,11 +7886,11 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
 
 	/* Get bitmap of field vectors (profiles) that are compatible with the
 	 * rule request; only these will be searched in the subsequent call to
-	 * ice_get_fv.
+	 * ice_get_sw_fv_list.
 	 */
 	ice_get_compat_fv_bitmap(hw, rinfo, fv_bitmap);
 
-	status = ice_get_fv(hw, lkup_exts, fv_bitmap, &rm->fv_list);
+	status = ice_get_sw_fv_list(hw, lkup_exts, fv_bitmap, &rm->fv_list);
 	if (status)
 		goto err_unroll;
 

index 49bd535c79..adb467eb66 100644
@@ -498,8 +498,7 @@ ice_aq_get_res_descs(struct ice_hw *hw, u16 num_entries,
 		     bool res_shared, u16 *desc_id, struct ice_sq_cd *cd);
 enum ice_status
 ice_add_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list);
-enum ice_status
-ice_remove_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list);
+enum ice_status ice_remove_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list);
 void ice_rem_all_sw_rules_info(struct ice_hw *hw);
 enum ice_status ice_add_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_lst);
 enum ice_status ice_remove_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_lst);

index cebf1504f1..6967ff1a8f 100644
@@ -3238,8 +3238,8 @@ bool ice_is_100m_speed_supported(struct ice_hw *hw)
  * Note: In the structure of [phy_type_low, phy_type_high], there should
  * be one bit set, as this function will convert one PHY type to its
  * speed.
- * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
- * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
+ * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
+ * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
  */
 static u16
 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)

@@ -6134,6 +6134,42 @@ bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw)
 				     ICE_FW_API_REPORT_DFLT_CFG_PATCH);
 }
 
+/* each of the indexes into the following array match the speed of a return
+ * value from the list of AQ returned speeds like the range:
+ * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding
+ * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) The array is defined as 15
+ * elements long because the link_speed returned by the firmware is a 16 bit
+ * value, but is indexed by [fls(speed) - 1]
+ */
+static const u32 ice_aq_to_link_speed[] = {
+	ICE_LINK_SPEED_10MBPS,	/* BIT(0) */
+	ICE_LINK_SPEED_100MBPS,
+	ICE_LINK_SPEED_1000MBPS,
+	ICE_LINK_SPEED_2500MBPS,
+	ICE_LINK_SPEED_5000MBPS,
+	ICE_LINK_SPEED_10000MBPS,
+	ICE_LINK_SPEED_20000MBPS,
+	ICE_LINK_SPEED_25000MBPS,
+	ICE_LINK_SPEED_40000MBPS,
+	ICE_LINK_SPEED_50000MBPS,
+	ICE_LINK_SPEED_100000MBPS,	/* BIT(10) */
+	ICE_LINK_SPEED_200000MBPS,
+};
+
+/**
+ * ice_get_link_speed - get integer speed from table
+ * @index: array index from fls(aq speed) - 1
+ *
+ * Returns: u32 value containing integer speed
+ */
+u32 ice_get_link_speed(u16 index)
+{
+	if (index >= ARRAY_SIZE(ice_aq_to_link_speed))
+		return ICE_LINK_SPEED_UNKNOWN;
+
+	return ice_aq_to_link_speed[index];
+}
+
 /**
  * ice_fw_supports_fec_dis_auto
  * @hw: pointer to the hardware structure

index 83ef438041..d8fb7a6163 100644
@@ -217,6 +217,7 @@ enum ice_status
 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
 		  u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
 		  bool write, struct ice_sq_cd *cd);
+u32 ice_get_link_speed(u16 index);
 
 enum ice_status
 ice_aq_prog_topo_dev_nvm(struct ice_hw *hw,

index eeaf044059..1d9baea624 100644
@@ -97,6 +97,10 @@ enum ice_sw_tunnel_type {
 	ICE_SW_TUN_IPV6_GTPU_EH_IPV6_UDP,
 	ICE_SW_TUN_IPV6_GTPU_IPV6_TCP,
 	ICE_SW_TUN_IPV6_GTPU_EH_IPV6_TCP,
+	ICE_SW_TUN_IPV4_GTPU_IPV4,
+	ICE_SW_TUN_IPV4_GTPU_IPV6,
+	ICE_SW_TUN_IPV6_GTPU_IPV4,
+	ICE_SW_TUN_IPV6_GTPU_IPV6,
 	ICE_SW_TUN_PPPOE,
 	ICE_SW_TUN_PPPOE_PAY,
 	ICE_SW_TUN_PPPOE_IPV4,

@@ -127,12 +131,6 @@ enum ice_sw_tunnel_type {
 	ICE_SW_TUN_PPPOE_PAY_QINQ,
 	ICE_SW_TUN_PPPOE_IPV4_QINQ,
 	ICE_SW_TUN_PPPOE_IPV6_QINQ,
-	ICE_SW_TUN_IPV4_GTPU_IPV4,
-	ICE_SW_TUN_IPV4_GTPU_IPV6,
-	ICE_SW_TUN_IPV6_GTPU_IPV4,
-	ICE_SW_TUN_IPV6_GTPU_IPV6,
-	ICE_SW_TUN_GTP_IPV4,
-	ICE_SW_TUN_GTP_IPV6,
 	ICE_ALL_TUNNELS /* All tunnel types including NVGRE */
 };
 

@@ -224,6 +222,7 @@ enum ice_prot_id {
 #define ICE_TUN_FLAG_MDID_OFF(word)   (ICE_MDID_SIZE * (ICE_TUN_FLAG_MDID + (word)))
 #define ICE_TUN_FLAG_MASK 0xFF
 #define ICE_DIR_FLAG_MASK 0x10
+#define ICE_TUN_FLAG_IN_VLAN_MASK 0x80 /* VLAN inside tunneled header */
 #define ICE_TUN_FLAG_VLAN_MASK 0x01
 #define ICE_TUN_FLAG_FV_IND 2
 

index b3d9847669..1b8311fdc7 100644
@@ -915,15 +915,6 @@ static const u8 dummy_ipv6_gtpu_ipv6_udp_packet[] = {
 	0x00, 0x00, /* 2 bytes for 4 byte alignment */
 };
 
-static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv4_packet_offsets[] = {
-	{ ICE_MAC_OFOS,		0 },
-	{ ICE_IPV4_OFOS,	14 },
-	{ ICE_UDP_OF,		34 },
-	{ ICE_GTP,		42 },
-	{ ICE_IPV4_IL,		62 },
-	{ ICE_PROTOCOL_LAST,	0 },
-};
-
 static const u8 dummy_ipv4_gtpu_ipv4_packet[] = {
 	0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
 	0x00, 0x00, 0x00, 0x00,

@@ -954,8 +945,17 @@ static const u8 dummy_ipv4_gtpu_ipv4_packet[] = {
 	0x00, 0x00,
 };
 
-static const
-struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv6_packet_offsets[] = {
+static const struct
+ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv4_packet_offsets[] = {
+	{ ICE_MAC_OFOS,		0 },
+	{ ICE_IPV4_OFOS,	14 },
+	{ ICE_UDP_OF,		34 },
+	{ ICE_GTP,		42 },
+	{ ICE_IPV4_IL,		62 },
+	{ ICE_PROTOCOL_LAST,	0 },
+};
+
+static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv6_packet_offsets[] = {
 	{ ICE_MAC_OFOS,		0 },
 	{ ICE_IPV4_OFOS,	14 },
 	{ ICE_UDP_OF,		34 },

@@ -7532,7 +7532,8 @@ static bool ice_tun_type_match_word(enum ice_sw_tunnel_type tun_type, u16 *off,
 
 	case ICE_SW_TUN_GENEVE_VLAN:
 	case ICE_SW_TUN_VXLAN_VLAN:
-		*mask = ICE_TUN_FLAG_MASK & ~ICE_TUN_FLAG_VLAN_MASK;
+		*mask = ICE_TUN_FLAG_MASK & ~(ICE_TUN_FLAG_VLAN_MASK |
+			ICE_TUN_FLAG_IN_VLAN_MASK);
 		*off = ICE_TUN_FLAG_MDID_OFF(1);
 		return true;
 

index ec4892179a..5779590a7e 100644
@@ -43,6 +43,24 @@ static inline int ice_ilog2(u64 n)
 	return -1;
 }
 
+/**
+ * ice_fls - find the most significant bit set in a u64
+ * @n: u64 value to scan for a bit
+ *
+ * Returns: 0 if no bits found, otherwise the index of the highest bit that was
+ * set, like ice_fls(0x20) == 6. This means this is returning a *1 based*
+ * count, and that the maximum largest value returned is 64!
+ */
+static inline unsigned int ice_fls(u64 n)
+{
+	int ret;
+
+	ret = ice_ilog2(n);
+
+	/* add one to turn to the ilog2 value into a 1 based index */
+	return ret >= 0 ? ret + 1 : 0;
+}
+
 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
 {
 	return ice_is_bit_set(&bitmap, tc);

index 6967ff1a8f..58da198d62 100644
@@ -9,7 +9,7 @@
 #include "ice_flow.h"
 #include "ice_switch.h"
 
-#define ICE_PF_RESET_WAIT_COUNT	300
+#define ICE_PF_RESET_WAIT_COUNT	500
 
 static const char * const ice_link_mode_str_low[] = {
 	ice_arr_elem_idx(0, "100BASE_TX"),

@@ -249,6 +249,12 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw)
 	case ICE_DEV_ID_E825X:
 		hw->mac_type = ICE_MAC_GENERIC;
 		break;
+	case ICE_DEV_ID_E830_BACKPLANE:
+	case ICE_DEV_ID_E830_QSFP56:
+	case ICE_DEV_ID_E830_SFP:
+	case ICE_DEV_ID_E830_SFP_DD:
+		hw->mac_type = ICE_MAC_E830;
+		break;
 	default:
 		hw->mac_type = ICE_MAC_UNKNOWN;
 		break;

index ae0a03c8ba..e3c1f413dd 100644
@@ -439,6 +439,9 @@ static u32 ice_get_pkg_segment_id(enum ice_mac_type mac_type)
 	u32 seg_id;
 
 	switch (mac_type) {
+	case ICE_MAC_E830:
+		seg_id = SEGMENT_TYPE_ICE_E830;
+		break;
 	case ICE_MAC_GENERIC:
 	case ICE_MAC_GENERIC_3K:
 	default:

@@ -458,6 +461,9 @@ static u32 ice_get_pkg_sign_type(enum ice_mac_type mac_type)
 	u32 sign_type;
 
 	switch (mac_type) {
+	case ICE_MAC_E830:
+		sign_type = SEGMENT_SIGN_TYPE_RSA3K_SBB;
+		break;
 	case ICE_MAC_GENERIC_3K:
 		sign_type = SEGMENT_SIGN_TYPE_RSA3K;
 		break;

index 4896e85b91..57b39c72ca 100644
@@ -106,6 +106,7 @@ struct ice_generic_seg_hdr {
 #define SEGMENT_TYPE_METADATA	0x00000001
 #define SEGMENT_TYPE_ICE_E810	0x00000010
 #define SEGMENT_TYPE_SIGNING	0x00001001
+#define SEGMENT_TYPE_ICE_E830	0x00000017
 #define SEGMENT_TYPE_ICE_RUN_TIME_CFG 0x00000020
 	__le32 seg_type;
 	struct ice_pkg_ver seg_format_ver;

index f80789ebc5..9ea915b967 100644
@@ -15,6 +15,14 @@
 #define ICE_DEV_ID_E823L_1GBE		0x124F
 /* Intel(R) Ethernet Connection E823-L for QSFP */
 #define ICE_DEV_ID_E823L_QSFP		0x151D
+/* Intel(R) Ethernet Controller E830-C for backplane */
+#define ICE_DEV_ID_E830_BACKPLANE	0x12D1
+/* Intel(R) Ethernet Controller E830-C for QSFP */
+#define ICE_DEV_ID_E830_QSFP56		0x12D2
+/* Intel(R) Ethernet Controller E830-C for SFP */
+#define ICE_DEV_ID_E830_SFP		0x12D3
+/* Intel(R) Ethernet Controller E830-C for SFP-DD */
+#define ICE_DEV_ID_E830_SFP_DD		0x12D4
 /* Intel(R) Ethernet Controller E810-C for backplane */
 #define ICE_DEV_ID_E810C_BACKPLANE	0x1591
 /* Intel(R) Ethernet Controller E810-C for QSFP */

1,645 lines not on this page · raw message

index 229db1041c..d8ac841e46 100644
@@ -2469,5 +2469,5 @@ static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype)
 #define ICE_LINK_SPEED_40000MBPS	40000
 #define ICE_LINK_SPEED_50000MBPS	50000
 #define ICE_LINK_SPEED_100000MBPS	100000
-
+#define ICE_LINK_SPEED_200000MBPS	200000
 #endif /* _ICE_LAN_TX_RX_H_ */

index cb45cb8134..6ab359af33 100644
@@ -1330,14 +1330,17 @@ ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
 		return status;
 
 	/* Reject requests to write to read-only registers */
-	switch (cmd->offset) {
-	case GL_HICR_EN:
-	case GLGEN_RSTAT:
-		return ICE_ERR_OUT_OF_RANGE;
-	default:
-		break;
+	if (hw->mac_type == ICE_MAC_E830) {
+		if (cmd->offset == E830_GL_HICR_EN)
+			return ICE_ERR_OUT_OF_RANGE;
+	} else {
+		if (cmd->offset == GL_HICR_EN)
+			return ICE_ERR_OUT_OF_RANGE;
 	}
 
+	if (cmd->offset == GLGEN_RSTAT)
+		return ICE_ERR_OUT_OF_RANGE;
+
 	ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n",
 		  cmd->offset, data->regval);
 

index 5779590a7e..576998549e 100644
@@ -222,6 +222,7 @@ enum ice_set_fc_aq_failures {
 enum ice_mac_type {
 	ICE_MAC_UNKNOWN = 0,
 	ICE_MAC_E810,
+	ICE_MAC_E830,
 	ICE_MAC_GENERIC,
 	ICE_MAC_GENERIC_3K,
 };

index 58da198d62..ed822afc30 100644
@@ -1397,6 +1397,37 @@ ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
 	return ICE_SUCCESS;
 }
 
+/**
+ * ice_copy_rxq_ctx_from_hw - Copy rxq context register from HW
+ * @hw: pointer to the hardware structure
+ * @ice_rxq_ctx: pointer to the rxq context
+ * @rxq_index: the index of the Rx queue
+ *
+ * Copies rxq context from HW register space to dense structure
+ */
+static enum ice_status
+ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
+{
+	u8 i;
+
+	if (!ice_rxq_ctx)
+		return ICE_ERR_BAD_PTR;
+
+	if (rxq_index > QRX_CTRL_MAX_INDEX)
+		return ICE_ERR_PARAM;
+
+	/* Copy each dword separately from HW */
+	for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
+		u32 *ctx = (u32 *)(ice_rxq_ctx + (i * sizeof(u32)));
+
+		*ctx = rd32(hw, QRX_CONTEXT(i, rxq_index));
+
+		ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx);
+	}
+
+	return ICE_SUCCESS;
+}
+
 /* LAN Rx Queue Context */
 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
 	/* Field		Width	LSB */

@@ -1448,6 +1479,32 @@ ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
 	return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
 }
 
+/**
+ * ice_read_rxq_ctx - Read rxq context from HW
+ * @hw: pointer to the hardware structure
+ * @rlan_ctx: pointer to the rxq context
+ * @rxq_index: the index of the Rx queue
+ *
+ * Read rxq context from HW register space and then converts it from dense
+ * structure to sparse
+ */
+enum ice_status
+ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
+		 u32 rxq_index)
+{
+	u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
+	enum ice_status status;
+
+	if (!rlan_ctx)
+		return ICE_ERR_BAD_PTR;
+
+	status = ice_copy_rxq_ctx_from_hw(hw, ctx_buf, rxq_index);
+	if (status)
+		return status;
+
+	return ice_get_ctx(ctx_buf, (u8 *)rlan_ctx, ice_rlan_ctx_info);
+}
+
 /**
  * ice_clear_rxq_ctx
  * @hw: pointer to the hardware structure

@@ -4883,7 +4940,7 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
  * @ce_info:  a description of the struct to be filled
  */
 static void
-ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
+ice_read_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
 {
 	u8 dest_byte, mask;
 	u8 *src, *target;

@@ -4901,7 +4958,7 @@ ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
 
 	ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
 
-	dest_byte &= ~(mask);
+	dest_byte &= mask;
 
 	dest_byte >>= shift_width;
 

@@ -4919,7 +4976,7 @@ ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
  * @ce_info:  a description of the struct to be filled
  */
 static void
-ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
+ice_read_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
 {
 	u16 dest_word, mask;
 	u8 *src, *target;

@@ -4941,7 +4998,7 @@ ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
 	/* the data in the memory is stored as little endian so mask it
 	 * correctly
 	 */
-	src_word &= ~(CPU_TO_LE16(mask));
+	src_word &= CPU_TO_LE16(mask);
 
 	/* get the data back into host order before shifting */
 	dest_word = LE16_TO_CPU(src_word);

@@ -4962,7 +5019,7 @@ ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
  * @ce_info:  a description of the struct to be filled
  */
 static void
-ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
+ice_read_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
 {
 	u32 dest_dword, mask;
 	__le32 src_dword;

@@ -4992,7 +5049,7 @@ ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
 	/* the data in the memory is stored as little endian so mask it
 	 * correctly
 	 */
-	src_dword &= ~(CPU_TO_LE32(mask));
+	src_dword &= CPU_TO_LE32(mask);
 
 	/* get the data back into host order before shifting */
 	dest_dword = LE32_TO_CPU(src_dword);

@@ -5013,7 +5070,7 @@ ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
  * @ce_info:  a description of the struct to be filled
  */
 static void
-ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
+ice_read_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
 {
 	u64 dest_qword, mask;
 	__le64 src_qword;

@@ -5043,7 +5100,7 @@ ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
 	/* the data in the memory is stored as little endian so mask it
 	 * correctly
 	 */
-	src_qword &= ~(CPU_TO_LE64(mask));
+	src_qword &= CPU_TO_LE64(mask);
 
 	/* get the data back into host order before shifting */
 	dest_qword = LE64_TO_CPU(src_qword);

@@ -5064,7 +5121,7 @@ ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
  * @ce_info:  a description of the structure to be read from
  */
 enum ice_status
-ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
+ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
 {
 	int f;
 

index d8fb7a6163..3e03f2e903 100644
@@ -92,6 +92,9 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
 enum ice_status
 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
 		  u32 rxq_index);
+enum ice_status
+ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
+		 u32 rxq_index);
 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index);
 enum ice_status
 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index);

@@ -135,6 +138,8 @@ extern const struct ice_ctx_ele ice_tlan_ctx_info[];
 enum ice_status
 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
 	    const struct ice_ctx_ele *ce_info);
+enum ice_status
+ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info);
 
 enum ice_status
 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,

@@ -229,8 +234,6 @@ ice_aq_read_topo_dev_nvm(struct ice_hw *hw,
 			 u32 start_address, u8 *buf, u8 buf_size,
 			 struct ice_sq_cd *cd);
 
-enum ice_status
-ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);
 enum ice_status
 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
 		u16 *q_handle, u16 *q_ids, u32 *q_teids,

index 548ef5e820..61145262ac 100644
@@ -448,1375 +448,6 @@ static void ice_ptp_clean_cmd(struct ice_hw *hw)
 	ice_flush(hw);
 }
 
-/* 56G PHY access functions */
-static const u32 eth56g_port_base[ICE_NUM_PHY_PORTS] = {
-	ICE_PHY0_BASE,
-	ICE_PHY1_BASE,
-	ICE_PHY2_BASE,
-	ICE_PHY3_BASE,
-	ICE_PHY4_BASE,
-};
-
-/**
- * ice_write_phy_eth56g_raw_lp - Write a PHY port register with lock parameter
- * @hw: pointer to the HW struct
- * @reg_addr: PHY register address
- * @val: Value to write
- * @lock_sbq: true to lock the sideband queue
- */
-static enum ice_status
-ice_write_phy_eth56g_raw_lp(struct ice_hw *hw,  u32 reg_addr, u32 val,
-			    bool lock_sbq)
-{
-	struct ice_sbq_msg_input phy_msg;
-	enum ice_status status;
-
-	phy_msg.opcode = ice_sbq_msg_wr;
-
-	phy_msg.msg_addr_low = ICE_LO_WORD(reg_addr);
-	phy_msg.msg_addr_high = ICE_HI_WORD(reg_addr);
-
-	phy_msg.data = val;
-	phy_msg.dest_dev = phy_56g;
-
-	status = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);
-
-	if (status)
-		ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
-			  status);
-
-	return status;
-}
-
-/**
- * ice_read_phy_eth56g_raw_lp - Read a PHY port register with lock parameter
- * @hw: pointer to the HW struct
- * @reg_addr: PHY port register address
- * @val: Pointer to the value to read (out param)
- * @lock_sbq: true to lock the sideband queue
- */
-static enum ice_status
-ice_read_phy_eth56g_raw_lp(struct ice_hw *hw, u32 reg_addr, u32 *val,
-			   bool lock_sbq)
-{
-	struct ice_sbq_msg_input phy_msg;
-	enum ice_status status;
-
-	phy_msg.opcode = ice_sbq_msg_rd;
-
-	phy_msg.msg_addr_low = ICE_LO_WORD(reg_addr);
-	phy_msg.msg_addr_high = ICE_HI_WORD(reg_addr);
-
-	phy_msg.dest_dev = phy_56g;
-
-	status = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);
-
-	if (status)
-		ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
-			  status);
-	else
-		*val = phy_msg.data;
-
-	return status;
-}
-
-/**
- * ice_phy_port_reg_address_eth56g - Calculate a PHY port register address
- * @port: Port number to be written
- * @offset: Offset from PHY port register base
- * @address: The result address
- */
-static enum ice_status
-ice_phy_port_reg_address_eth56g(u8 port, u16 offset, u32 *address)
-{
-	u8 phy, lane;
-
-	if (port >= ICE_NUM_EXTERNAL_PORTS)
-		return ICE_ERR_OUT_OF_RANGE;
-
-	phy = port / ICE_PORTS_PER_QUAD;
-	lane = port % ICE_PORTS_PER_QUAD;
-
-	*address = offset + eth56g_port_base[phy] +
-		   PHY_PTP_LANE_ADDR_STEP * lane;
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_phy_port_mem_address_eth56g - Calculate a PHY port memory address
- * @port: Port number to be written
- * @offset: Offset from PHY port register base
- * @address: The result address
- */
-static enum ice_status
-ice_phy_port_mem_address_eth56g(u8 port, u16 offset, u32 *address)
-{
-	u8 phy, lane;
-
-	if (port >= ICE_NUM_EXTERNAL_PORTS)
-		return ICE_ERR_OUT_OF_RANGE;
-
-	phy = port / ICE_PORTS_PER_QUAD;
-	lane = port % ICE_PORTS_PER_QUAD;
-
-	*address = offset + eth56g_port_base[phy] +
-		   PHY_PTP_MEM_START + PHY_PTP_MEM_LANE_STEP * lane;
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_write_phy_reg_eth56g_lp - Write a PHY port register with lock parameter
- * @hw: pointer to the HW struct
- * @port: Port number to be written
- * @offset: Offset from PHY port register base
- * @val: Value to write
- * @lock_sbq: true to lock the sideband queue
- */
-static enum ice_status
-ice_write_phy_reg_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset, u32 val,
-			    bool lock_sbq)
-{
-	enum ice_status status;
-	u32 reg_addr;
-
-	status = ice_phy_port_reg_address_eth56g(port, offset, &reg_addr);
-	if (status)
-		return status;
-
-	return ice_write_phy_eth56g_raw_lp(hw, reg_addr, val, lock_sbq);
-}
-
-/**
- * ice_write_phy_reg_eth56g - Write a PHY port register with sbq locked
- * @hw: pointer to the HW struct
- * @port: Port number to be written
- * @offset: Offset from PHY port register base
- * @val: Value to write
- */
-enum ice_status
-ice_write_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val)
-{
-	return ice_write_phy_reg_eth56g_lp(hw, port, offset, val, true);
-}
-
-/**
- * ice_read_phy_reg_eth56g_lp - Read a PHY port register with
- * lock parameter
- * @hw: pointer to the HW struct
- * @port: Port number to be read
- * @offset: Offset from PHY port register base
- * @val: Pointer to the value to read (out param)
- * @lock_sbq: true to lock the sideband queue
- */
-static enum ice_status
-ice_read_phy_reg_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset, u32 *val,
-			   bool lock_sbq)
-{
-	enum ice_status status;
-	u32 reg_addr;
-
-	status = ice_phy_port_reg_address_eth56g(port, offset, &reg_addr);
-	if (status)
-		return status;
-
-	return ice_read_phy_eth56g_raw_lp(hw, reg_addr, val, lock_sbq);
-}
-
-/**
- * ice_read_phy_reg_eth56g - Read a PHY port register with sbq locked
- * @hw: pointer to the HW struct
- * @port: Port number to be read
- * @offset: Offset from PHY port register base
- * @val: Pointer to the value to read (out param)
- */
-enum ice_status
-ice_read_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
-{
-	return ice_read_phy_reg_eth56g_lp(hw, port, offset, val, true);
-}
-
-/**
- * ice_phy_port_mem_read_eth56g_lp - Read a PHY port memory location
- * with lock parameter
- * @hw: pointer to the HW struct
- * @port: Port number to be read
- * @offset: Offset from PHY port register base
- * @val: Pointer to the value to read (out param)
- * @lock_sbq: true to lock the sideband queue
- */
-static enum ice_status
-ice_phy_port_mem_read_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset,
-				u32 *val, bool lock_sbq)
-{
-	enum ice_status status;
-	u32 mem_addr;
-
-	status = ice_phy_port_mem_address_eth56g(port, offset, &mem_addr);
-	if (status)
-		return status;
-
-	return ice_read_phy_eth56g_raw_lp(hw, mem_addr, val, lock_sbq);
-}
-
-/**
- * ice_phy_port_mem_read_eth56g - Read a PHY port memory location with
- * sbq locked
- * @hw: pointer to the HW struct
- * @port: Port number to be read
- * @offset: Offset from PHY port register base
- * @val: Pointer to the value to read (out param)
- */
-static enum ice_status
-ice_phy_port_mem_read_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
-{
-	return ice_phy_port_mem_read_eth56g_lp(hw, port, offset, val, true);
-}
-
-/**
- * ice_phy_port_mem_write_eth56g_lp - Write a PHY port memory location with
- * lock parameter
- * @hw: pointer to the HW struct
- * @port: Port number to be read
- * @offset: Offset from PHY port register base
- * @val: Pointer to the value to read (out param)
- * @lock_sbq: true to lock the sideband queue
- */
-static enum ice_status
-ice_phy_port_mem_write_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset,
-				 u32 val, bool lock_sbq)
-{
-	enum ice_status status;
-	u32 mem_addr;
-
-	status = ice_phy_port_mem_address_eth56g(port, offset, &mem_addr);
-	if (status)
-		return status;
-
-	return ice_write_phy_eth56g_raw_lp(hw, mem_addr, val, lock_sbq);
-}
-
-/**
- * ice_phy_port_mem_write_eth56g - Write a PHY port memory location with
- * sbq locked
- * @hw: pointer to the HW struct
- * @port: Port number to be read
- * @offset: Offset from PHY port register base
- * @val: Pointer to the value to read (out param)
- */
-static enum ice_status
-ice_phy_port_mem_write_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val)
-{
-	return ice_phy_port_mem_write_eth56g_lp(hw, port, offset, val, true);
-}
-
-/**
- * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register
- * @low_addr: the low address to check
- *
- * Checks if the provided low address is one of the known 64bit PHY values
- * represented as two 32bit registers.
- */
-static bool ice_is_64b_phy_reg_eth56g(u16 low_addr)
-{
-	switch (low_addr) {
-	case PHY_REG_TX_TIMER_INC_PRE_L:
-	case PHY_REG_RX_TIMER_INC_PRE_L:
-	case PHY_REG_TX_CAPTURE_L:
-	case PHY_REG_RX_CAPTURE_L:
-	case PHY_REG_TOTAL_TX_OFFSET_L:
-	case PHY_REG_TOTAL_RX_OFFSET_L:
-		return true;
-	default:
-		return false;
-	}
-}
-
-/**
- * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register
- * @low_addr: the low address to check
- *
- * Checks if the provided low address is one of the known 40bit PHY values
- * split into two registers with the lower 8 bits in the low register and the
- * upper 32 bits in the high register.
- */
-static bool ice_is_40b_phy_reg_eth56g(u16 low_addr)
-{
-	switch (low_addr) {
-	case PHY_REG_TIMETUS_L:
-		return true;
-	default:
-		return false;
-	}
-}
-
-/**
- * ice_read_40b_phy_reg_eth56g - Read a 40bit value from PHY registers
- * @hw: pointer to the HW struct
- * @port: PHY port to read from
- * @low_addr: offset of the lower register to read from
- * @val: on return, the contents of the 40bit value from the PHY registers
- *
- * Reads the two registers associated with a 40bit value and returns it in the
- * val pointer.
- * This function checks that the caller has specified a known 40 bit register
- * offset
- */
-static enum ice_status
-ice_read_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
-{
-	u16 high_addr = low_addr + sizeof(u32);
-	enum ice_status status;
-	u32 lo, hi;
-
-	if (!ice_is_40b_phy_reg_eth56g(low_addr))
-		return ICE_ERR_PARAM;
-
-	status = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, status %d",
-			  (int)low_addr, status);
-		return status;
-	}
-
-	status = ice_read_phy_reg_eth56g(hw, port, low_addr + sizeof(u32), &hi);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %08x\n, status %d",
-			  high_addr, status);
-		return status;
-	}
-
-	*val = ((u64)hi << P_REG_40B_HIGH_S) | (lo & P_REG_40B_LOW_M);
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers
- * @hw: pointer to the HW struct
- * @port: PHY port to read from
- * @low_addr: offset of the lower register to read from
- * @val: on return, the contents of the 64bit value from the PHY registers
- *
- * Reads the two registers associated with a 64bit value and returns it in the
- * val pointer.
- * This function checks that the caller has specified a known 64 bit register
- * offset
- */
-static enum ice_status
-ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
-{
-	u16 high_addr = low_addr + sizeof(u32);
-	enum ice_status status;
-	u32 lo, hi;
-
-	if (!ice_is_64b_phy_reg_eth56g(low_addr))
-		return ICE_ERR_PARAM;
-
-	status = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, status %d",
-			  low_addr, status);
-		return status;
-	}
-
-	status = ice_read_phy_reg_eth56g(hw, port, high_addr, &hi);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, status %d",
-			  high_addr, status);
-		return status;
-	}
-
-	*val = ((u64)hi << 32) | lo;
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY
- * @hw: pointer to the HW struct
- * @port: port to write to
- * @low_addr: offset of the low register
- * @val: 40b value to write
- *
- * Write the provided 40b value to the two associated registers by splitting
- * it up into two chunks, the lower 8 bits and the upper 32 bits.
- * This function checks that the caller has specified a known 40 bit register
- * offset
- */
-static enum ice_status
-ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
-{
-	u16 high_addr = low_addr + sizeof(u32);
-	enum ice_status status;
-	u32 lo, hi;
-
-	if (!ice_is_40b_phy_reg_eth56g(low_addr))
-		return ICE_ERR_PARAM;
-
-	lo = (u32)(val & P_REG_40B_LOW_M);
-	hi = (u32)(val >> P_REG_40B_HIGH_S);
-
-	status = ice_write_phy_reg_eth56g(hw, port, low_addr, lo);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
-			  low_addr, status);
-		return status;
-	}
-
-	status = ice_write_phy_reg_eth56g(hw, port, high_addr, hi);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
-			  high_addr, status);
-		return status;
-	}
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers
- * @hw: pointer to the HW struct
- * @port: PHY port to read from
- * @low_addr: offset of the lower register to read from
- * @val: the contents of the 64bit value to write to PHY
- *
- * Write the 64bit value to the two associated 32bit PHY registers.
- * This function checks that the caller has specified a known 64 bit register
- * offset
- */
-static enum ice_status
-ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
-{
-	u16 high_addr = low_addr + sizeof(u32);
-	enum ice_status status;
-	u32 lo, hi;
-
-	if (!ice_is_64b_phy_reg_eth56g(low_addr))
-		return ICE_ERR_PARAM;
-
-	lo = ICE_LO_DWORD(val);
-	hi = ICE_HI_DWORD(val);
-
-	status = ice_write_phy_reg_eth56g(hw, port, low_addr, lo);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
-			  low_addr, status);
-		return status;
-	}
-
-	status = ice_write_phy_reg_eth56g(hw, port, high_addr, hi);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
-			  high_addr, status);
-		return status;
-	}
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_read_phy_tstamp_eth56g - Read a PHY timestamp out of the port memory
- * @hw: pointer to the HW struct
- * @port: the port to read from
- * @idx: the timestamp index to read
- * @tstamp: on return, the 40bit timestamp value
- *
- * Read a 40bit timestamp value out of the two associated entries in the
- * port memory block of the internal PHYs of the 56G devices.
- */
-static enum ice_status
-ice_read_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, u64 *tstamp)
-{
-	enum ice_status status;
-	u16 lo_addr, hi_addr;
-	u32 lo, hi;
-
-	lo_addr = (u16)PHY_TSTAMP_L(idx);
-	hi_addr = (u16)PHY_TSTAMP_U(idx);
-
-	status = ice_phy_port_mem_read_eth56g(hw, port, lo_addr, &lo);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, status %d\n",
-			  status);
-		return status;
-	}
-
-	status = ice_phy_port_mem_read_eth56g(hw, port, hi_addr, &hi);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, status %d\n",
-			  status);
-		return status;
-	}
-
-	/* For 56G based internal PHYs, the timestamp is reported with the
-	 * lower 8 bits in the low register, and the upper 32 bits in the high
-	 * register.
-	 */
-	*tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M);
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_clear_phy_tstamp_eth56g - Clear a timestamp from the quad block
- * @hw: pointer to the HW struct
- * @port: the quad to read from
- * @idx: the timestamp index to reset
- *
- * Clear a timestamp, resetting its valid bit, in the PHY port memory of
- * internal PHYs of the 56G devices.
- */
-static enum ice_status
-ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx)
-{
-	enum ice_status status;
-	u16 lo_addr;
-
-	lo_addr = (u16)PHY_TSTAMP_L(idx);
-
-	status = ice_phy_port_mem_write_eth56g(hw, port, lo_addr, 0);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n",
-			  status);
-		return status;
-	}
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_prep_port_phy_time_eth56g - Prepare one PHY port with initial time
- * @hw: pointer to the HW struct
- * @port: port number
- * @phy_time: time to initialize the PHY port clocks to
- *
- * Write a new initial time value into registers of a specific PHY port.
- */
-static enum ice_status
-ice_ptp_prep_port_phy_time_eth56g(struct ice_hw *hw, u8 port, u64 phy_time)
-{
-	enum ice_status status;
-
-	/* Tx case */
-	status = ice_write_64b_phy_reg_eth56g(hw, port,
-					      PHY_REG_TX_TIMER_INC_PRE_L,
-					      phy_time);
-	if (status)
-		return status;
-
-	/* Rx case */
-	return ice_write_64b_phy_reg_eth56g(hw, port,
-					    PHY_REG_RX_TIMER_INC_PRE_L,
-					    phy_time);
-}
-
-/**
- * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time
- * @hw: pointer to the HW struct
- * @time: Time to initialize the PHY port clocks to
- *
- * Program the PHY port registers with a new initial time value. The port
- * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync
- * command. The time value is the upper 32 bits of the PHY timer, usually in
- * units of nominal nanoseconds.
- */
-static enum ice_status
-ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time)
-{
-	enum ice_status status;
-	u64 phy_time;
-	u8 port;
-
-	/* The time represents the upper 32 bits of the PHY timer, so we need
-	 * to shift to account for this when programming.
-	 */
-	phy_time = (u64)time << 32;
-
-	for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
-		if (!(hw->ena_lports & BIT(port)))
-			continue;
-		status = ice_ptp_prep_port_phy_time_eth56g(hw, port,
-							   phy_time);
-
-		if (status) {
-			ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, status %d\n",
-				  port, status);
-			return status;
-		}
-	}
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust
- * @hw: pointer to HW struct
- * @port: Port number to be programmed
- * @time: time in cycles to adjust the port Tx and Rx clocks
- * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the
- *            sq_lock has already been locked at a higher level
- *
- * Program the port for an atomic adjustment by writing the Tx and Rx timer
- * registers. The atomic adjustment won't be completed until the driver issues
- * an ICE_PTP_ADJ_TIME command.
- *
- * Note that time is not in units of nanoseconds. It is in clock time
- * including the lower sub-nanosecond portion of the port timer.
- *
- * Negative adjustments are supported using 2s complement arithmetic.
- */
-enum ice_status
-ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time,
-			     bool lock_sbq)
-{
-	enum ice_status status;
-	u32 l_time, u_time;
-
-	l_time = ICE_LO_DWORD(time);
-	u_time = ICE_HI_DWORD(time);
-
-	/* Tx case */
-	status = ice_write_phy_reg_eth56g_lp(hw, port,
-					     PHY_REG_TX_TIMER_INC_PRE_L,
-					     l_time, lock_sbq);
-	if (status)
-		goto exit_err;
-
-	status = ice_write_phy_reg_eth56g_lp(hw, port,
-					     PHY_REG_TX_TIMER_INC_PRE_U,
-					     u_time, lock_sbq);
-	if (status)
-		goto exit_err;
-
-	/* Rx case */
-	status = ice_write_phy_reg_eth56g_lp(hw, port,
-					     PHY_REG_RX_TIMER_INC_PRE_L,
-					     l_time, lock_sbq);
-	if (status)
-		goto exit_err;
-
-	status = ice_write_phy_reg_eth56g_lp(hw, port,
-					     PHY_REG_RX_TIMER_INC_PRE_U,
-					     u_time, lock_sbq);
-	if (status)
-		goto exit_err;
-
-	return ICE_SUCCESS;
-
-exit_err:
-	ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, status %d\n",
-		  port, status);
-	return status;
-}
-
-/**
- * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment
- * @hw: pointer to HW struct
- * @adj: adjustment in nanoseconds
- * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the
- *            sq_lock has already been locked at a higher level
- *
- * Prepare the PHY ports for an atomic time adjustment by programming the PHY
- * Tx and Rx port registers. The actual adjustment is completed by issuing an
- * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.
- */
-static enum ice_status
-ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj, bool lock_sbq)
-{
-	enum ice_status status = ICE_SUCCESS;
-	s64 cycles;
-	u8 port;
-
-	/* The port clock supports adjustment of the sub-nanosecond portion of
-	 * the clock. We shift the provided adjustment in nanoseconds to
-	 * calculate the appropriate adjustment to program into the PHY ports.
-	 */
-	cycles = (s64)adj << 32;
-
-	for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
-		if (!(hw->ena_lports & BIT(port)))
-			continue;
-
-		status = ice_ptp_prep_port_adj_eth56g(hw, port, cycles,
-						      lock_sbq);
-		if (status)
-			break;
-	}
-
-	return status;
-}
-
-/**
- * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment
- * @hw: pointer to HW struct
- * @incval: new increment value to prepare
- *
- * Prepare each of the PHY ports for a new increment value by programming the
- * port's TIMETUS registers. The new increment value will be updated after
- * issuing an ICE_PTP_INIT_INCVAL command.
- */
-static enum ice_status
-ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval)
-{
-	enum ice_status status;
-	u8 port;
-
-	for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
-		if (!(hw->ena_lports & BIT(port)))
-			continue;
-		status = ice_write_40b_phy_reg_eth56g(hw, port,
-						      PHY_REG_TIMETUS_L,
-						      incval);
-		if (status) {
-			ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, status %d\n",
-				  port, status);
-			return status;
-		}
-	}
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_read_phy_incval_eth56g - Read a PHY port's current incval
- * @hw: pointer to the HW struct
- * @port: the port to read
- * @incval: on return, the time_clk_cyc incval for this port
- *
- * Read the time_clk_cyc increment value for a given PHY port.
- */
-enum ice_status
-ice_ptp_read_phy_incval_eth56g(struct ice_hw *hw, u8 port, u64 *incval)
-{
-	enum ice_status status;
-
-	status = ice_read_40b_phy_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
-					     incval);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to read TIMETUS_L, status %d\n",
-			  status);
-		return status;
-	}
-
-	ice_debug(hw, ICE_DBG_PTP, "read INCVAL = 0x%016llx\n",
-		  (unsigned long long)*incval);
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_prep_phy_adj_target_eth56g - Prepare PHY for adjust at target time
- * @hw: pointer to HW struct
- * @target_time: target time to program
- *
- * Program the PHY port Tx and Rx TIMER_CNT_ADJ registers used for the
- * ICE_PTP_ADJ_TIME_AT_TIME command. This should be used in conjunction with
- * ice_ptp_prep_phy_adj_eth56g to program an atomic adjustment that is
- * delayed until a specified target time.
- *
- * Note that a target time adjustment is not currently supported on E810
- * devices.
- */
-static enum ice_status
-ice_ptp_prep_phy_adj_target_eth56g(struct ice_hw *hw, u32 target_time)
-{
-	enum ice_status status;
-	u8 port;
-
-	for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
-		if (!(hw->ena_lports & BIT(port)))
-			continue;
-
-		/* Tx case */
-		/* No sub-nanoseconds data */
-		status = ice_write_phy_reg_eth56g_lp(hw, port,
-						     PHY_REG_TX_TIMER_CNT_ADJ_L,
-						     0, true);
-		if (status)
-			goto exit_err;
-
-		status = ice_write_phy_reg_eth56g_lp(hw, port,
-						     PHY_REG_TX_TIMER_CNT_ADJ_U,
-						     target_time, true);
-		if (status)
-			goto exit_err;
-
-		/* Rx case */
-		/* No sub-nanoseconds data */
-		status = ice_write_phy_reg_eth56g_lp(hw, port,
-						     PHY_REG_RX_TIMER_CNT_ADJ_L,
-						     0, true);
-		if (status)
-			goto exit_err;
-
-		status = ice_write_phy_reg_eth56g_lp(hw, port,
-						     PHY_REG_RX_TIMER_CNT_ADJ_U,
-						     target_time, true);
-		if (status)
-			goto exit_err;
-	}
-
-	return ICE_SUCCESS;
-
-exit_err:
-	ice_debug(hw, ICE_DBG_PTP, "Failed to write target time for port %u, status %d\n",
-		  port, status);
-
-	return status;
-}
-
-/**
- * ice_ptp_read_port_capture_eth56g - Read a port's local time capture
- * @hw: pointer to HW struct
- * @port: Port number to read
- * @tx_ts: on return, the Tx port time capture
- * @rx_ts: on return, the Rx port time capture
- *
- * Read the port's Tx and Rx local time capture values.
- */
-enum ice_status
-ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, u64 *tx_ts,
-				 u64 *rx_ts)
-{
-	enum ice_status status;
-
-	/* Tx case */
-	status = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L,
-					     tx_ts);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, status %d\n",
-			  status);
-		return status;
-	}
-
-	ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n",
-		  (unsigned long long)*tx_ts);
-
-	/* Rx case */
-	status = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L,
-					     rx_ts);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, status %d\n",
-			  status);
-		return status;
-	}
-
-	ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n",
-		  (unsigned long long)*rx_ts);
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_one_port_cmd_eth56g - Prepare a single PHY port for a timer command
- * @hw: pointer to HW struct
- * @port: Port to which cmd has to be sent
- * @cmd: Command to be sent to the port
- * @lock_sbq: true if the sideband queue lock must be acquired
- *
- * Prepare the requested port for an upcoming timer sync command.
- */
-enum ice_status
-ice_ptp_one_port_cmd_eth56g(struct ice_hw *hw, u8 port,
-			    enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
-{
-	enum ice_status status;
-	u32 cmd_val, val;
-	u8 tmr_idx;
-
-	tmr_idx = ice_get_ptp_src_clock_index(hw);
-	cmd_val = tmr_idx << SEL_PHY_SRC;
-	switch (cmd) {
-	case ICE_PTP_INIT_TIME:
-		cmd_val |= PHY_CMD_INIT_TIME;
-		break;
-	case ICE_PTP_INIT_INCVAL:
-		cmd_val |= PHY_CMD_INIT_INCVAL;
-		break;
-	case ICE_PTP_ADJ_TIME:
-		cmd_val |= PHY_CMD_ADJ_TIME;
-		break;
-	case ICE_PTP_ADJ_TIME_AT_TIME:
-		cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME;
-		break;
-	case ICE_PTP_READ_TIME:
-		cmd_val |= PHY_CMD_READ_TIME;
-		break;
-	default:
-		ice_warn(hw, "Unknown timer command %u\n", cmd);
-		return ICE_ERR_PARAM;
-	}
-
-	/* Tx case */
-	/* Read, modify, write */
-	status = ice_read_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TMR_CMD, &val,
-					    lock_sbq);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, status %d\n",
-			  status);
-		return status;
-	}
-
-	/* Modify necessary bits only and perform write */
-	val &= ~TS_CMD_MASK;
-	val |= cmd_val;
-
-	status = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TMR_CMD, val,
-					     lock_sbq);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, status %d\n",
-			  status);
-		return status;
-	}
-
-	/* Rx case */
-	/* Read, modify, write */
-	status = ice_read_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TMR_CMD, &val,
-					    lock_sbq);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, status %d\n",
-			  status);
-		return status;
-	}
-
-	/* Modify necessary bits only and perform write */
-	val &= ~TS_CMD_MASK;
-	val |= cmd_val;
-
-	status = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TMR_CMD, val,
-					     lock_sbq);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, status %d\n",
-			  status);
-		return status;
-	}
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_port_cmd_eth56g - Prepare all ports for a timer command
- * @hw: pointer to the HW struct
- * @cmd: timer command to prepare
- * @lock_sbq: true if the sideband queue lock must  be acquired
- *
- * Prepare all ports connected to this device for an upcoming timer sync
- * command.
- */
-static enum ice_status
-ice_ptp_port_cmd_eth56g(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
-			bool lock_sbq)
-{
-	enum ice_status status;
-	u8 port;
-
-	for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
-		if (!(hw->ena_lports & BIT(port)))
-			continue;
-
-		status = ice_ptp_one_port_cmd_eth56g(hw, port, cmd, lock_sbq);
-		if (status)
-			return status;
-	}
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_calc_fixed_tx_offset_eth56g - Calculated Fixed Tx offset for a port
- * @hw: pointer to the HW struct
- * @link_spd: the Link speed to calculate for
- *
- * Calculate the fixed offset due to known static latency data.
- */
-static u64
-ice_calc_fixed_tx_offset_eth56g(struct ice_hw *hw,
-				enum ice_ptp_link_spd link_spd)
-{
-	u64 fixed_offset = 0;
-	return fixed_offset;
-}
-
-/**
- * ice_phy_cfg_tx_offset_eth56g - Configure total Tx timestamp offset
- * @hw: pointer to the HW struct
- * @port: the PHY port to configure
- *
- * Program the PHY_REG_TOTAL_TX_OFFSET register with the total number of TUs to
- * adjust Tx timestamps by.
- *
- * To avoid overflow, when calculating the offset based on the known static
- * latency values, we use measurements in 1/100th of a nanosecond, and divide
- * the TUs per second up front. This avoids overflow while allowing
- * calculation of the adjustment using integer arithmetic.
- */
-enum ice_status ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port)
-{
-	enum ice_ptp_link_spd link_spd = ICE_PTP_LNK_SPD_10G;
-	enum ice_status status;
-	u64 total_offset;
-
-	total_offset = ice_calc_fixed_tx_offset_eth56g(hw, link_spd);
-
-	/* Now that the total offset has been calculated, program it to the
-	 * PHY and indicate that the Tx offset is ready. After this,
-	 * timestamps will be enabled.
-	 */
-	status = ice_write_64b_phy_reg_eth56g(hw, port,
-					      PHY_REG_TOTAL_TX_OFFSET_L,
-					      total_offset);
-	if (status)
-		return status;
-
-	return ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1);
-}
-
-/**
- * ice_calc_fixed_rx_offset_eth56g - Calculated the fixed Rx offset for a port
- * @hw: pointer to HW struct
- * @link_spd: The Link speed to calculate for
- *
- * Determine the fixed Rx latency for a given link speed.
- */
-static u64
-ice_calc_fixed_rx_offset_eth56g(struct ice_hw *hw,
-				enum ice_ptp_link_spd link_spd)
-{
-	u64 fixed_offset = 0;
-	return fixed_offset;
-}
-
-/**
- * ice_phy_cfg_rx_offset_eth56g - Configure total Rx timestamp offset
- * @hw: pointer to the HW struct
- * @port: the PHY port to configure
- *
- * Program the PHY_REG_TOTAL_RX_OFFSET register with the number of Time Units to
- * adjust Rx timestamps by. This combines calculations from the Vernier offset
- * measurements taken in hardware with some data about known fixed delay as
- * well as adjusting for multi-lane alignment delay.
- *
- * This function must be called only after the offset registers are valid,
- * i.e. after the Vernier calibration wait has passed, to ensure that the PHY
- * has measured the offset.
- *
- * To avoid overflow, when calculating the offset based on the known static
- * latency values, we use measurements in 1/100th of a nanosecond, and divide
- * the TUs per second up front. This avoids overflow while allowing
- * calculation of the adjustment using integer arithmetic.
- */
-enum ice_status ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port)
-{
-	enum ice_status status;
-	u64 total_offset;
-
-	total_offset = ice_calc_fixed_rx_offset_eth56g(hw, 0);
-
-	/* Now that the total offset has been calculated, program it to the
-	 * PHY and indicate that the Rx offset is ready. After this,
-	 * timestamps will be enabled.
-	 */
-	status = ice_write_64b_phy_reg_eth56g(hw, port,
-					      PHY_REG_TOTAL_RX_OFFSET_L,
-					      total_offset);
-	if (status)
-		return status;
-
-	return ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1);
-}
-
-/**
- * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time
- * @hw: pointer to the HW struct
- * @port: the PHY port to read
- * @phy_time: on return, the 64bit PHY timer value
- * @phc_time: on return, the lower 64bits of PHC time
- *
- * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY
- * and PHC timer values.
- */
-static enum ice_status
-ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, u64 *phy_time,
-				 u64 *phc_time)
-{
-	enum ice_status status;
-	u64 tx_time, rx_time;
-	u32 zo, lo;
-	u8 tmr_idx;
-
-	tmr_idx = ice_get_ptp_src_clock_index(hw);
-
-	/* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */
-	ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
-
-	/* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
-	status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_READ_TIME, true);
-	if (status)
-		return status;
-
-	/* Issue the sync to start the ICE_PTP_READ_TIME capture */
-	ice_ptp_exec_tmr_cmd(hw);
-	ice_ptp_clean_cmd(hw);
-
-	/* Read the captured PHC time from the shadow time registers */
-	zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
-	lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
-	*phc_time = (u64)lo << 32 | zo;
-
-	/* Read the captured PHY time from the PHY shadow registers */
-	status = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time);
-	if (status)
-		return status;
-
-	/* If the PHY Tx and Rx timers don't match, log a warning message.
-	 * Note that this should not happen in normal circumstances since the
-	 * driver always programs them together.
-	 */
-	if (tx_time != rx_time)
-		ice_warn(hw, "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
-			 port, (unsigned long long)tx_time,
-			 (unsigned long long)rx_time);
-
-	*phy_time = tx_time;
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer
- * @hw: pointer to the HW struct
- * @port: the PHY port to synchronize
- *
- * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
- * This is done by issuing a ICE_PTP_READ_TIME command which triggers a
- * simultaneous read of the PHY timer and PHC timer. Then we use the
- * difference to calculate an appropriate 2s complement addition to add
- * to the PHY timer in order to ensure it reads the same value as the
- * primary PHC timer.
- */
-static enum ice_status ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)
-{
-	u64 phc_time, phy_time, difference;
-	enum ice_status status;
-
-	if (!ice_ptp_lock(hw)) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
-		return ICE_ERR_NOT_READY;
-	}
-
-	status = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time,
-						  &phc_time);
-	if (status)
-		goto err_unlock;
-
-	/* Calculate the amount required to add to the port time in order for
-	 * it to match the PHC time.
-	 *
-	 * Note that the port adjustment is done using 2s complement
-	 * arithmetic. This is convenient since it means that we can simply
-	 * calculate the difference between the PHC time and the port time,
-	 * and it will be interpreted correctly.
-	 */
-
-	ice_ptp_src_cmd(hw, ICE_PTP_NOP);
-	difference = phc_time - phy_time;
-
-	status = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference, true);
-	if (status)
-		goto err_unlock;
-
-	status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_ADJ_TIME, true);
-	if (status)
-		goto err_unlock;
-
-	/* Issue the sync to activate the time adjustment */
-	ice_ptp_exec_tmr_cmd(hw);
-	ice_ptp_clean_cmd(hw);
-
-	/* Re-capture the timer values to flush the command registers and
-	 * verify that the time was properly adjusted.
-	 */
-
-	status = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time,
-						  &phc_time);
-	if (status)
-		goto err_unlock;
-
-	ice_info(hw, "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
-		 port, (unsigned long long)phy_time,
-		 (unsigned long long)phc_time);
-
-err_unlock:
-	ice_ptp_unlock(hw);
-	return status;
-}
-
-/**
- * ice_stop_phy_timer_eth56g - Stop the PHY clock timer
- * @hw: pointer to the HW struct
- * @port: the PHY port to stop
- * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS
- *
- * Stop the clock of a PHY port. This must be done as part of the flow to
- * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
- * initialized or when link speed changes.
- */
-enum ice_status
-ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset)
-{
-	enum ice_status status;
-
-	status = ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0);
-	if (status)
-		return status;
-
-	status = ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0);
-	if (status)
-		return status;
-
-	ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_start_phy_timer_eth56g - Start the PHY clock timer
- * @hw: pointer to the HW struct
- * @port: the PHY port to start
- * @bypass: unused, for compatibility
- *
- * Start the clock of a PHY port. This must be done as part of the flow to
- * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
- * initialized or when link speed changes.
- *
- */
-enum ice_status
-ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass)
-{
-	enum ice_status status;
-	u32 lo, hi;
-	u64 incval;
-	u8 tmr_idx;
-
-	tmr_idx = ice_get_ptp_src_clock_index(hw);
-
-	status = ice_stop_phy_timer_eth56g(hw, port, false);
-	if (status)
-		return status;
-
-	ice_ptp_src_cmd(hw, ICE_PTP_NOP);
-
-	lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
-	hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
-	incval = (u64)hi << 32 | lo;
-
-	status = ice_write_40b_phy_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
-					      incval);
-	if (status)
-		return status;
-
-	status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_INIT_INCVAL,
-					     true);
-	if (status)
-		return status;
-
-	ice_ptp_exec_tmr_cmd(hw);
-
-	status = ice_sync_phy_timer_eth56g(hw, port);
-	if (status)
-		return status;
-
-	/* Program the Tx offset */
-	status = ice_phy_cfg_tx_offset_eth56g(hw, port);
-	if (status)
-		return status;
-
-	/* Program the Rx offset */
-	status = ice_phy_cfg_rx_offset_eth56g(hw, port);
-	if (status)
-		return status;
-
-	ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_init_phc_eth56g - Perform E822 specific PHC initialization
- * @hw: pointer to HW struct
- *
- * Perform PHC initialization steps specific to E822 devices.
- */
-static enum ice_status ice_ptp_init_phc_eth56g(struct ice_hw *hw)
-{
-	enum ice_status status = ICE_SUCCESS;
-	u32 regval;
-
-	/* Enable reading switch and PHY registers over the sideband queue */
-#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
-#define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
-	regval = rd32(hw, PF_SB_REM_DEV_CTL);
-	regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ |
-		   PF_SB_REM_DEV_CTL_PHY0);
-	wr32(hw, PF_SB_REM_DEV_CTL, regval);
-
-	/* Initialize the Clock Generation Unit */
-	status = ice_init_cgu_e822(hw);
-
-	return status;
-}
-
-/**
- * ice_ptp_read_tx_hwtstamp_status_eth56g - Get the current TX timestamp
- * status mask. Returns the mask of ports where TX timestamps are available
- * @hw: pointer to the HW struct
- * @ts_status: the timestamp mask pointer
- */
-enum ice_status
-ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)
-{
-	enum ice_status status;
-
-	status = ice_read_phy_eth56g_raw_lp(hw, PHY_PTP_INT_STATUS, ts_status,
-					    true);
-	if (status)
-		return status;
-
-	ice_debug(hw, ICE_DBG_PTP, "PHY interrupt status: %x\n", *ts_status);
-
-	return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_init_phy_cfg - Get the current TX timestamp status
- * mask. Returns the mask of ports where TX timestamps are available
- * @hw: pointer to the HW struct
- */
-enum ice_status
-ice_ptp_init_phy_cfg(struct ice_hw *hw)
-{
-	enum ice_status status;
-	u32 phy_rev;
-
-	status = ice_read_phy_eth56g_raw_lp(hw, PHY_REG_REVISION, &phy_rev,
-					    true);
-	if (status)
-		return status;
-
-	if (phy_rev == PHY_REVISION_ETH56G) {
-		hw->phy_cfg = ICE_PHY_ETH56G;
-		return ICE_SUCCESS;
-	}
-
-	if (ice_is_e810(hw))
-		hw->phy_cfg = ICE_PHY_E810;
-	else
-		hw->phy_cfg = ICE_PHY_E822;
-
-	return ICE_SUCCESS;
-}
 
 /* ----------------------------------------------------------------------------
  * E822 family functions