FAILED: patch "[PATCH] mtd: spi-nor: spansion: Enable JFFS2 write buffer for" failed to apply to 6.3-stable tree
Subsystems (3)
[email protected]
maintainerThe patch below does not apply to the 6.3-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.3.y
git checkout FETCH_HEAD
git cherry-pick -x 9fd0945fe6fadfb6b54a9cd73be101c02b3e8134
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2023050724-lapped-bunkbed-43a4@gregkh' --subject-prefix 'PATCH 6.3.y' HEAD^..
Possible dependencies:
9fd0945fe6fa ("mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER flash") 4eddee70140b ("mtd: spi-nor: Add a RWW flag")
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 9fd0945fe6fadfb6b54a9cd73be101c02b3e8134 Mon Sep 17 00:00:00 2001
From: Takahiro Kuwano <[email protected]>
Date: Thu, 6 Apr 2023 15:17:44 +0900
Subject: [PATCH] mtd: spi-nor: spansion: Enable JFFS2 write buffer for
Infineon s28hx SEMPER flash
Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program granularity is 16-byte ECC data unit size. JFFS2 supports write buffer mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE flag in order to enable JFFS2 write buffer mode support.
A new SNOR_F_ECC flag is introduced to determine if the part has on-die ECC and if it has, MTD_BIT_WRITEABLE is unset.
In vendor specific driver, a common cypress_nor_ecc_init() helper is added. This helper takes care for ECC related initialization for SEMPER flash family by setting up params->writesize and SNOR_F_ECC.
drivers/mtd/spi-nor/core.c +3 -0
@@ -3407,6 +3407,9 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor) mtd->name =dev_name (dev); mtd->type =MTD_NORFLASH ; mtd->flags =MTD_CAP_NORFLASH ; +/* Unset BIT_WRITEABLE to enable JFFS2 write buffer for ECC'd NOR */ +if (nor->flags &SNOR_F_ECC ) + mtd->flags &= ~MTD_BIT_WRITEABLE ;if (nor->info->flags &SPI_NOR_NO_ERASE ) mtd->flags |=MTD_NO_ERASE ;else
drivers/mtd/spi-nor/core.h +1 -0
@@ -131,6 +131,7 @@ enum spi_nor_option_flags {SNOR_F_SOFT_RESET =BIT (12 ),SNOR_F_SWP_IS_VOLATILE =BIT (13 ),SNOR_F_RWW =BIT (14 ), + SNOR_F_ECC = BIT(15), }; struct spi_nor_read_command {
drivers/mtd/spi-nor/debugfs.c +1 -0
@@ -26,6 +26,7 @@ static const char *const snor_f_names[] = {SNOR_F_NAME (SOFT_RESET ),SNOR_F_NAME (SWP_IS_VOLATILE ),SNOR_F_NAME (RWW ), + SNOR_F_NAME(ECC), };#undef SNOR_F_NAME
drivers/mtd/spi-nor/spansion.c +12 -1
@@ -332,6 +332,17 @@ static int cypress_nor_set_page_size(struct spi_nor *nor)return 0 ; } +static void cypress_nor_ecc_init (struct spi_nor *nor) +{ +/* +* Programming is supported only in 16-byte ECC data unit granularity. +* Byte-programming, bit-walking, or multiple program operations to the +* same ECC data unit without an erase are not allowed. +*/ + nor->params->writesize =16 ; + nor->flags |=SNOR_F_ECC ; +} + static int s25fs256t_post_bfpt_fixup(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header,
@@ -506,7 +517,7 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor,static void s28hx_t_late_init (struct spi_nor *nor) { nor->params->octal_dtr_enable = cypress_nor_octal_dtr_enable; - nor->params->writesize =16 ; +cypress_nor_ecc_init (nor); }static const struct spi_nor_fixups s28hx_t_fixups = {