pinctrl: tegra: Add Tegra234 pinmux driver
Subsystems (4)
v3 cover pinctrl: tegra: Add Tegra234 pinmux driver
From: Thierry Reding <[email protected]>
Hi,
this is an updated version of Prathamesh's v2 of the series, which can be found here:
https://patchwork.ozlabs.org/project/linux-tegra/list/?series=345256
The most prominent change is the split of the device tree bindings into multiple files to make them more readable, as agreed upon with Krzysztof during review.
Changes in v3:
- split up device tree bindings into multiple files for better readability
- do not permit underscore in pinmux node names
- use correct #address-cells and #size-cells for DT nodes
- fixup a typo in the gpio-ranges property name
Note that the driver patch applies on top of the function table fix that I sent out earlier:
http://patchwork.ozlabs.org/project/linux-tegra/list/?series=357206
Once accepted, patches 1 and 2 can go through the pinctrl tree and I can pick up patch 3 into the Tegra tree. Alternatively I can also pick up patch 1 into the Tegra tree to help with validation. We're not quite at a point yet where the Tegra DTs fully validate, so it doesn't matter much which way these get applied.
Thanks,
Thierry
Prathamesh Shete (3):
dt-bindings: pinctrl: Document Tegra234 pin controllers
pinctrl: tegra: Add Tegra234 pinmux driver
arm64: tegra: Add Tegra234 pin controllers
.../pinctrl/nvidia,tegra234-pinmux-aon.yaml | 61 + .../nvidia,tegra234-pinmux-common.yaml | 65 + .../pinctrl/nvidia,tegra234-pinmux.yaml | 141 ++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 12 + drivers/pinctrl/tegra/Kconfig | 4 + drivers/pinctrl/tegra/Makefile | 1 + drivers/pinctrl/tegra/pinctrl-tegra234.c | 1969 +++++++++++++++++ drivers/soc/tegra/Kconfig | 1 + 8 files changed, 2254 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra234.c
Signature · 1 line
2.40.1
PATCH v3 1/3 dt-bindings: pinctrl: Document Tegra234 pin controllers
From: Prathamesh Shete <[email protected]>
Tegra234 contains two pin controllers. Document their compatible strings and describe the list of pins and functions that they provide.
---
Changes in v3:
- split up into multiple files (suggested by Krzysztof)
- do not permit underscore in pinmux node names
- reword commit message
.../pinctrl/nvidia,tegra234-pinmux-aon.yaml | 61 ++++++++ .../nvidia,tegra234-pinmux-common.yaml | 65 ++++++++ .../pinctrl/nvidia,tegra234-pinmux.yaml | 141 ++++++++++++++++++ 3 files changed, 267 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +61 -0
@@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +$ref: nvidia,tegra234-pinmux-common.yaml + +title: NVIDIA Tegra234 AON Pinmux Controller + +maintainers: + - Thierry Reding <[email protected]> + - Jon Hunter <[email protected]> + +properties: + compatible: + const: nvidia,tegra234-pinmux-aon + + reg: true + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + properties: + nvidia,pins: + items: + enum: [ can0_dout_paa0, can0_din_paa1, can1_dout_paa2, + can1_din_paa3, can0_stb_paa4, can0_en_paa5, + soc_gpio49_paa6, can0_err_paa7, can1_stb_pbb0, + can1_en_pbb1, soc_gpio50_pbb2, can1_err_pbb3, + spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2, + spi2_cs0_pcc3, touch_clk_pcc4, uart3_tx_pcc5, + uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0, + gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, + sce_error_pee0, vcomp_alert_pee1, + ao_retention_n_pee2, batt_oc_pee3, power_on_pee4, + soc_gpio26_pee5, soc_gpio27_pee6, bootv_ctl_n_pee7, + hdmi_cec_pgg0, + # drive groups + drive_touch_clk_pcc4, drive_uart3_rx_pcc6, + drive_uart3_tx_pcc5, drive_gen8_i2c_sda_pdd2, + drive_gen8_i2c_scl_pdd1, drive_spi2_mosi_pcc2, + drive_gen2_i2c_scl_pcc7, drive_spi2_cs0_pcc3, + drive_gen2_i2c_sda_pdd0, drive_spi2_sck_pcc0, + drive_spi2_miso_pcc1, drive_can1_dout_paa2, + drive_can1_din_paa3, drive_can0_dout_paa0, + drive_can0_din_paa1, drive_can0_stb_paa4, + drive_can0_en_paa5, drive_soc_gpio49_paa6, + drive_can0_err_paa7, drive_can1_stb_pbb0, + drive_can1_en_pbb1, drive_soc_gpio50_pbb2, + drive_can1_err_pbb3, drive_sce_error_pee0, + drive_batt_oc_pee3, drive_bootv_ctl_n_pee7, + drive_power_on_pee4, drive_soc_gpio26_pee5, + drive_soc_gpio27_pee6, drive_ao_retention_n_pee2, + drive_vcomp_alert_pee1, drive_hdmi_cec_pgg0 ] + +additionalProperties: false +...
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +65 -0
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Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml new file +141 -0
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Signature · 1 line
2.40.1
Re: [PATCH v3 1/3] dt-bindings: pinctrl: Document Tegra234 pin controllers
Quoted 27 lines · Thierry Reding
From: Prathamesh Shete <[email protected]>
Tegra234 contains two pin controllers. Document their compatible strings and describe the list of pins and functions that they provide.
Signed-off-by Prathamesh Shete <[email protected]>Signed-off-by Thierry Reding <[email protected]>---
Changes in v3:
- split up into multiple files (suggested by Krzysztof)
- do not permit underscore in pinmux node names
- reword commit message.../pinctrl/nvidia,tegra234-pinmux-aon.yaml | 61 ++++++++ .../nvidia,tegra234-pinmux-common.yaml | 65 ++++++++ .../pinctrl/nvidia,tegra234-pinmux.yaml | 141 ++++++++++++++++++ 3 files changed, 267 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yamlDocumentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +0
-0
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml line 7
Quoted 7 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +7
-0@@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +$ref: nvidia,tegra234-pinmux-common.yaml
Keep it before properties:. That's really unexpected order.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml line 19
Quoted 12 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +12
-0+ +title: NVIDIA Tegra234 AON Pinmux Controller + +maintainers: + - Thierry Reding <[email protected]> + - Jon Hunter <[email protected]> + +properties: + compatible: + const: nvidia,tegra234-pinmux-aon + + reg: true
Drop this one.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml line 26
Quoted 7 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +7
-0+ +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties:
Why do you need this? This binding looks odd...
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml line 28
Quoted 2 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +2
-0+ properties: + nvidia,pins:
min/maxItems? If variable, put some reasonable numbers.
Quoted 22 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +22
-0+ items: + enum: [ can0_dout_paa0, can0_din_paa1, can1_dout_paa2, + can1_din_paa3, can0_stb_paa4, can0_en_paa5, + soc_gpio49_paa6, can0_err_paa7, can1_stb_pbb0, + can1_en_pbb1, soc_gpio50_pbb2, can1_err_pbb3, + spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2, + spi2_cs0_pcc3, touch_clk_pcc4, uart3_tx_pcc5, + uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0, + gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, + sce_error_pee0, vcomp_alert_pee1, + ao_retention_n_pee2, batt_oc_pee3, power_on_pee4, + soc_gpio26_pee5, soc_gpio27_pee6, bootv_ctl_n_pee7, + hdmi_cec_pgg0, + # drive groups + drive_touch_clk_pcc4, drive_uart3_rx_pcc6, + drive_uart3_tx_pcc5, drive_gen8_i2c_sda_pdd2, + drive_gen8_i2c_scl_pdd1, drive_spi2_mosi_pcc2, + drive_gen2_i2c_scl_pcc7, drive_spi2_cs0_pcc3, + drive_gen2_i2c_sda_pdd0, drive_spi2_sck_pcc0, + drive_spi2_miso_pcc1, drive_can1_dout_paa2, + drive_can1_din_paa3, drive_can0_dout_paa0, + drive_can0_din_paa1, drive_can0_stb_paa4,
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml line 60
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +10
-0+ drive_can0_en_paa5, drive_soc_gpio49_paa6, + drive_can0_err_paa7, drive_can1_stb_pbb0, + drive_can1_en_pbb1, drive_soc_gpio50_pbb2, + drive_can1_err_pbb3, drive_sce_error_pee0, + drive_batt_oc_pee3, drive_bootv_ctl_n_pee7, + drive_power_on_pee4, drive_soc_gpio26_pee5, + drive_soc_gpio27_pee6, drive_ao_retention_n_pee2, + drive_vcomp_alert_pee1, drive_hdmi_cec_pgg0 ] + +additionalProperties: false
unevaluatedProperties: false
Quoted 11 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +1
-0+...Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +4
-0@@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-common.yaml#
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 14
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +10
-0+$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra234 Pinmux Controller + +maintainers: + - Thierry Reding <[email protected]> + - Jon Hunter <[email protected]> + +properties: + compatible: true
Drop, won't be needed with additionalProps true.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 24
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +10
-0+ + reg: + items: + - description: pinmux registers + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + properties: + phandle: true
No clue what's that but if you need it, something is broken. Remove it and we need to fix the root cause.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 27
Quoted 3 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +3
-0+ + # pin groups + additionalProperties:
I still don't get what you want to express here. We usually list the children with patternProperties for specific pattern. Your approach could work too, but did you really check it enforces proper type/ref? That it really works?
Quoted 9 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +9
-0+ $ref: nvidia,tegra-pinmux-common.yaml + unevaluatedProperties: false + properties: + nvidia,function: + enum: [ gp, uartc, i2c8, spi2, i2c2, can1, can0, rsvd0, eth0, eth2, + eth1, dp, eth3, i2c4, i2c7, i2c9, eqos, pe2, pe1, pe0, pe3, + pe4, pe5, pe6, pe7, pe8, pe9, pe10, qspi0, qspi1, qpsi, + sdmmc1, sce, soc, gpio, hdmi, ufs0, spi3, spi1, uartb, uarte, + usb, extperiph2, extperiph1, i2c3, vi0, i2c5, uarta, uartd,
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 46
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +10
-0+ i2c1, i2s4, i2s6, aud, spi5, touch, uartj, rsvd1, wdt, tsc, + dmic3, led, vi0_alt, i2s5, nv, extperiph3, extperiph4, spi4, + ccla, i2s1, i2s2, i2s3, i2s8, rsvd2, dmic5, dca, displayb, + displaya, vi1, dcb, dmic1, dmic4, i2s7, dmic2, dspk0, rsvd3, + tsc_alt, istctrl, vi1_alt, dspk1, igpu ] + + nvidia,pins: + description: An array of strings. Each string contains the name + of a pin or group. Valid values for these names are listed + below.
Drop, not needed.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 55
Quoted 9 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +9
-0+ + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true
Drop all these.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 60
Quoted 5 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +5
-0+ + required: + - nvidia,pins + +additionalProperties: false
We keep it "true" for common schema and then the users of this binding use unevaluatedProperties: false.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 64
Quoted 4 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +4
-0+ +required: + - compatible + - reg
Keep it before additionalProperites:.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 65
Quoted 1 line
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +1
-0+...
Best regards,
Krzysztof
Re: [PATCH v3 1/3] dt-bindings: pinctrl: Document Tegra234 pin controllers
Quoted 64 lines · Krzysztof Kozlowski
Quoted 27 lines · Thierry Reding
From: Prathamesh Shete <[email protected]>
Tegra234 contains two pin controllers. Document their compatible strings and describe the list of pins and functions that they provide.
Signed-off-by Prathamesh Shete <[email protected]>Signed-off-by Thierry Reding <[email protected]>---
Changes in v3:
- split up into multiple files (suggested by Krzysztof)
- do not permit underscore in pinmux node names
- reword commit message.../pinctrl/nvidia,tegra234-pinmux-aon.yaml | 61 ++++++++ .../nvidia,tegra234-pinmux-common.yaml | 65 ++++++++ .../pinctrl/nvidia,tegra234-pinmux.yaml | 141 ++++++++++++++++++ 3 files changed, 267 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yamlDocumentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +0
-0Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml line 7
Quoted 7 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +7
-0@@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +$ref: nvidia,tegra234-pinmux-common.yamlKeep it before properties:. That's really unexpected order.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml line 19
Quoted 12 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +12
-0+ +title: NVIDIA Tegra234 AON Pinmux Controller + +maintainers: + - Thierry Reding <[email protected]> + - Jon Hunter <[email protected]> + +properties: + compatible: + const: nvidia,tegra234-pinmux-aon + + reg: trueDrop this one.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml line 26
Quoted 7 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +7
-0+ +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties:Why do you need this? This binding looks odd...
Quoted 4 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml line 28
Quoted 2 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +2
-0+ properties: + nvidia,pins:min/maxItems? If variable, put some reasonable numbers.
There isn't really a reasonable number for maxItems. Most of the pins in a controller could technically be assigned to the same group. While that doesn't happen in practice (most of the time there will be a single pin per group), limiting this isn't correct and would only make this less flexible. Are there any advantages to arbitrarily restricting maxItems?
Quoted 60 lines
Quoted 23 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +22
-0+ items: + enum: [ can0_dout_paa0, can0_din_paa1, can1_dout_paa2, + can1_din_paa3, can0_stb_paa4, can0_en_paa5, + soc_gpio49_paa6, can0_err_paa7, can1_stb_pbb0, + can1_en_pbb1, soc_gpio50_pbb2, can1_err_pbb3, + spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2, + spi2_cs0_pcc3, touch_clk_pcc4, uart3_tx_pcc5, + uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0, + gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, + sce_error_pee0, vcomp_alert_pee1, + ao_retention_n_pee2, batt_oc_pee3, power_on_pee4, + soc_gpio26_pee5, soc_gpio27_pee6, bootv_ctl_n_pee7, + hdmi_cec_pgg0, + # drive groups + drive_touch_clk_pcc4, drive_uart3_rx_pcc6, + drive_uart3_tx_pcc5, drive_gen8_i2c_sda_pdd2, + drive_gen8_i2c_scl_pdd1, drive_spi2_mosi_pcc2, + drive_gen2_i2c_scl_pcc7, drive_spi2_cs0_pcc3, + drive_gen2_i2c_sda_pdd0, drive_spi2_sck_pcc0, + drive_spi2_miso_pcc1, drive_can1_dout_paa2, + drive_can1_din_paa3, drive_can0_dout_paa0, + drive_can0_din_paa1, drive_can0_stb_paa4,Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml line 60
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +10
-0+ drive_can0_en_paa5, drive_soc_gpio49_paa6, + drive_can0_err_paa7, drive_can1_stb_pbb0, + drive_can1_en_pbb1, drive_soc_gpio50_pbb2, + drive_can1_err_pbb3, drive_sce_error_pee0, + drive_batt_oc_pee3, drive_bootv_ctl_n_pee7, + drive_power_on_pee4, drive_soc_gpio26_pee5, + drive_soc_gpio27_pee6, drive_ao_retention_n_pee2, + drive_vcomp_alert_pee1, drive_hdmi_cec_pgg0 ] + +additionalProperties: falseunevaluatedProperties: false
Quoted 11 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file +1
-0+...Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +4
-0@@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-common.yaml#Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 14
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +10
-0+$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra234 Pinmux Controller + +maintainers: + - Thierry Reding <[email protected]> + - Jon Hunter <[email protected]> + +properties: + compatible: trueDrop, won't be needed with additionalProps true.
Quoted 13 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 24
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +10
-0+ + reg: + items: + - description: pinmux registers + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + properties: + phandle: trueNo clue what's that but if you need it, something is broken. Remove it and we need to fix the root cause.
I'm fairly sure that the validation tools at least used to require a "properties" property. Or it might have been because phandle would otherwise be validated by the "additionalProperties" block below. In any case, running the validation again it doesn't seem like that's true anymore, so I'll drop this.
Quoted 8 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 27
Quoted 3 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +3
-0+ + # pin groups + additionalProperties:I still don't get what you want to express here. We usually list the children with patternProperties for specific pattern. Your approach could work too, but did you really check it enforces proper type/ref? That it really works?
If you look at the description of the common Tegra pinmux bindings in pinctr/nvidia,tegra-pinmux-common.yaml, there's this comment in the description:
The name of each subnode is not important; all subnodes should be enumerated and processed purely based on their content.
Using additionalProperties is the best transcription of this because it is the easiest way to accept any node name. So we purely validate based on content.
And yes, this was already tested with the bindings from previous chip iterations, which all use the same construct, and it works fine.
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Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +9
-0+ $ref: nvidia,tegra-pinmux-common.yaml + unevaluatedProperties: false + properties: + nvidia,function: + enum: [ gp, uartc, i2c8, spi2, i2c2, can1, can0, rsvd0, eth0, eth2, + eth1, dp, eth3, i2c4, i2c7, i2c9, eqos, pe2, pe1, pe0, pe3, + pe4, pe5, pe6, pe7, pe8, pe9, pe10, qspi0, qspi1, qpsi, + sdmmc1, sce, soc, gpio, hdmi, ufs0, spi3, spi1, uartb, uarte, + usb, extperiph2, extperiph1, i2c3, vi0, i2c5, uarta, uartd,Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 46
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Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +10
-0+ i2c1, i2s4, i2s6, aud, spi5, touch, uartj, rsvd1, wdt, tsc, + dmic3, led, vi0_alt, i2s5, nv, extperiph3, extperiph4, spi4, + ccla, i2s1, i2s2, i2s3, i2s8, rsvd2, dmic5, dca, displayb, + displaya, vi1, dcb, dmic1, dmic4, i2s7, dmic2, dspk0, rsvd3, + tsc_alt, istctrl, vi1_alt, dspk1, igpu ] + + nvidia,pins: + description: An array of strings. Each string contains the name + of a pin or group. Valid values for these names are listed + below.Drop, not needed.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 55
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Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +9
-0+ + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true
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Drop all these.
I think these were originally included here because the generic pinmux group schema (in nvidia,tegra-pinmux-common.yaml) lists the superset of all properties that can go into a group. However, not all chips generations support all of those properties.
But looking at this again, given that we have unevaluatedProperties in the above, this shouldn't have any effect anyway.
I wonder now how we can properly validate for this. I suppose another option would be to have a list of properties that aren't allowed and mark them as ": false".
Thierry
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Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 60
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Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +5
-0+ + required: + - nvidia,pins + +additionalProperties: falseWe keep it "true" for common schema and then the users of this binding use unevaluatedProperties: false.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 64
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Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +4
-0+ +required: + - compatible + - regKeep it before additionalProperites:.
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml line 65
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Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file +1
-0+...Best regards,
Krzysztof
PATCH v3 2/3 pinctrl: tegra: Add Tegra234 pinmux driver
In reply to Thierry RedingFrom: Prathamesh Shete <[email protected]>
This change adds support for the two pin controllers found on Tegra234.
---
Changes in v3:
- rebase on top of pinmux function table fix:
http://patchwork.ozlabs.org/project/linux-tegra/list/?series=357206
drivers/pinctrl/tegra/Kconfig | 4 + drivers/pinctrl/tegra/Makefile | 1 + drivers/pinctrl/tegra/pinctrl-tegra234.c | 1969 ++++++++++++++++++++++ drivers/soc/tegra/Kconfig | 1 + 4 files changed, 1975 insertions(+) create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra234.c
drivers/pinctrl/tegra/Kconfig +4 -0
@@ -28,6 +28,10 @@ config PINCTRL_TEGRA194 bool select PINCTRL_TEGRA +config PINCTRL_TEGRA234 + bool + select PINCTRL_TEGRA + config PINCTRL_TEGRA_XUSB def_bool y if ARCH_TEGRA select GENERIC_PHY
drivers/pinctrl/tegra/Makefile +1 -0
@@ -6,4 +6,5 @@ obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o obj-$(CONFIG_PINCTRL_TEGRA194) += pinctrl-tegra194.o +obj-$(CONFIG_PINCTRL_TEGRA234) += pinctrl-tegra234.o obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o
drivers/pinctrl/tegra/pinctrl-tegra234.c new file +1969 -0
1,969 lines not on this page · raw message
drivers/soc/tegra/Kconfig +1 -0
@@ -125,6 +125,7 @@ config ARCH_TEGRA_234_SOC bool "NVIDIA Tegra234 SoC" depends on !CPU_BIG_ENDIAN select MAILBOX + select PINCTRL_TEGRA234 select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC
Signature · 1 line
2.40.1
Tue, May 30, 2023 at 03:36:53PM +0200, Thierry Reding kirjoitti:
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From: Prathamesh Shete <[email protected]>
This change adds support for the two pin controllers found on Tegra234.
...
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drivers/pinctrl/tegra/pinctrl-tegra234.c new file +4
-0+// SPDX-License-Identifier: GPL-2.0+ +/* +* Pinctrl data for the NVIDIA Tegra234 pinmux +*
drivers/pinctrl/tegra/pinctrl-tegra234.c line 14
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drivers/pinctrl/tegra/pinctrl-tegra234.c new file +9
-0+* Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved. +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details.
The whole SPDX idea is to avoid including this duplication. Is this a requirement of your company lawers?
drivers/pinctrl/tegra/pinctrl-tegra234.c line 17
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+ */
drivers/pinctrl/tegra/pinctrl-tegra234.c new file +2
-0+ +#include <linux/module.h>
Missing mod_devicetable.h
drivers/pinctrl/tegra/pinctrl-tegra234.c line 19
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drivers/pinctrl/tegra/pinctrl-tegra234.c new file +2
-0+#include <linux/of.h> +#include <linux/of_device.h>
Do you need both for just of_device_get_match_data() call? Note, you may replace it with device_get_match_data() and property.h and be completely OF independent.
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drivers/pinctrl/tegra/pinctrl-tegra234.c new file +4
-0+#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include "pinctrl-tegra.h"
...
drivers/pinctrl/tegra/pinctrl-tegra234.c line 1628
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drivers/pinctrl/tegra/pinctrl-tegra234.c new file +6
-0+#define PINGROUP (pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \ + gpio_sfio_sel, schmitt_b) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \
Can we use struct pingroup, please?
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drivers/pinctrl/tegra/pinctrl-tegra234.c new file +12
-0+ .funcs = { \ + TEGRA_MUX_##f0, \ + TEGRA_MUX_##f1, \ + TEGRA_MUX_##f2, \ + TEGRA_MUX_##f3, \ + }, \ + PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \ + e_input, e_lpdr, e_pbias_buf, \ + gpio_sfio_sel, schmitt_b) \ + drive_##pg_name, \ + } +static int tegra234_pinctrl_probe (struct platform_device *pdev)
drivers/pinctrl/tegra/pinctrl-tegra234.c
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drivers/pinctrl/tegra/pinctrl-tegra234.c new file +10
-0+{ +const struct tegra_pinctrl_soc_data *soc =of_device_get_match_data (&pdev->dev); + +return tegra_pinctrl_probe (pdev, soc); +} + +static const struct of_device_id tegra234_pinctrl_of_match[] = { + { .compatible ="nvidia,tegra234-pinmux" , .data = &tegra234_pinctrl}, + { .compatible ="nvidia,tegra234-pinmux-aon" , .data = &tegra234_pinctrl_aon }, + { },
No comma for the terminator entry.
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+};
...
drivers/pinctrl/tegra/pinctrl-tegra234.c line 1959
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drivers/pinctrl/tegra/pinctrl-tegra234.c new file +4
-0+static struct platform_driver tegra234_pinctrl_driver = { + .driver = { + .name ="tegra234-pinctrl" , + .owner =THIS_MODULE ,
Approx. 15 years this is _not_ needed.
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drivers/pinctrl/tegra/pinctrl-tegra234.c new file +4
-0+ .of_match_table = tegra234_pinctrl_of_match, + }, + .probe = tegra234_pinctrl_probe, +};
Signature · 2 lines
With Best Regards, Andy Shevchenko
PATCH v3 3/3 arm64: tegra: Add Tegra234 pin controllers
In reply to Thierry RedingFrom: Prathamesh Shete <[email protected]>
Add the device tree nodes for the MAIN and AON pin controllers found on the Tegra234 family of SoCs.
---
Changes in v3:
- use correct value for #address-cells and #size-cells
- correct gpio-ranges property name
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/nvidia/tegra234.dtsi +12 -0
@@ -109,6 +109,7 @@ gpio: gpio@2200000 { interrupt-controller; #gpio-cells = <2>; gpio-controller; + gpio-ranges = <&pinmux 0 0 164>; }; ethernet@2310000 {
@@ -147,6 +148,11 @@ codec@242c000 { status = "disabled"; }; + pinmux: pinmux@2430000 { + compatible = "nvidia,tegra234-pinmux"; + reg = <0x0 0x2430000 0x0 0x19100>; + }; + gpcdma: dma-controller@2600000 { compatible = "nvidia,tegra234-gpcdma", "nvidia,tegra186-gpcdma";
@@ -1805,6 +1811,12 @@ gpio_aon: gpio@c2f0000 { interrupt-controller; #gpio-cells = <2>; gpio-controller; + gpio-ranges = <&pinmux_aon 0 0 32>; + }; + + pinmux_aon: pinmux@c300000 { + compatible = "nvidia,tegra234-pinmux-aon"; + reg = <0x0 0xc300000 0x0 0x4000>; }; pwm4: pwm@c340000 {
Signature · 1 line
2.40.1