Add initialization of clock for StarFive JH7110 SoC
Subsystems (4)
v3 cover Add initialization of clock for StarFive JH7110 SoC
Hi,
This patchset adds initial rudimentary support for the StarFive Quad SPI controller driver. And this driver will be used in StarFive's VisionFive 2 board. In 6.4, the QSPI_AHB and QSPI_APB clocks changed from the default ON state to the default OFF state, so these clocks need to be enabled in the driver.At the same time, dts patch is added to this series.
Changes v1->v2:
- Rebaed to v6.4rc6.
- Renamed the clock names.
- Changed the variable definition type.
Changes v1->v2:
- Renamed the clock names.
- Specified a different array of clocks.
- Used clk_bulk_ APIs.
The patch series is based on v6.4rc6.
William Qiu (3):
dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC
.../bindings/spi/cdns,qspi-nor.yaml | 20 +++++++++++- .../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++ drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++ 4 files changed, 89 insertions(+), 1 deletion(-)
--
2.34.1
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PATCH v3 1/3 dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3. Other platforms do not have this constraint.
--- .../bindings/spi/cdns,qspi-nor.yaml | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +19 -1
@@ -26,6 +26,15 @@ allOf: const: starfive,jh7110-qspi then: properties: + clocks: + maxItems: 3 + + clock-names: + items: + - const: ref + - const: ahb + - const: apb + resets: minItems: 2 maxItems: 3
@@ -38,6 +47,9 @@ allOf: else: properties: + clocks: + maxItems: 1 + resets: maxItems: 2
@@ -70,7 +82,13 @@ properties: maxItems: 1 clocks: - maxItems: 1 + maxItems: 3 + + clock-names: + items: + - const: ref + - const: ahb + - const: apb cdns,fifo-depth: description:
Signature · 7 lines
2.34.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Rob Herring
maintainerRe: [PATCH v3 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
Quoted 11 lines · William Qiu
The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3. Other platforms do not have this constraint.
Signed-off-by William Qiu <[email protected]>Reviewed-by Hal Feng <[email protected]>Reviewed-by Conor Dooley <[email protected]>--- .../bindings/spi/cdns,qspi-nor.yaml | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/spi/cdns,qspi-nor.example.dtb: spi@ff705000: clocks: [[4294967295]] is too short
from schema $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Re: [PATCH v3 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
Quoted 34 lines · Rob Herring
Quoted 11 lines · William Qiu
The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3. Other platforms do not have this constraint.
Signed-off-by William Qiu <[email protected]>Reviewed-by Hal Feng <[email protected]>Reviewed-by Conor Dooley <[email protected]>--- .../bindings/spi/cdns,qspi-nor.yaml | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)My bot found errors running 'make DT_CHECKER_FLAGS=-m
dt_binding_check' on your patch (DT_CHECKER_FLAGSis new in v5.13):yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/spi/cdns,qspi-nor.example.dtb: spi@ff705000: clocks: [[4294967295]] is too short
from schema $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make
dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
Quoted 6 lines
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that
DT_SCHEMA_FILEScan be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
It seems that my changes are not compatible with other dts files, I'll try to fix it.
Thanks for reminding.
Best regards
William
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Re: [PATCH v3 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
In reply to William QiuQuoted 17 lines · William Qiu
The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3. Other platforms do not have this constraint.
Signed-off-by William Qiu <[email protected]>Reviewed-by Hal Feng <[email protected]>Reviewed-by Conor Dooley <[email protected]>--- .../bindings/spi/cdns,qspi-nor.yaml | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +0
-0@@ -26,6 +26,15 @@ allOf: const: starfive,jh7110-qspi
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml allOf: · line 36
Quoted 10 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +8
-0then: properties: + clocks: + maxItems: 3 + + clock-names: + items: + - const: ref + - const: ahb + - const: apb
You are duplicating top-level property. Define the items only in one place. If this list is applicable to everything, then in top-level property.
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml allOf: · line 51
Quoted 10 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +3
-0+ resets: minItems: 2 maxItems: 3@@ -38,6 +47,9 @@ allOf: else: properties: + clocks: + maxItems: 1
clock-names is missing. They must be in sync with clocks. What is the first clock?
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml properties: · line 85
Quoted 10 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +2
-1+ resets: maxItems: 2@@ -70,7 +82,13 @@ properties: maxItems: 1 clocks: - maxItems: 1 + maxItems: 3
You did not test it before sending. minItems is missing.
Quoted 11 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +6
-0+ + clock-names: + items: + - const: ref + - const: ahb + - const: apbcdns,fifo-depth:
description:
Best regards,
Krzysztof
Re: [PATCH v3 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
Quoted 23 lines · Krzysztof Kozlowski
Quoted 22 lines · William Qiu
The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3. Other platforms do not have this constraint.
Signed-off-by William Qiu <[email protected]>Reviewed-by Hal Feng <[email protected]>Reviewed-by Conor Dooley <[email protected]>--- .../bindings/spi/cdns,qspi-nor.yaml | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +3
-0@@ -26,6 +26,15 @@ allOf: const: starfive,jh7110-qspi then: properties: + clocks: + maxItems: 3 +
Quoted 9 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml allOf: · line 36
Quoted 5 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +5
-0+ clock-names: + items: + - const: ref + - const: ahb + - const: apbYou are duplicating top-level property. Define the items only in one place. If this list is applicable to everything, then in top-level property.
Only in JH7110 SoC need there clocks, other platforms do not have this constraint. So I need to duplicating top-level property.
Quoted 6 lines
Quoted 6 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +1
-0+ resets: minItems: 2 maxItems: 3@@ -38,6 +47,9 @@ allOf:
Quoted 8 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml allOf: · line 51
Quoted 4 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +2
-0else: properties: + clocks: + maxItems: 1clock-names is missing. They must be in sync with clocks. What is the first clock?
But there are no clock-names before, should I add it?
Quoted 7 lines
Quoted 7 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +1
-0+ resets: maxItems: 2@@ -70,7 +82,13 @@ properties: maxItems: 1
Quoted 7 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml properties: · line 85
Quoted 3 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +1
-1clocks: - maxItems: 1 + maxItems: 3You did not test it before sending. minItems is missing.
I will add it.
As for other platforms, should I use enum to constraint the clocks?
Quoted 9 lines
Quoted 9 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +6
-0+ + clock-names: + items: + - const: ref + - const: ahb + - const: apb
Quoted 6 lines
Quoted 2 lines
cdns,fifo-depth:
description:Best regards,
Krzysztof
Thanks for taking time to review this patches series.
Best regards,
William
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Re: [PATCH v3 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
Quoted 35 lines · William Qiu
Quoted 23 lines · Krzysztof Kozlowski
Quoted 22 lines · William Qiu
The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3. Other platforms do not have this constraint.
Signed-off-by William Qiu <[email protected]>Reviewed-by Hal Feng <[email protected]>Reviewed-by Conor Dooley <[email protected]>--- .../bindings/spi/cdns,qspi-nor.yaml | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +3
-0@@ -26,6 +26,15 @@ allOf: const: starfive,jh7110-qspi then: properties: + clocks: + maxItems: 3 +Quoted 9 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml allOf: · line 36
Quoted 5 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +5
-0+ clock-names: + items: + - const: ref + - const: ahb + - const: apbYou are duplicating top-level property. Define the items only in one place. If this list is applicable to everything, then in top-level property.
Quoted 2 lines
Only in JH7110 SoC need there clocks, other platforms do not have this constraint. So I need to duplicating top-level property.
You don't need, why? Why writing something twice is an answer to "JH7110 needs 3 clocks"? It's not related.
What is the clock for all other variants?
Quoted 14 lines
Quoted 6 lines
Quoted 6 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +1
-0+ resets: minItems: 2 maxItems: 3@@ -38,6 +47,9 @@ allOf:Quoted 8 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml allOf: · line 51
Quoted 4 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +2
-0else: properties: + clocks: + maxItems: 1clock-names is missing. They must be in sync with clocks. What is the first clock?
Quoted 1 line
But there are no clock-names before, should I add it?
Then let's just disallow it. Either you define it or you not allow it.
Quoted 14 lines
Quoted 7 lines
Quoted 7 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +1
-0+ resets: maxItems: 2@@ -70,7 +82,13 @@ properties: maxItems: 1Quoted 7 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml properties: · line 85
Quoted 3 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +1
-1clocks: - maxItems: 1 + maxItems: 3You did not test it before sending. minItems is missing.
Quoted 2 lines
I will add it.
As for other platforms, should I use enum to constraint the clocks?
What is the clock on other platforms?
Best regards,
Krzysztof
Re: [PATCH v3 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
Quoted 36 lines · Krzysztof Kozlowski
Quoted 35 lines · William Qiu
Quoted 32 lines · Krzysztof Kozlowski
Quoted 17 lines · William Qiu
The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3. Other platforms do not have this constraint.
Signed-off-by William Qiu <[email protected]>Reviewed-by Hal Feng <[email protected]>Reviewed-by Conor Dooley <[email protected]>--- .../bindings/spi/cdns,qspi-nor.yaml | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +0
-0@@ -26,6 +26,15 @@ allOf: const: starfive,jh7110-qspiDocumentation/devicetree/bindings/spi/cdns,qspi-nor.yaml allOf: · line 36
Quoted 10 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +8
-0then: properties: + clocks: + maxItems: 3 + + clock-names: + items: + - const: ref + - const: ahb + - const: apbYou are duplicating top-level property. Define the items only in one place. If this list is applicable to everything, then in top-level property.
Quoted 8 lines
Quoted 2 lines
Only in JH7110 SoC need there clocks, other platforms do not have this constraint. So I need to duplicating top-level property.
You don't need, why? Why writing something twice is an answer to "JH7110 needs 3 clocks"? It's not related.
What is the clock for all other variants?
I'll try to not duplicating top-level property.
Quoted 14 lines
Quoted 14 lines
Quoted 14 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml allOf: · line 51
Quoted 10 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +3
-0+ resets: minItems: 2 maxItems: 3@@ -38,6 +47,9 @@ allOf: else: properties: + clocks: + maxItems: 1clock-names is missing. They must be in sync with clocks. What is the first clock?
Quoted 4 lines
Quoted 1 line
But there are no clock-names before, should I add it?
Then let's just disallow it. Either you define it or you not allow it.
Fine, I'll keep it disallow.
Quoted 14 lines
Quoted 14 lines
Quoted 14 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml properties: · line 85
Quoted 10 lines
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +2
-1+ resets: maxItems: 2@@ -70,7 +82,13 @@ properties: maxItems: 1 clocks: - maxItems: 1 + maxItems: 3You did not test it before sending. minItems is missing.
Quoted 5 lines
Quoted 2 lines
I will add it.
As for other platforms, should I use enum to constraint the clocks?What is the clock on other platforms?
Other platforms have only one clock.
Quoted 3 lines
Best regards,
Krzysztof
Thanks for taking time to review this patch series and give usefull suggestions.
Best Regards,
William
PATCH v3 2/3 spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
In reply to William QiuAdd QSPI clock operation in device probe.
--- drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
drivers/spi/spi-cadence-quadspi.c +20 -0
@@ -63,6 +63,8 @@ struct cqspi_st {struct platform_device *pdev;struct spi_master *master;struct clk *clk; +struct clk_bulk_data *clks; +int num_clks;unsigned int sclk;void __iomem *iobase;
@@ -1715,6 +1717,16 @@ static int cqspi_probe(struct platform_device *pdev) }if (of_device_is_compatible (pdev->dev.of_node,"starfive,jh7110-qspi" )) { + cqspi->num_clks =devm_clk_bulk_get_all (dev, &cqspi->clks); +if (cqspi->num_clks <0 ) { +dev_err (dev,"Cannot claim clock: %u\n" , cqspi->num_clks); +return -EINVAL ; + } + + ret =clk_bulk_prepare_enable (cqspi->num_clks, cqspi->clks); +if (ret) +dev_err (dev,"Cannot enable clock clks\n" ); + rstc_ref =devm_reset_control_get_optional_exclusive (dev,"rstc_ref" );if (IS_ERR (rstc_ref)) { ret =PTR_ERR (rstc_ref);
@@ -1816,6 +1828,9 @@ static void cqspi_remove(struct platform_device *pdev)clk_disable_unprepare (cqspi->clk); +if (of_device_is_compatible (pdev->dev.of_node,"starfive,jh7110-qspi" )) +clk_bulk_disable_unprepare (cqspi->num_clks, cqspi->clks); +pm_runtime_put_sync (&pdev->dev);pm_runtime_disable (&pdev->dev); }
@@ -1831,6 +1846,9 @@ static int cqspi_suspend(struct device *dev)clk_disable_unprepare (cqspi->clk); +if (of_device_is_compatible (dev->of_node,"starfive,jh7110-qspi" )) +clk_bulk_disable_unprepare (cqspi->num_clks, cqspi->clks); +return ret; }
@@ -1840,6 +1858,8 @@ static int cqspi_resume(struct device *dev)struct spi_master *master =dev_get_drvdata (dev);clk_prepare_enable (cqspi->clk); +if (of_device_is_compatible (dev->of_node,"starfive,jh7110-qspi" )) +clk_bulk_prepare_enable (cqspi->num_clks, cqspi->clks);cqspi_wait_idle (cqspi);cqspi_controller_init (cqspi);
Signature · 7 lines
2.34.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
PATCH v3 3/3 riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC
In reply to William QiuAdd the quad spi controller node for the StarFive JH7110 SoC.
--- .../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++ 2 files changed, 50 insertions(+)
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +32 -0
@@ -126,6 +126,38 @@ &i2c6 { status = "okay"; }; +&qspi { + #address-cells = <1>; + #size-cells = <0>; + + nor_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg=<0>; + cdns,read-delay = <5>; + spi-max-frequency = <12000000>; + cdns,tshsl-ns = <1>; + cdns,tsd2d-ns = <1>; + cdns,tchsh-ns = <1>; + cdns,tslch-ns = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + spl@0 { + reg = <0x0 0x20000>; + }; + uboot@100000 { + reg = <0x100000 0x300000>; + }; + data@f00000 { + reg = <0xf00000 0x100000>; + }; + }; + }; +}; + &sysgpio { i2c0_pins: i2c0-0 { i2c-pins {
arch/riscv/boot/dts/starfive/jh7110.dtsi +18 -0
@@ -440,6 +440,24 @@ i2c6: i2c@12060000 { status = "disabled"; }; + qspi: spi@13010000 { + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; + reg = <0x0 0x13010000 0x0 0x10000 + 0x0 0x21000000 0x0 0x400000>; + interrupts = <25>; + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, + <&syscrg JH7110_SYSCLK_QSPI_AHB>, + <&syscrg JH7110_SYSCLK_QSPI_APB>; + clock-names = "ref", "ahb", "apb"; + resets = <&syscrg JH7110_SYSRST_QSPI_APB>, + <&syscrg JH7110_SYSRST_QSPI_AHB>, + <&syscrg JH7110_SYSRST_QSPI_REF>; + reset-names = "qspi", "qspi-ocp", "rstc_ref"; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + }; + syscrg: clock-controller@13020000 { compatible = "starfive,jh7110-syscrg"; reg = <0x0 0x13020000 0x0 0x10000>;
Signature · 7 lines
2.34.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Re: [PATCH v3 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC
Quoted 16 lines · William Qiu
Add the quad spi controller node for the StarFive JH7110 SoC.
Co-developed-by Ziv Xu <[email protected]>Signed-off-by Ziv Xu <[email protected]>Signed-off-by William Qiu <[email protected]>Reviewed-by Hal Feng <[email protected]>--- .../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++ 2 files changed, 50 insertions(+)arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +0
-0
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi &i2c6 { · line 135
Quoted 10 lines
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +7
-0@@ -126,6 +126,38 @@ &i2c6 { status = "okay"; }; +&qspi { + #address-cells = <1>; + #size-cells = <0>; + + nor_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg=<0>;
Missing spaces.
Quoted 33 lines
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +25
-0+ cdns,read-delay = <5>; + spi-max-frequency = <12000000>; + cdns,tshsl-ns = <1>; + cdns,tsd2d-ns = <1>; + cdns,tchsh-ns = <1>; + cdns,tslch-ns = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + spl@0 { + reg = <0x0 0x20000>; + }; + uboot@100000 { + reg = <0x100000 0x300000>; + }; + data@f00000 { + reg = <0xf00000 0x100000>; + }; + }; + }; +}; + &sysgpio { i2c0_pins: i2c0-0 { i2c-pins {arch/riscv/boot/dts/starfive/jh7110.dtsi +0
-0
arch/riscv/boot/dts/starfive/jh7110.dtsi i2c6: i2c@12060000 { · line 446
Quoted 7 lines
arch/riscv/boot/dts/starfive/jh7110.dtsi +4
-0@@ -440,6 +440,24 @@ i2c6: i2c@12060000 { status = "disabled"; }; + qspi: spi@13010000 { + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; + reg = <0x0 0x13010000 0x0 0x10000 + 0x0 0x21000000 0x0 0x400000>;
This should be two items so <>, <>. Not one item.
Best regards,
Krzysztof
Re: [PATCH v3 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC
Quoted 20 lines · Krzysztof Kozlowski
Quoted 19 lines · William Qiu
Add the quad spi controller node for the StarFive JH7110 SoC.
Co-developed-by Ziv Xu <[email protected]>Signed-off-by Ziv Xu <[email protected]>Signed-off-by William Qiu <[email protected]>Reviewed-by Hal Feng <[email protected]>--- .../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++ 2 files changed, 50 insertions(+)arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +0
-0@@ -126,6 +126,38 @@ &i2c6 { status = "okay"; };
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arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi &i2c6 { · line 135
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arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +7
-0+&qspi { + #address-cells = <1>; + #size-cells = <0>; + + nor_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg=<0>;Missing spaces.
Will fix.
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arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +25
-0+ cdns,read-delay = <5>; + spi-max-frequency = <12000000>; + cdns,tshsl-ns = <1>; + cdns,tsd2d-ns = <1>; + cdns,tchsh-ns = <1>; + cdns,tslch-ns = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + spl@0 { + reg = <0x0 0x20000>; + }; + uboot@100000 { + reg = <0x100000 0x300000>; + }; + data@f00000 { + reg = <0xf00000 0x100000>; + }; + }; + }; +}; + &sysgpio { i2c0_pins: i2c0-0 { i2c-pins {arch/riscv/boot/dts/starfive/jh7110.dtsi +0
-0arch/riscv/boot/dts/starfive/jh7110.dtsi i2c6: i2c@12060000 { · line 446
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arch/riscv/boot/dts/starfive/jh7110.dtsi +4
-0@@ -440,6 +440,24 @@ i2c6: i2c@12060000 { status = "disabled"; }; + qspi: spi@13010000 { + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; + reg = <0x0 0x13010000 0x0 0x10000 + 0x0 0x21000000 0x0 0x400000>;This should be two items so <>, <>. Not one item.
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Best regards,
Krzysztof
Will fix.
Thanks for taking time to review this patch series.
Best reagards
William