Skip to contentSkip to conversation

dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

PATCH Applied Conor Dooley 5 participants 9 messages Jun 15, 2023 – Jun 25, 2023

Subsystems (2)
Device tree bindings RISC-V
lore
Share & tools
lore

Conor Dooley

author
#0 lore raw

v2 cover dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

From: Conor Dooley <[email protected]>

Do the various bits needed to drop the additionalProperties: true that we currently have in riscv/cpu.yaml, to permit actually enforcing what people put in cpus nodes.

Changes in v2:
- drop patches 2 -> 5, they're now standard in dt-schema

CC Rob Herring <[email protected]>
CC Krzysztof Kozlowski <[email protected]>
CC Paul Walmsley <[email protected]>
CC Palmer Dabbelt <[email protected]>
CC [email protected]
CC [email protected]
CC [email protected]

Conor Dooley (2):
dt-bindings: riscv: cpus: add a ref the common cpu schema
dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

 Documentation/devicetree/bindings/riscv/cpus.yaml | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
Signature · 1 line
2.39.2
author
#1 lore raw

PATCH v2 1/2 dt-bindings: riscv: cpus: add a ref the common cpu schema

From: Conor Dooley <[email protected]>

To permit validation of RISC-V cpu nodes, "additionalProperties: true" needs to be swapped for "unevaluatedProperties: false". To facilitate this in a way that passes dt_binding_check, a reference to the cpu schema is required.

Disallow the generic cache-op-block-size property that that drags in, since the RISC-V CBO extensions do not require a common size, and have individual properties.

Signed-off-by Conor Dooley <[email protected]>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
 1 file changed, 6 insertions(+)
Documentation/devicetree/bindings/riscv/cpus.yaml +6 -0
index 3d2934b15e80..e89a10d9c06b 100644
@@ -23,6 +23,9 @@ description: |
   two cores, each of which has two hyperthreads, could be described as
   having four harts.
 
+allOf:
+  - $ref: /schemas/cpu.yaml#
+
 properties:
   compatible:
     oneOf:

@@ -98,6 +101,9 @@ properties:
     $ref: "/schemas/types.yaml#/definitions/string"
     pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
 
+  # RISC-V has multiple properties for cache op block sizes as the sizes
+  # differ between individual CBO extensions
+  cache-op-block-size: false
   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
   timebase-frequency: false
Signature · 1 line
2.39.2
maintainer Reviewed-by on v2 1/2
#2 lore raw

Re: [PATCH v2 1/2] dt-bindings: riscv: cpus: add a ref the common cpu schema

Quoted 7 lines · Conor Dooley

From: Conor Dooley <[email protected]>

To permit validation of RISC-V cpu nodes, "additionalProperties: true" needs to be swapped for "unevaluatedProperties: false". To facilitate this in a way that passes dt_binding_check, a reference to the cpu schema is required.

Quoted 9 lines

Disallow the generic cache-op-block-size property that that drags in, since the RISC-V CBO extensions do not require a common size, and have individual properties.

Signed-off-by Conor Dooley <[email protected]>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
 1 file changed, 6 insertions(+)
Reviewed-by Rob Herring <[email protected]>
author
#3 lore raw

PATCH v2 2/2 dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

To permit validation of cpu nodes, swap "additionalProperties: true" out for "unevaluatedProperties: false".

Signed-off-by Conor Dooley <[email protected]>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Documentation/devicetree/bindings/riscv/cpus.yaml +1 -1
index e89a10d9c06b..144da86718c1 100644
@@ -143,7 +143,7 @@ required:
   - riscv,isa
   - interrupt-controller
 
-additionalProperties: true
+unevaluatedProperties: false
 
 examples:
   - |
Signature · 7 lines
2.39.2


_______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv
maintainer Acked-by on the v2 series
#5 lore raw
In reply to Conor Dooley
Quoted 17 lines · Conor Dooley

From: Conor Dooley <[email protected]>

Do the various bits needed to drop the additionalProperties: true that we currently have in riscv/cpu.yaml, to permit actually enforcing what people put in cpus nodes.

Changes in v2:
- drop patches 2 -> 5, they're now standard in dt-schema

CC Rob Herring <[email protected]>
CC Krzysztof Kozlowski <[email protected]>
CC Paul Walmsley <[email protected]>
CC Palmer Dabbelt <[email protected]>
CC [email protected]
CC [email protected]
CC [email protected]
Quoted 6 lines

Conor Dooley (2):
dt-bindings: riscv: cpus: add a ref the common cpu schema
dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

 Documentation/devicetree/bindings/riscv/cpus.yaml | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
Acked-by Palmer Dabbelt <[email protected]>

LMK if you wanted me to pick these up?

author
#6 lore raw
Quoted 22 lines · Palmer Dabbelt
Quoted 21 lines · Conor Dooley

From: Conor Dooley <[email protected]>

Do the various bits needed to drop the additionalProperties: true that we currently have in riscv/cpu.yaml, to permit actually enforcing what people put in cpus nodes.

Changes in v2:
- drop patches 2 -> 5, they're now standard in dt-schema

CC Rob Herring <[email protected]>
CC Krzysztof Kozlowski <[email protected]>
CC Paul Walmsley <[email protected]>
CC Palmer Dabbelt <[email protected]>
CC [email protected]
CC [email protected]
CC [email protected]

Conor Dooley (2):
dt-bindings: riscv: cpus: add a ref the common cpu schema
dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

Quoted 6 lines
Quoted 2 lines
 Documentation/devicetree/bindings/riscv/cpus.yaml | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
Acked-by Palmer Dabbelt <[email protected]>

LMK if you wanted me to pick these up?

That was my hope, please do!

Cheers,
Conor.

Applied
#7 lore raw
In reply to Conor Dooley
Quoted 10 lines · Conor Dooley

From: Conor Dooley <[email protected]>

Do the various bits needed to drop the additionalProperties: true that we currently have in riscv/cpu.yaml, to permit actually enforcing what people put in cpus nodes.

Changes in v2:
- drop patches 2 -> 5, they're now standard in dt-schema

[...]

Applied, thanks!

[1/2] dt-bindings: riscv: cpus: add a ref the common cpu schema

      https://git.kernel.org/palmer/c/3c1b4758a954
[2/2] dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
      https://git.kernel.org/palmer/c/1ffe6ddc5c64

Best regards,

Signature · 1 line
Palmer Dabbelt <[email protected]>
CI Applied
#8 lore raw
In reply to Conor Dooley
This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <[email protected]>:

Hello:

This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <[email protected]>:

Quoted 10 lines · On Thu, 15 Jun 2023 23:50:13 +0100 you wrote:

From: Conor Dooley <[email protected]>

Do the various bits needed to drop the additionalProperties: true that we currently have in riscv/cpu.yaml, to permit actually enforcing what people put in cpus nodes.

Changes in v2:
- drop patches 2 -> 5, they're now standard in dt-schema

[...]

Here is the summary with links:
- [v2,1/2] dt-bindings: riscv: cpus: add a ref the common cpu schema

    https://git.kernel.org/riscv/c/3c1b4758a954
  - [v2,2/2] dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
    https://git.kernel.org/riscv/c/1ffe6ddc5c64

You are awesome, thank you!

Signature · 2 lines
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html