Add support for Allwinner PWM on D1/T113s/R329 SoCs
Subsystems (4)
v2 cover Add support for Allwinner PWM on D1/T113s/R329 SoCs
Hi,
This series adds support for PWM controller on new Allwinner's SoCs, such as D1, T113s and R329. The implemented driver provides basic functionality for control PWM channels.
v2:
- fix dt-bindings
- fix a remark in the driver
Aleksandr Shubin (3):
dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM
controller
pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support
riscv: dts: allwinner: d1: Add pwm node
.../bindings/pwm/allwinner,sun20i-pwm.yaml | 83 +++++ .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 + drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sun20i.c | 322 ++++++++++++++++++ 5 files changed, 428 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml create mode 100644 drivers/pwm/pwm-sun20i.c
Signature · 1 line
2.25.1
PATCH v2 1/3 dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller
Allwinner's D1, T113-S3 and R329 SoCs have a new pwm controller witch is different from the previous pwm-sun4i.
The D1 and T113 are identical in terms of peripherals, they differ only in the architecture of the CPU core, and even share the majority of their DT. Because of that, using the same compatible makes sense.
The R329 is a different SoC though, and should have a different compatible string added, especially as there is a difference in the number of channels.
D1 and T113s SoCs have one PWM controller with 8 channels. R329 SoC has two PWM controllers in both power domains, one of them has 9 channels (CPUX one) and the other has 6 (CPUS one).
Add a device tree binding for them.
--- .../bindings/pwm/allwinner,sun20i-pwm.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file +83 -0
@@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner D1, T113-S3 and R329 PWM + +maintainers: + - Aleksandr Shubin <[email protected]> + +properties: + compatible: + oneOf: + - const: allwinner,sun20i-d1-pwm + - items: + - const: allwinner,sun20i-r329-pwm + - const: allwinner,sun20i-d1-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: 24 MHz oscillator + - description: Bus Clock + + clock-names: + items: + - const: hosc + - const: bus + + resets: + maxItems: 1 + description: module reset + +allOf: + - $ref: pwm.yaml# + + - if: + properties: + compatible: + contains: + const: allwinner,sun20i-r329-pwm + + then: + properties: + allwinner,pwm-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [6, 9] + + required: + - allwinner,pwm-channels + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun20i-d1-ccu.h> + #include <dt-bindings/reset/sun20i-d1-ccu.h> + + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x02000c00 0x400>; + clocks = <&dcxo>, <&ccu CLK_BUS_PWM>; + clock-names = "hosc", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <0x3>; + }; + +...
Signature · 1 line
2.25.1
Re: [PATCH v2 1/3] dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller
Hey Alexksandr,
Quoted 73 lines · Aleksandr Shubin
Allwinner's D1, T113-S3 and R329 SoCs have a new pwm controller witch is different from the previous pwm-sun4i.
The D1 and T113 are identical in terms of peripherals, they differ only in the architecture of the CPU core, and even share the majority of their DT. Because of that, using the same compatible makes sense.
The R329 is a different SoC though, and should have a different compatible string added, especially as there is a difference in the number of channels.D1 and T113s SoCs have one PWM controller with 8 channels. R329 SoC has two PWM controllers in both power domains, one of them has 9 channels (CPUX one) and the other has 6 (CPUS one).
Add a device tree binding for them.
Signed-off-by Aleksandr Shubin <[email protected]>--- .../bindings/pwm/allwinner,sun20i-pwm.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yamlDocumentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file +44
-0@@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner D1, T113-S3 and R329 PWM + +maintainers: + - Aleksandr Shubin <[email protected]> + +properties: + compatible: + oneOf: + - const: allwinner,sun20i-d1-pwm + - items: + - const: allwinner,sun20i-r329-pwm + - const: allwinner,sun20i-d1-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: 24 MHz oscillator + - description: Bus Clock + + clock-names: + items: + - const: hosc + - const: bus + + resets: + maxItems: 1 + description: module reset + +allOf: + - $ref: pwm.yaml# + + - if: + properties:
Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml line 54
Quoted 10 lines
Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file +10
-0+ compatible: + contains: + const: allwinner,sun20i-r329-pwm + + then: + properties: + allwinner,pwm-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [6, 9]
Last time I acked something like this, Krzysztof complained about defining properties inside conditionals. This diff avoids the definition in the conditional, while also disallowing it on the D1. Thoughts?
Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml +10 -6
@@ -37,6 +37,11 @@ properties: maxItems: 1 description: module reset + allwinner,pwm-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [6, 9] + allOf: - $ref: pwm.yaml#
@@ -47,15 +52,14 @@ allOf: const: allwinner,sun20i-r329-pwm then: - properties: - allwinner,pwm-channels: - $ref: /schemas/types.yaml#/definitions/uint32 - description: The number of PWM channels configured for this instance - enum: [6, 9] - required: - allwinner,pwm-channels + else: + not: + required: + - allwinner,pwm-channels + required: - compatible - reg
Quoted 32 lines
Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file +29
-0+ + required: + - allwinner,pwm-channels + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun20i-d1-ccu.h> + #include <dt-bindings/reset/sun20i-d1-ccu.h> + + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x02000c00 0x400>; + clocks = <&dcxo>, <&ccu CLK_BUS_PWM>; + clock-names = "hosc", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <0x3>; + }; + +...Signature · 1 line
2.25.1
Re: [PATCH v2 1/3] dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller
In reply to Aleksandr ShubinDocumentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml line 38
Quoted 3 lines · Aleksandr Shubin
Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file +3
-0+ resets: + maxItems: 1 + description: module reset
Also, this description doesn't really add any value, resetting the peripheral is the default meaning pretty much, and should be dropped.
Re: [PATCH v2 1/3] dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller
In reply to Aleksandr ShubinQuoted 74 lines · Aleksandr Shubin
Allwinner's D1, T113-S3 and R329 SoCs have a new pwm controller witch is different from the previous pwm-sun4i.
The D1 and T113 are identical in terms of peripherals, they differ only in the architecture of the CPU core, and even share the majority of their DT. Because of that, using the same compatible makes sense.
The R329 is a different SoC though, and should have a different compatible string added, especially as there is a difference in the number of channels.D1 and T113s SoCs have one PWM controller with 8 channels. R329 SoC has two PWM controllers in both power domains, one of them has 9 channels (CPUX one) and the other has 6 (CPUS one).
Add a device tree binding for them.
Signed-off-by Aleksandr Shubin <[email protected]>--- .../bindings/pwm/allwinner,sun20i-pwm.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yamlDocumentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file +45
-0@@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner D1, T113-S3 and R329 PWM + +maintainers: + - Aleksandr Shubin <[email protected]> + +properties: + compatible: + oneOf: + - const: allwinner,sun20i-d1-pwm + - items: + - const: allwinner,sun20i-r329-pwm + - const: allwinner,sun20i-d1-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: 24 MHz oscillator + - description: Bus Clock + + clock-names: + items: + - const: hosc + - const: bus + + resets: + maxItems: 1 + description: module reset + +allOf: + - $ref: pwm.yaml# + + - if: + properties: + compatible:
Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml line 55
Quoted 10 lines
Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file +10
-0+ contains: + const: allwinner,sun20i-r329-pwm + + then: + properties: + allwinner,pwm-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [6, 9] +
Your DTS says this is 8, so you did not test it. Why do you need it in the first place? r329 can have both 6 and 9?
Anyway, this won't work with additionalProperties, which you would see with testing. Don't define properties in allOf. Also switch to
unevaluatedProperties: false.
Best regards,
Krzysztof
PATCH v2 2/3 pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support
In reply to Aleksandr ShubinAllwinner's D1, T113-S3 and R329 SoCs have a quite different PWM controllers with ones supported by pwm-sun4i driver.
This patch adds a PWM controller driver for Allwinner's D1, T113-S3 and R329 SoCs. The main difference between these SoCs is the number of channels defined by the DT property.
--- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sun20i.c | 322 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 333 insertions(+) create mode 100644 drivers/pwm/pwm-sun20i.c
drivers/pwm/Kconfig +10 -0
@@ -594,6 +594,16 @@ config PWM_SUN4I To compile this driver as a module, choose M here: the module will be called pwm-sun4i. +config PWM_SUN20I + tristate "Allwinner D1/T113s/R329 PWM support" + depends on ARCH_SUNXI || COMPILE_TEST + depends on COMMON_CLK + help + Generic PWM framework driver for Allwinner D1/T113s/R329 SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-sun20i. + config PWM_SUNPLUS tristate "Sunplus PWM support" depends on ARCH_SUNPLUS || COMPILE_TEST
drivers/pwm/Makefile +1 -0
@@ -55,6 +55,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o +obj-$(CONFIG_PWM_SUN20I) += pwm-sun20i.o obj-$(CONFIG_PWM_SUNPLUS) += pwm-sunplus.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o
drivers/pwm/pwm-sun20i.c new file +322 -0
322 lines not on this page · raw message
Signature · 1 line
2.25.1
PATCH v2 3/3 riscv: dts: allwinner: d1: Add pwm node
In reply to Aleksandr ShubinD1 and T113s contain a pwm controller with 8 channels. This controller is supported by the sun20i-pwm driver.
Add a device tree node for it.
--- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +12 -0
@@ -127,6 +127,18 @@ uart3_pb_pins: uart3-pb-pins { }; }; + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x02000c00 0x400>; + clocks = <&dcxo>, + <&ccu CLK_BUS_PWM>; + clock-names = "hosc", "bus"; + resets = <&ccu RST_BUS_PWM>; + allwinner,pwm-channels = <8>; + status = "disabled"; + #pwm-cells = <0x3>; + }; + ccu: clock-controller@2001000 { compatible = "allwinner,sun20i-d1-ccu"; reg = <0x2001000 0x1000>;
Signature · 1 line
2.25.1
Re: [PATCH v2 3/3] riscv: dts: allwinner: d1: Add pwm node
Quoted 17 lines · Aleksandr Shubin
D1 and T113s contain a pwm controller with 8 channels. This controller is supported by the sun20i-pwm driver.
Add a device tree node for it.
Signed-off-by Aleksandr Shubin <[email protected]>--- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +0
-0@@ -127,6 +127,18 @@ uart3_pb_pins: uart3-pb-pins { }; };
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi uart3_pb_pins: uart3-pb-pins { · line 138
Quoted 10 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +8
-0+ pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x02000c00 0x400>; + clocks = <&dcxo>, + <&ccu CLK_BUS_PWM>; + clock-names = "hosc", "bus"; + resets = <&ccu RST_BUS_PWM>; + allwinner,pwm-channels = <8>;
This fails dtbs_check. Please test the dts against the bindings.
Cheers,
Conor.
Quoted 10 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +4
-0+ status = "disabled"; + #pwm-cells = <0x3>; + }; + ccu: clock-controller@2001000 { compatible = "allwinner,sun20i-d1-ccu";reg = <
0x20010000x1000>;Signature · 1 line
2.25.1