RISC-V: archrandom support
Subsystems (2)
v2 cover RISC-V: archrandom support
This patchset adds support for the archrandom API to the RISC-V architecture.
The ratified crypto scalar extensions provide entropy bits via the seed CSR, as exposed by the Zkr extension.
The first patch of this patchset allows for detecting support of the Zbc and all scalar crypto extensions.
The second patch exposes the Zbc and scalar crypto extensions through the hwprobe syscall.
The last patch relies on the first ones to check for the Zkr support, and implements get_random_seed_longs by looping through a seed CSR read-write to return one long worth of entropy.
---
v2:
- Fixed the ISA map setting for zkbx
- Alphanumerically sort the ISA map setting
- Added my SOB on Hongren's patch
- Fixed patch #1 commit message
- Remove printk prefix from the archrandom implementation
- Fix needed_seeds computation (and make it const)
- Replace riscv_isa_extension_available() with riscv_has_extension_likely()
- Make the get_random_seed_longs implementation more readable
---
Hongren (Zenithal) Zheng (1):
RISC-V: add Bitmanip/Scalar Crypto parsing from DT
Samuel Ortiz (2):
RISC-V: hwprobe: Expose Zbc and the scalar crypto extensions
RISC-V: Implement archrandom when Zkr is available
Documentation/riscv/hwprobe.rst | 33 +++++++++++++ arch/riscv/include/asm/archrandom.h | 70 +++++++++++++++++++++++++++ arch/riscv/include/asm/csr.h | 9 ++++ arch/riscv/include/asm/hwcap.h | 11 +++++ arch/riscv/include/uapi/asm/hwprobe.h | 11 +++++ arch/riscv/kernel/cpu.c | 11 +++++ arch/riscv/kernel/cpufeature.c | 30 ++++++++++++ arch/riscv/kernel/sys_riscv.c | 36 ++++++++------ 8 files changed, 197 insertions(+), 14 deletions(-) create mode 100644 arch/riscv/include/asm/archrandom.h
base-commit: 488833ccdcac118da16701f4ee0673b20ba47fe3
Signature · 1 line
2.41.0
PATCH v2 1/3 RISC-V: add Bitmanip/Scalar Crypto parsing from DT
From: "Hongren (Zenithal) Zheng" <[email protected]>
Parse Zb/Zk related string from DT and output them to cpuinfo.
It is worth noting that the Scalar Crypto extension defines "zk" as a shorthand for the Zkn, Zkr and Zkt extensions. Since the Zkn one also implies the Zbkb, Zbkc and Zbkx extensions, simply passing the valid "zk" extension name through a DT will enable all of the Zbkb, Zbkc, Zbkx, Zkn, Zkr and Zkt extensions.
Also, since there currently is no mechanism to merge all enabled extensions, the generated cpuinfo output could be relatively large. For example, setting the "riscv,isa" DT property to "rv64imafdc_zk_zks" will generate the following cpuinfo output:
"rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt".
--- arch/riscv/include/asm/hwcap.h | 11 +++++++++++ arch/riscv/kernel/cpu.c | 11 +++++++++++ arch/riscv/kernel/cpufeature.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+)
arch/riscv/include/asm/hwcap.h +11 -0
@@ -53,6 +53,17 @@#define RISCV_ISA_EXT_ZICSR 40#define RISCV_ISA_EXT_ZIFENCEI 41#define RISCV_ISA_EXT_ZIHPM 42 +#define RISCV_ISA_EXT_ZBC 43 +#define RISCV_ISA_EXT_ZBKB 44 +#define RISCV_ISA_EXT_ZBKC 45 +#define RISCV_ISA_EXT_ZBKX 46 +#define RISCV_ISA_EXT_ZKND 47 +#define RISCV_ISA_EXT_ZKNE 48 +#define RISCV_ISA_EXT_ZKNH 49 +#define RISCV_ISA_EXT_ZKR 50 +#define RISCV_ISA_EXT_ZKSED 51 +#define RISCV_ISA_EXT_ZKSH 52 +#define RISCV_ISA_EXT_ZKT 53#define RISCV_ISA_EXT_MAX 64#define RISCV_ISA_EXT_NAME_LEN_MAX 32
arch/riscv/kernel/cpu.c +11 -0
@@ -215,7 +215,18 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {__RISCV_ISA_EXT_DATA (zihpm,RISCV_ISA_EXT_ZIHPM ),__RISCV_ISA_EXT_DATA (zba,RISCV_ISA_EXT_ZBA ),__RISCV_ISA_EXT_DATA (zbb,RISCV_ISA_EXT_ZBB ), +__RISCV_ISA_EXT_DATA (zbc,RISCV_ISA_EXT_ZBC ), +__RISCV_ISA_EXT_DATA (zbkb,RISCV_ISA_EXT_ZBKB ), +__RISCV_ISA_EXT_DATA (zbkc,RISCV_ISA_EXT_ZBKC ), +__RISCV_ISA_EXT_DATA (zbkx,RISCV_ISA_EXT_ZBKX ),__RISCV_ISA_EXT_DATA (zbs,RISCV_ISA_EXT_ZBS ), +__RISCV_ISA_EXT_DATA (zknd,RISCV_ISA_EXT_ZKND ), +__RISCV_ISA_EXT_DATA (zkne,RISCV_ISA_EXT_ZKNE ), +__RISCV_ISA_EXT_DATA (zknh,RISCV_ISA_EXT_ZKNH ), +__RISCV_ISA_EXT_DATA (zkr,RISCV_ISA_EXT_ZKR ), +__RISCV_ISA_EXT_DATA (zksed,RISCV_ISA_EXT_ZKSED ), +__RISCV_ISA_EXT_DATA (zksh,RISCV_ISA_EXT_ZKSH ), +__RISCV_ISA_EXT_DATA (zkt,RISCV_ISA_EXT_ZKT ),__RISCV_ISA_EXT_DATA (smaia,RISCV_ISA_EXT_SMAIA ),__RISCV_ISA_EXT_DATA (ssaia,RISCV_ISA_EXT_SSAIA ), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
arch/riscv/kernel/cpufeature.c +30 -0
@@ -309,10 +309,40 @@ void __init riscv_fill_hwcap(void)SET_ISA_EXT_MAP ("svpbmt" ,RISCV_ISA_EXT_SVPBMT );SET_ISA_EXT_MAP ("zba" ,RISCV_ISA_EXT_ZBA );SET_ISA_EXT_MAP ("zbb" ,RISCV_ISA_EXT_ZBB ); +SET_ISA_EXT_MAP ("zbc" ,RISCV_ISA_EXT_ZBC ); +SET_ISA_EXT_MAP ("zbkb" ,RISCV_ISA_EXT_ZBKB ); +SET_ISA_EXT_MAP ("zbkc" ,RISCV_ISA_EXT_ZBKC ); +SET_ISA_EXT_MAP ("zbkx" ,RISCV_ISA_EXT_ZBKX );SET_ISA_EXT_MAP ("zbs" ,RISCV_ISA_EXT_ZBS );SET_ISA_EXT_MAP ("zicbom" ,RISCV_ISA_EXT_ZICBOM );SET_ISA_EXT_MAP ("zicboz" ,RISCV_ISA_EXT_ZICBOZ );SET_ISA_EXT_MAP ("zihintpause" ,RISCV_ISA_EXT_ZIHINTPAUSE ); +SET_ISA_EXT_MAP ("zk" ,RISCV_ISA_EXT_ZBKB ); +SET_ISA_EXT_MAP ("zk" ,RISCV_ISA_EXT_ZBKC ); +SET_ISA_EXT_MAP ("zk" ,RISCV_ISA_EXT_ZBKX ); +SET_ISA_EXT_MAP ("zk" ,RISCV_ISA_EXT_ZKND ); +SET_ISA_EXT_MAP ("zk" ,RISCV_ISA_EXT_ZKNE ); +SET_ISA_EXT_MAP ("zk" ,RISCV_ISA_EXT_ZKNH ); +SET_ISA_EXT_MAP ("zk" ,RISCV_ISA_EXT_ZKR ); +SET_ISA_EXT_MAP ("zk" ,RISCV_ISA_EXT_ZKT ); +SET_ISA_EXT_MAP ("zkn" ,RISCV_ISA_EXT_ZBKB ); +SET_ISA_EXT_MAP ("zkn" ,RISCV_ISA_EXT_ZBKC ); +SET_ISA_EXT_MAP ("zkn" ,RISCV_ISA_EXT_ZBKX ); +SET_ISA_EXT_MAP ("zkn" ,RISCV_ISA_EXT_ZKND ); +SET_ISA_EXT_MAP ("zkn" ,RISCV_ISA_EXT_ZKNE ); +SET_ISA_EXT_MAP ("zkn" ,RISCV_ISA_EXT_ZKNH ); +SET_ISA_EXT_MAP ("zknd" ,RISCV_ISA_EXT_ZKND ); +SET_ISA_EXT_MAP ("zkne" ,RISCV_ISA_EXT_ZKNE ); +SET_ISA_EXT_MAP ("zknh" ,RISCV_ISA_EXT_ZKNH ); +SET_ISA_EXT_MAP ("zks" ,RISCV_ISA_EXT_ZBKB ); +SET_ISA_EXT_MAP ("zks" ,RISCV_ISA_EXT_ZBKC ); +SET_ISA_EXT_MAP ("zks" ,RISCV_ISA_EXT_ZBKX ); +SET_ISA_EXT_MAP ("zks" ,RISCV_ISA_EXT_ZKSED ); +SET_ISA_EXT_MAP ("zks" ,RISCV_ISA_EXT_ZKSH ); +SET_ISA_EXT_MAP ("zksed" ,RISCV_ISA_EXT_ZKSED ); +SET_ISA_EXT_MAP ("zksh" ,RISCV_ISA_EXT_ZKSH ); +SET_ISA_EXT_MAP ("zkr" ,RISCV_ISA_EXT_ZKR ); +SET_ISA_EXT_MAP ("zkt" ,RISCV_ISA_EXT_ZKT ); }#undef SET_ISA_EXT_MAP }
Signature · 1 line
2.41.0
Re: [PATCH v2 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT
Quoted 17 lines · Samuel Ortiz
From: "Hongren (Zenithal) Zheng" <[email protected]>
Parse Zb/Zk related string from DT and output them to cpuinfo.
It is worth noting that the Scalar Crypto extension defines "zk" as a shorthand for the Zkn, Zkr and Zkt extensions. Since the Zkn one also implies the Zbkb, Zbkc and Zbkx extensions, simply passing the valid "zk" extension name through a DT will enable all of the Zbkb, Zbkc, Zbkx, Zkn, Zkr and Zkt extensions.
Also, since there currently is no mechanism to merge all enabled extensions, the generated cpuinfo output could be relatively large. For example, setting the "riscv,isa" DT property to "
rv64imafdc_zk_zks" will generate the following cpuinfo output:
"rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt".
Quoted 3 lines
Tested-by Jiatai He <[email protected]>Signed-off-by Samuel Ortiz <[email protected]>Signed-off-by Hongren (Zenithal) Zheng <[email protected]>
Re: [PATCH v2 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT
In reply to Samuel OrtizHey,
Quoted 34 lines · Samuel Ortiz
From: "Hongren (Zenithal) Zheng" <[email protected]>
Parse Zb/Zk related string from DT and output them to cpuinfo.
It is worth noting that the Scalar Crypto extension defines "zk" as a shorthand for the Zkn, Zkr and Zkt extensions. Since the Zkn one also implies the Zbkb, Zbkc and Zbkx extensions, simply passing the valid "zk" extension name through a DT will enable all of the Zbkb, Zbkc, Zbkx, Zkn, Zkr and Zkt extensions.
Also, since there currently is no mechanism to merge all enabled extensions, the generated cpuinfo output could be relatively large. For example, setting the "riscv,isa" DT property to "
rv64imafdc_zk_zks" will generate the following cpuinfo output:
"rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt".Tested-by Jiatai He <[email protected]>Signed-off-by Samuel Ortiz <[email protected]>Signed-off-by Hongren (Zenithal) Zheng <[email protected]>--- arch/riscv/include/asm/hwcap.h | 11 +++++++++++ arch/riscv/kernel/cpu.c | 11 +++++++++++ arch/riscv/kernel/cpufeature.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+)arch/riscv/include/asm/hwcap.h +1
-0@@ -53,6 +53,17 @@#define RISCV_ISA_EXT_ZICSR 40#define RISCV_ISA_EXT_ZIFENCEI 41#define RISCV_ISA_EXT_ZIHPM 42 +#define RISCV_ISA_EXT_ZBC 43
arch/riscv/include/asm/hwcap.h line 66
Quoted 10 lines
arch/riscv/include/asm/hwcap.h +10
-0+#define RISCV_ISA_EXT_ZBKB 44 +#define RISCV_ISA_EXT_ZBKC 45 +#define RISCV_ISA_EXT_ZBKX 46 +#define RISCV_ISA_EXT_ZKND 47 +#define RISCV_ISA_EXT_ZKNE 48 +#define RISCV_ISA_EXT_ZKNH 49 +#define RISCV_ISA_EXT_ZKR 50 +#define RISCV_ISA_EXT_ZKSED 51 +#define RISCV_ISA_EXT_ZKSH 52 +#define RISCV_ISA_EXT_ZKT 53
Getting mighty close to running out of space in a u64 :)
I'd personally rather get my changes to this extensions stuff merged before adding more extensions, but I am clearly biased in terms of saving my own work there, and it'd not really be "fair" to hold it up on that basis alone.
However, since Palmer has now merged the "riscv,isa" deprecation [1], adding parsing of new ISA extensions, now requires documenting them in the extensions dt-binding. Can you please do that in v3?
Otherwise, this looks good to me:
Cheers,
Conor.
Re: [PATCH v2 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT
In reply to Samuel OrtizAm Mittwoch, 28. Juni 2023, 15:14:33 CEST schrieb Samuel Ortiz:
Quoted 16 lines
From: "Hongren (Zenithal) Zheng" <[email protected]>
Parse Zb/Zk related string from DT and output them to cpuinfo.
It is worth noting that the Scalar Crypto extension defines "zk" as a shorthand for the Zkn, Zkr and Zkt extensions. Since the Zkn one also implies the Zbkb, Zbkc and Zbkx extensions, simply passing the valid "zk" extension name through a DT will enable all of the Zbkb, Zbkc, Zbkx, Zkn, Zkr and Zkt extensions.
Also, since there currently is no mechanism to merge all enabled extensions, the generated cpuinfo output could be relatively large. For example, setting the "riscv,isa" DT property to "
rv64imafdc_zk_zks" will generate the following cpuinfo output:
"rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt".
Quoted 3 lines
Tested-by Jiatai He <[email protected]>Signed-off-by Samuel Ortiz <[email protected]>Signed-off-by Hongren (Zenithal) Zheng <[email protected]>
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PATCH v2 2/3 RISC-V: hwprobe: Expose Zbc and the scalar crypto extensions
In reply to Samuel OrtizZbc was missing from a previous Bit-Manipulation extension hwprobe patch.
Add all scalar crypto extensions bits, and define a macro for setting the hwprobe key/pair in a more readable way.
--- Documentation/riscv/hwprobe.rst | 33 ++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 11 ++++++++ arch/riscv/kernel/sys_riscv.c | 36 ++++++++++++++++----------- 3 files changed, 66 insertions(+), 14 deletions(-)
Documentation/riscv/hwprobe.rst +33 -0
@@ -72,11 +72,44 @@ The following keys are defined: extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined + in version 1.0 of the Bit-Manipulation ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBC`: The Zbc extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_EXT_ZBKB`: The Zbkb extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBKC`: The Zbkc extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBKX`: The Zbkx extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKND`: The Zknd extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKNE`: The Zkne extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKNH`: The Zknh extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKR`: The Zkr extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKSED`: The Zksed extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKSH`: The Zksh extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKT`: The Zkt extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors.
arch/riscv/include/uapi/asm/hwprobe.h +11 -0
@@ -29,6 +29,17 @@ struct riscv_hwprobe {#define RISCV_HWPROBE_EXT_ZBA (1 << 3)#define RISCV_HWPROBE_EXT_ZBB (1 << 4)#define RISCV_HWPROBE_EXT_ZBS (1 << 5) +#define RISCV_HWPROBE_EXT_ZBC (1 << 6) +#define RISCV_HWPROBE_EXT_ZBKB (1 << 7) +#define RISCV_HWPROBE_EXT_ZBKC (1 << 8) +#define RISCV_HWPROBE_EXT_ZBKX (1 << 9) +#define RISCV_HWPROBE_EXT_ZKND (1 << 10) +#define RISCV_HWPROBE_EXT_ZKNE (1 << 11) +#define RISCV_HWPROBE_EXT_ZKNH (1 << 12) +#define RISCV_HWPROBE_EXT_ZKR (1 << 13) +#define RISCV_HWPROBE_EXT_ZKSED (1 << 14) +#define RISCV_HWPROBE_EXT_ZKSH (1 << 15) +#define RISCV_HWPROBE_EXT_ZKT (1 << 16)#define RISCV_HWPROBE_KEY_CPUPERF_0 5#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
arch/riscv/kernel/sys_riscv.c +22 -14
@@ -145,20 +145,28 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,for_each_cpu (cpu, cpus) {struct riscv_isainfo *isainfo = &hart_isa[cpu]; -if (riscv_isa_extension_available (isainfo->isa,ZBA )) - pair->value |=RISCV_HWPROBE_EXT_ZBA ; -else - missing |=RISCV_HWPROBE_EXT_ZBA ; - -if (riscv_isa_extension_available (isainfo->isa,ZBB )) - pair->value |=RISCV_HWPROBE_EXT_ZBB ; -else - missing |=RISCV_HWPROBE_EXT_ZBB ; - -if (riscv_isa_extension_available (isainfo->isa,ZBS )) - pair->value |=RISCV_HWPROBE_EXT_ZBS ; -else - missing |=RISCV_HWPROBE_EXT_ZBS ; +#define SET_HWPROBE_EXT_PAIR (ext) \ + do { \ + if (riscv_isa_extension_available(isainfo->isa, ext)) \ + pair->value |= RISCV_HWPROBE_EXT_## ext; \ + else \ + missing |= RISCV_HWPROBE_EXT_## ext; \ + } while (false) \ + +SET_HWPROBE_EXT_PAIR (ZBA ); +SET_HWPROBE_EXT_PAIR (ZBB ); +SET_HWPROBE_EXT_PAIR (ZBC ); +SET_HWPROBE_EXT_PAIR (ZBS ); +SET_HWPROBE_EXT_PAIR (ZBKB ); +SET_HWPROBE_EXT_PAIR (ZBKC ); +SET_HWPROBE_EXT_PAIR (ZBKX ); +SET_HWPROBE_EXT_PAIR (ZKND ); +SET_HWPROBE_EXT_PAIR (ZKNE ); +SET_HWPROBE_EXT_PAIR (ZKNH ); +SET_HWPROBE_EXT_PAIR (ZKR ); +SET_HWPROBE_EXT_PAIR (ZKSED ); +SET_HWPROBE_EXT_PAIR (ZKSH ); +SET_HWPROBE_EXT_PAIR (ZKT ); }/* Now turn off reporting features if any CPU is missing it. */
Signature · 7 lines
2.41.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Re: [PATCH v2 2/3] RISC-V: hwprobe: Expose Zbc and the scalar crypto extensions
Quoted 8 lines · Samuel Ortiz
Zbc was missing from a previous Bit-Manipulation extension hwprobe patch.
Add all scalar crypto extensions bits, and define a macro for setting the hwprobe key/pair in a more readable way.
Reviewed-by Evan Green <[email protected]>Signed-off-by Samuel Ortiz <[email protected]>
Cheers,
Conor.
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Re: [PATCH v2 2/3] RISC-V: hwprobe: Expose Zbc and the scalar crypto extensions
In reply to Samuel OrtizAm Mittwoch, 28. Juni 2023, 15:14:34 CEST schrieb Samuel Ortiz:
Quoted 8 lines
Zbc was missing from a previous Bit-Manipulation extension hwprobe patch.
Add all scalar crypto extensions bits, and define a macro for setting the hwprobe key/pair in a more readable way.
Reviewed-by Evan Green <[email protected]>Signed-off-by Samuel Ortiz <[email protected]>
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PATCH v2 3/3 RISC-V: Implement archrandom when Zkr is available
In reply to Samuel OrtizThe Zkr extension is ratified and provides 16 bits of entropy seed when reading the SEED CSR.
We can implement arch_get_random_seed_longs() by doing multiple csrrw to that CSR and filling an unsigned long with valid entropy bits.
--- arch/riscv/include/asm/archrandom.h | 70 +++++++++++++++++++++++++++++ arch/riscv/include/asm/csr.h | 9 ++++ 2 files changed, 79 insertions(+) create mode 100644 arch/riscv/include/asm/archrandom.h
arch/riscv/include/asm/archrandom.h new file +70 -0
@@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Kernel interface for the RISCV arch_random_* functions +* +* Copyright (c) 2023 by Rivos Inc. +* +*/ + +#ifndef ASM_RISCV_ARCHRANDOM_H +#define ASM_RISCV_ARCHRANDOM_H + +#include <asm/csr.h> + +#define SEED_RETRY_LOOPS 10 + +static inline bool __must_check csr_seed_long (unsigned long *v) +{ +unsigned int retry =SEED_RETRY_LOOPS , valid_seeds =0 ; +const int needed_seeds =sizeof (long ) /sizeof (u16); +u16 *entropy = (u16 *)v; + +do { +/* +* The SEED CSR (0x015) must be accessed with a read-write +* instruction. +*/ +unsigned long csr_seed =csr_swap (CSR_SEED ,0 ); + +switch (csr_seed &SEED_OPST_MASK ) { +case SEED_OPST_ES16 : + entropy[valid_seeds++] = csr_seed &SEED_ENTROPY_MASK ; +if (valid_seeds == needed_seeds) +return true; +break ; + +case SEED_OPST_DEAD : +pr_err_once ("archrandom: Unrecoverable error\n" ); +return false; + +case SEED_OPST_BIST : +case SEED_OPST_WAIT : +default : +continue ; + } + }while (--retry); + +return false; +} + +static inline size_t __must_check arch_get_random_longs (unsigned long *v,size_t max_longs) +{ +return 0 ; +} + +static inline size_t __must_check arch_get_random_seed_longs (unsigned long *v,size_t max_longs) +{ +if (!max_longs) +return 0 ; + +/* +* If Zkr is supported and csr_seed_long succeeds, we return one long +* worth of entropy. +*/ +if (riscv_has_extension_likely (RISCV_ISA_EXT_ZKR ) &&csr_seed_long (v)) +return 1 ; + +return 0 ; +} + +#endif /* ASM_RISCV_ARCHRANDOM_H */
arch/riscv/include/asm/csr.h +9 -0
@@ -389,6 +389,15 @@#define CSR_VTYPE 0xc21#define CSR_VLENB 0xc22 +/* Scalar Crypto Extension - Entropy */ +#define CSR_SEED 0x015 +#define SEED_OPST_MASK _AC(0xC0000000, UL) +#define SEED_OPST_BIST _AC(0x00000000, UL) +#define SEED_OPST_WAIT _AC(0x40000000, UL) +#define SEED_OPST_ES16 _AC(0x80000000, UL) +#define SEED_OPST_DEAD _AC(0xC0000000, UL) +#define SEED_ENTROPY_MASK _AC(0xFFFF, UL) +#ifdef CONFIG_RISCV_M_MODE # define CSR_STATUS CSR_MSTATUS# define CSR_IE CSR_MIE
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2.41.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Re: [PATCH v2 3/3] RISC-V: Implement archrandom when Zkr is available
Quoted 7 lines · Samuel Ortiz
The Zkr extension is ratified and provides 16 bits of entropy seed when reading the SEED CSR.
We can implement
arch_get_random_seed_longs()by doing multiple csrrw to that CSR and filling an unsigned long with valid entropy bits.Signed-off-by Samuel Ortiz <[email protected]>
Cheers,
Conor.
Re: [PATCH v2 3/3] RISC-V: Implement archrandom when Zkr is available
In reply to Samuel OrtizQuoted 42 lines · Samuel Ortiz
The Zkr extension is ratified and provides 16 bits of entropy seed when reading the SEED CSR.
We can implement
arch_get_random_seed_longs()by doing multiple csrrw to that CSR and filling an unsigned long with valid entropy bits.Signed-off-by Samuel Ortiz <[email protected]>--- arch/riscv/include/asm/archrandom.h | 70 +++++++++++++++++++++++++++++ arch/riscv/include/asm/csr.h | 9 ++++ 2 files changed, 79 insertions(+) create mode 100644 arch/riscv/include/asm/archrandom.harch/riscv/include/asm/archrandom.h new file +22
-0@@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Kernel interface for the RISCV arch_random_* functions +* +* Copyright (c) 2023 by Rivos Inc. +* +*/ + +#ifndef ASM_RISCV_ARCHRANDOM_H +#define ASM_RISCV_ARCHRANDOM_H + +#include <asm/csr.h> + +#define SEED_RETRY_LOOPS 10 + +static inline bool __must_check csr_seed_long (unsigned long *v) +{ +unsigned int retry =SEED_RETRY_LOOPS , valid_seeds =0 ; +const int needed_seeds =sizeof (long ) /sizeof (u16); +u16 *entropy = (u16 *)v; + + do {
arch/riscv/include/asm/archrandom.h line 32
Quoted 10 lines
arch/riscv/include/asm/archrandom.h new file +10
-0+/* +* The SEED CSR (0x015) must be accessed with a read-write +* instruction. +*/ +unsigned long csr_seed =csr_swap (CSR_SEED ,0 ); + +switch (csr_seed &SEED_OPST_MASK ) { +case SEED_OPST_ES16 : + entropy[valid_seeds++] = csr_seed &SEED_ENTROPY_MASK ; +if (valid_seeds == needed_seeds)
max_longs = 1? needed_seeds only could be 2/4.
arch/riscv/include/asm/archrandom.h line 37
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arch/riscv/include/asm/archrandom.h new file +5
-0+return true; +break ; + +case SEED_OPST_DEAD : +pr_err_once ("archrandom: Unrecoverable error\n" );
Do we need this pr_err? Could we treat it as a return false? Yes, it's a hardware problem, but not serious.
Quoted 10 lines
arch/riscv/include/asm/archrandom.h new file +10
-0+return false; + +case SEED_OPST_BIST : +case SEED_OPST_WAIT : +default : +continue ; + } + }while (--retry); + +return false;
arch/riscv/include/asm/archrandom.h
Quoted 10 lines
arch/riscv/include/asm/archrandom.h new file +10
-0+} + +static inline size_t __must_check arch_get_random_longs (unsigned long *v,size_t max_longs) +{ +return 0 ; +} + +static inline size_t __must_check arch_get_random_seed_longs (unsigned long *v,size_t max_longs) +{ +if (!max_longs )
if (max_longs == 1) ?
Quoted 34 lines
arch/riscv/include/asm/archrandom.h new file +13
-0+return 0 ; + +/* +* If Zkr is supported and csr_seed_long succeeds, we return one long +* worth of entropy. +*/ +if (riscv_has_extension_likely (RISCV_ISA_EXT_ZKR ) &&csr_seed_long (v)) +return 1 ; + + return 0; +} + +#endif /* ASM_RISCV_ARCHRANDOM_H */ arch/riscv/include/asm/csr.h +9
-1@@ -389,6 +389,15 @@#define CSR_VTYPE 0xc21#define CSR_VLENB 0xc22 +/* Scalar Crypto Extension - Entropy */ +#define CSR_SEED 0x015 +#define SEED_OPST_MASK _AC(0xC0000000, UL) +#define SEED_OPST_BIST _AC(0x00000000, UL) +#define SEED_OPST_WAIT _AC(0x40000000, UL) +#define SEED_OPST_ES16 _AC(0x80000000, UL) +#define SEED_OPST_DEAD _AC(0xC0000000, UL) +#define SEED_ENTROPY_MASK _AC(0xFFFF, UL) +#ifdef CONFIG_RISCV_M_MODE # define CSR_STATUS CSR_MSTATUS# define CSR_IE CSR_MIE --
Quoted 2 lines
2.41.0
Signature · 7 lines
Best Regards Guo Ren _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv