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usb: dwc2: add new compatible for Intel SoCFPGA Stratix10 platform

PATCH Superseded Meng Li 2 participants 4 messages Jul 18, 2023

Subsystems (2)
Device tree bindings Arm/socfpga architecture

v1 of 2 Superseded Latest is v2 →

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Meng Li

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#0 lore raw

PATCH 1/1 usb: dwc2: add new compatible for Intel SoCFPGA Stratix10 platform

Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on the Stratix platform also does not support clock-gating. The commit 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's Agilex") had fixed this issue. So, add the essential compatible to also use the specific data on Stratix10 platform.

Signed-off-by Meng Li <[email protected]>
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +2 -2
index ea788a920eab..b8dd5509c214 100644
@@ -490,7 +490,7 @@ usbphy0: usbphy@0 {
 		};
 
 		usb0: usb@ffb00000 {
-			compatible = "snps,dwc2";
+			compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
 			reg = <0xffb00000 0x40000>;
 			interrupts = <0 93 4>;
 			phys = <&usbphy0>;

@@ -504,7 +504,7 @@ usb0: usb@ffb00000 {
 		};
 
 		usb1: usb@ffb40000 {
-			compatible = "snps,dwc2";
+			compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
 			reg = <0xffb40000 0x40000>;
 			interrupts = <0 94 4>;
 			phys = <&usbphy0>;
Signature · 1 line
2.34.1
#1 lore raw
Quoted 16 lines · Meng Li

Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on the Stratix platform also does not support clock-gating. The commit 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's Agilex") had fixed this issue. So, add the essential compatible to also use the specific data on Stratix10 platform.

Signed-off-by Meng Li <[email protected]>
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +0 -0
index ea788a920eab..b8dd5509c214 100644

arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi usbphy0: usbphy@0 { · line 493

Quoted 5 lines
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +1 -1
@@ -490,7 +490,7 @@ usbphy0: usbphy@0 {
 		};
 
 		usb0: usb@ffb00000 {
-			compatible = "snps,dwc2";
+			compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";

You miss SoC specific compatible.

Best regards,
Krzysztof

author
#2 lore raw
Quoted 36 lines

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Tuesday, July 18, 2023 2:11 PM
To: Li, Meng <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: [email protected]
Subject: Re: [PATCH] usb: dwc2: add new compatible for Intel SoCFPGA Stratix10 platform

CAUTION: This email comes from a non Wind River email account! Do not click links or open attachments unless you recognize the sender and know the content is safe.

Quoted 19 lines · Meng Li

Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on the Stratix platform also does not support clock-gating. The commit 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's Agilex") had fixed this issue. So, add the essential compatible to also use the specific data on Stratix10 platform.

Signed-off-by Meng Li <[email protected]>
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +0 -0
index ea788a920eab..b8dd5509c214 100644
@@ -490,7 +490,7 @@ usbphy0: usbphy@0 {
              };
Quoted 7 lines

arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi usbphy0: usbphy@0 {

Quoted 4 lines
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +2 -1
              usb0: usb@ffb00000 {
-                     compatible = "snps,dwc2";
+                     compatible = "intel,socfpga-agilex-hsotg",
+ "snps,dwc2";

You miss SoC specific compatible.

Sorry! I don't understand what do you mean about SoC specific compatible. I think agilex is the soc specific.
Could you please show your example?

Thanks,
LImeng

Quoted 2 lines

Best regards,
Krzysztof

#3 lore raw
Quoted 44 lines · Meng
Quoted 36 lines

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Tuesday, July 18, 2023 2:11 PM
To: Li, Meng <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: [email protected]
Subject: Re: [PATCH] usb: dwc2: add new compatible for Intel SoCFPGA Stratix10 platform

CAUTION: This email comes from a non Wind River email account! Do not click links or open attachments unless you recognize the sender and know the content is safe.

Quoted 19 lines · Meng Li

Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on the Stratix platform also does not support clock-gating. The commit 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's Agilex") had fixed this issue. So, add the essential compatible to also use the specific data on Stratix10 platform.

Signed-off-by Meng Li <[email protected]>
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +0 -0
index ea788a920eab..b8dd5509c214 100644
@@ -490,7 +490,7 @@ usbphy0: usbphy@0 {
              };
Quoted 7 lines

arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi usbphy0: usbphy@0 {

Quoted 4 lines
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +2 -1
              usb0: usb@ffb00000 {
-                     compatible = "snps,dwc2";
+                     compatible = "intel,socfpga-agilex-hsotg",
+ "snps,dwc2";

You miss SoC specific compatible.

Quoted 3 lines

Sorry! I don't understand what do you mean about SoC specific compatible. I think agilex is the soc specific.
Could you please show your example?

But this is stratix.

rk3128.dtsi

Or many other devices in Linux kernel.

Best regards,
Krzysztof