Extend i915/perf for testing Xe OA

index 432bd87ca401..bec8b82dc8bb 100644
@@ -3,8 +3,8 @@
  * Copyright © 2023 Intel Corporation
  */
 
-#ifndef _UAPI_XE_DRM_H_
-#define _UAPI_XE_DRM_H_
+#ifndef _XE_DRM_H_
+#define _XE_DRM_H_
 
 #include "drm.h"
 

@@ -29,7 +29,7 @@ extern "C" {
  * redefine the interface more easily than an ever growing struct of
  * increasing complexity, and for large parts of that interface to be
  * entirely optional. The downside is more pointer chasing; chasing across
- * the __user boundary with pointers encapsulated inside u64.
+ * the boundary with pointers encapsulated inside u64.
  *
  * Example chaining:
  *

@@ -101,6 +101,9 @@ struct xe_user_extension {
 #define DRM_XE_WAIT_USER_FENCE		0x0b
 #define DRM_XE_VM_MADVISE		0x0c
 #define DRM_XE_ENGINE_GET_PROPERTY	0x0d
+#define DRM_XE_OA_OPEN			0x36
+#define DRM_XE_OA_ADD_CONFIG		0x37
+#define DRM_XE_OA_REMOVE_CONFIG		0x38
 
 /* Must be kept compact -- no holes */
 #define DRM_IOCTL_XE_DEVICE_QUERY		DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query)

@@ -117,6 +120,9 @@ struct xe_user_extension {
 #define DRM_IOCTL_XE_ENGINE_SET_PROPERTY	 DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_SET_PROPERTY, struct drm_xe_engine_set_property)
 #define DRM_IOCTL_XE_WAIT_USER_FENCE		DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
 #define DRM_IOCTL_XE_VM_MADVISE			 DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise)
+#define DRM_IOCTL_XE_OA_OPEN			DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OA_OPEN, struct drm_xe_oa_open_param)
+#define DRM_IOCTL_XE_OA_ADD_CONFIG		DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OA_ADD_CONFIG, struct drm_xe_oa_config)
+#define DRM_IOCTL_XE_OA_REMOVE_CONFIG		DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OA_REMOVE_CONFIG, __u64)
 
 /**
  * enum drm_xe_memory_class - Supported memory classes.

@@ -223,7 +229,8 @@ struct drm_xe_query_config {
 #define XE_QUERY_CONFIG_GT_COUNT		4
 #define XE_QUERY_CONFIG_MEM_REGION_COUNT	5
 #define XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY	6
-#define XE_QUERY_CONFIG_NUM_PARAM		(XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY + 1)
+#define XE_QUERY_OA_IOCTL_VERSION		7
+#define XE_QUERY_CONFIG_NUM_PARAM		(XE_QUERY_OA_IOCTL_VERSION + 1)
 	/** @info: array of elements containing the config info */
 	__u64 info[];
 };

@@ -242,11 +249,13 @@ struct drm_xe_query_gts {
 	/** @pad: MBZ */
 	__u32 pad;
 
-	/*
+	/**
+	 * @gts: The GTs returned for this device
+	 *
+	 * TODO: convert drm_xe_query_gt to proper kernel-doc.
 	 * TODO: Perhaps info about every mem region relative to this GT? e.g.
 	 * bandwidth between this GT and remote region?
 	 */
-
 	struct drm_xe_query_gt {
 #define XE_QUERY_GT_TYPE_MAIN		0
 #define XE_QUERY_GT_TYPE_REMOTE		1

@@ -258,6 +267,7 @@ struct drm_xe_query_gts {
 		__u64 native_mem_regions;	/* bit mask of instances from drm_xe_query_mem_usage */
 		__u64 slow_mem_regions;		/* bit mask of instances from drm_xe_query_mem_usage */
 		__u64 inaccessible_mem_regions;	/* bit mask of instances from drm_xe_query_mem_usage */
+		__u64 oa_timestamp_freq;
 		__u64 reserved[8];
 	} gts[];
 };

@@ -697,6 +707,7 @@ struct drm_xe_engine_class_instance {
 
 	__u16 engine_instance;
 	__u16 gt_id;
+	__u16 oa_unit_id;
 };
 
 struct drm_xe_engine_create {

@@ -799,7 +810,7 @@ struct drm_xe_exec {
 	/** @extensions: Pointer to the first extension struct, if any */
 	__u64 extensions;
 
-	/** @vm_id: VM ID to run batch buffer in */
+	/** @engine_id: Engine ID for the batch buffer */
 	__u32 engine_id;
 
 	/** @num_syncs: Amount of struct drm_xe_sync in array. */

@@ -852,8 +863,9 @@ struct drm_xe_mmio {
  * struct drm_xe_wait_user_fence - wait user fence
  *
  * Wait on user fence, XE will wakeup on every HW engine interrupt in the
- * instances list and check if user fence is complete:
- * (*addr & MASK) OP (VALUE & MASK)
+ * instances list and check if user fence is complete::
+ *
+ *	(*addr & MASK) OP (VALUE & MASK)
  *
  * Returns to user on user fence completion or timeout.
  */

@@ -901,8 +913,20 @@ struct drm_xe_wait_user_fence {
 #define DRM_XE_UFENCE_WAIT_U64		0xffffffffffffffffu
 	/** @mask: comparison mask */
 	__u64 mask;
-
-	/** @timeout: how long to wait before bailing, value in jiffies */
+	/**
+	 * @timeout: how long to wait before bailing, value in nanoseconds.
+	 * Without DRM_XE_UFENCE_WAIT_ABSTIME flag set (relative timeout)
+	 * it contains timeout expressed in nanoseconds to wait (fence will
+	 * expire at now() + timeout).
+	 * When DRM_XE_UFENCE_WAIT_ABSTIME flat is set (absolute timeout) wait
+	 * will end at timeout (uses system MONOTONIC_CLOCK).
+	 * Passing negative timeout leads to neverending wait.
+	 *
+	 * On relative timeout this value is updated with timeout left
+	 * (for restarting the call in case of signal delivery).
+	 * On absolute timeout this value stays intact (restarted call still
+	 * expire at the same point of time).
+	 */
 	__s64 timeout;
 
 	/**

@@ -987,8 +1011,255 @@ struct drm_xe_vm_madvise {
 	__u64 reserved[2];
 };
 
+enum drm_xe_oa_format {
+	XE_OA_FORMAT_C4_B8 = 7,
+
+	/* Gen8+ */
+	XE_OA_FORMAT_A12,
+	XE_OA_FORMAT_A12_B8_C8,
+	XE_OA_FORMAT_A32u40_A4u32_B8_C8,
+
+	/* DG2 */
+	XE_OAR_FORMAT_A32u40_A4u32_B8_C8,
+	XE_OA_FORMAT_A24u40_A14u32_B8_C8,
+
+	/* MTL OAM */
+	XE_OAM_FORMAT_MPEC8u64_B8_C8,
+	XE_OAM_FORMAT_MPEC8u32_B8_C8,
+
+	XE_OA_FORMAT_MAX	    /* non-ABI */
+};
+
+enum drm_xe_oa_property_id {
+	/**
+	 * Open the stream for a specific engine id (as used with
+	 * drm_xe_exec). A stream opened for a specific engine id this way
+	 * won't typically require root privileges.
+	 */
+	DRM_XE_OA_PROP_ENGINE_ID = 1,
+
+	/**
+	 * A value of 1 requests the inclusion of raw OA unit reports as
+	 * part of stream samples.
+	 */
+	DRM_XE_OA_PROP_SAMPLE_OA,
+
+	/**
+	 * The value specifies which set of OA unit metrics should be
+	 * configured, defining the contents of any OA unit reports.
+	 */
+	DRM_XE_OA_PROP_OA_METRICS_SET,
+
+	/**
+	 * The value specifies the size and layout of OA unit reports.
+	 */
+	DRM_XE_OA_PROP_OA_FORMAT,
+
+	/**
+	 * Specifying this property implicitly requests periodic OA unit
+	 * sampling and (at least on Haswell) the sampling frequency is derived
+	 * from this exponent as follows:
+	 *
+	 *   80ns * 2^(period_exponent + 1)
+	 */
+	DRM_XE_OA_PROP_OA_EXPONENT,
+
+	/**
+	 * Specifying this property is only valid when specify a context to
+	 * filter with DRM_XE_OA_PROP_ENGINE_ID. Specifying this property
+	 * will hold preemption of the particular engine we want to gather
+	 * performance data about.
+	 */
+	DRM_XE_OA_PROP_HOLD_PREEMPTION,
+
+	/**
+	 * Specifying this pins all contexts to the specified SSEU power
+	 * configuration for the duration of the recording.
+	 *
+	 * This parameter's value is a pointer to a struct
+	 * drm_xe_gem_context_param_sseu (TBD).
+	 */
+	DRM_XE_OA_PROP_GLOBAL_SSEU,
+
+	/**
+	 * This optional parameter specifies the timer interval in nanoseconds
+	 * at which the xe driver will check the OA buffer for available data.
+	 * Minimum allowed value is 100 microseconds. A default value is used by
+	 * the driver if this parameter is not specified. Note that larger timer
+	 * values will reduce cpu consumption during OA perf captures. However,
+	 * excessively large values would potentially result in OA buffer
+	 * overwrites as captures reach end of the OA buffer.
+	 */
+	DRM_XE_OA_PROP_POLL_OA_PERIOD,
+
+	/**
+	 * Multiple engines may be mapped to the same OA unit. The OA unit is
+	 * identified by class:instance of any engine mapped to it.
+	 *
+	 * This parameter specifies the engine class and must be passed along
+	 * with DRM_XE_OA_PROP_OA_ENGINE_INSTANCE.
+	 */
+	DRM_XE_OA_PROP_OA_ENGINE_CLASS,
+
+	/**
+	 * This parameter specifies the engine instance and must be passed along
+	 * with DRM_XE_OA_PROP_OA_ENGINE_CLASS.
+	 */
+	DRM_XE_OA_PROP_OA_ENGINE_INSTANCE,
+
+	DRM_XE_OA_PROP_MAX /* non-ABI */
+};
+
+struct drm_xe_oa_open_param {
+	__u32 flags;
+#define XE_OA_FLAG_FD_CLOEXEC	BIT(0)
+#define XE_OA_FLAG_FD_NONBLOCK	BIT(1)
+#define XE_OA_FLAG_DISABLED	BIT(2)
+
+	/** The number of u64 (id, value) pairs */
+	__u32 num_properties;
+
+	/**
+	 * Pointer to array of u64 (id, value) pairs configuring the stream
+	 * to open.
+	 */
+	__u64 properties_ptr;
+};
+
+/*
+ * Enable data capture for a stream that was either opened in a disabled state
+ * via I915_PERF_FLAG_DISABLED or was later disabled via
+ * I915_PERF_IOCTL_DISABLE.
+ *
+ * It is intended to be cheaper to disable and enable a stream than it may be
+ * to close and re-open a stream with the same configuration.
+ *
+ * It's undefined whether any pending data for the stream will be lost.
+ */
+#define XE_OA_IOCTL_ENABLE	_IO('i', 0x0)
+
+/*
+ * Disable data capture for a stream.
+ *
+ * It is an error to try and read a stream that is disabled.
+ */
+#define XE_OA_IOCTL_DISABLE	_IO('i', 0x1)
+
+/*
+ * Change metrics_set captured by a stream.
+ *
+ * If the stream is bound to a specific context, the configuration change
+ * will performed __inline__ with that context such that it takes effect before
+ * the next execbuf submission.
+ *
+ * Returns the previously bound metrics set id, or a negative error code.
+ */
+#define XE_OA_IOCTL_CONFIG	_IO('i', 0x2)
+
+struct drm_xe_oa_record_header {
+	__u32 type;
+	__u16 pad;
+	__u16 size;
+};
+
+enum drm_xe_oa_record_type {
+
+	/**
+	 * Samples are the work horse record type whose contents are
+	 * extensible and defined when opening an xe oa stream based on the
+	 * given properties.
+	 *
+	 * Boolean properties following the naming convention
+	 * DRM_XE_OA_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
+	 * every sample.
+	 *
+	 * The order of these sample properties given by userspace has no
+	 * affect on the ordering of data within a sample. The order is
+	 * documented here.
+	 *
+	 * struct {
+	 *     struct drm_xe_oa_record_header header;
+	 *
+	 *     { u32 oa_report[]; } && DRM_XE_OA_PROP_SAMPLE_OA
+	 * };
+	 */
+	DRM_XE_OA_RECORD_SAMPLE = 1,
+
+	/**
+	 * Indicates that one or more OA reports were not written by the
+	 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
+	 * command collides with periodic sampling - which would be more likely
+	 * at higher sampling frequencies.
+	 */
+	DRM_XE_OA_RECORD_OA_REPORT_LOST = 2,
+
+	/**
+	 * An error occurred that resulted in all pending OA reports being lost.
+	 */
+	DRM_XE_OA_RECORD_OA_BUFFER_LOST = 3,
+
+	DRM_XE_OA_RECORD_MAX /* non-ABI */
+};
+
+struct drm_xe_oa_config {
+	/**
+	 * @uuid:
+	 *
+	 * String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
+	 */
+	char uuid[36];
+
+	/**
+	 * @n_mux_regs:
+	 *
+	 * Number of mux regs in &mux_regs_ptr.
+	 */
+	__u32 n_mux_regs;
+
+	/**
+	 * @n_boolean_regs:
+	 *
+	 * Number of boolean regs in &boolean_regs_ptr.
+	 */
+	__u32 n_boolean_regs;
+
+	/**
+	 * @n_flex_regs:
+	 *
+	 * Number of flex regs in &flex_regs_ptr.
+	 */
+	__u32 n_flex_regs;
+
+	/**
+	 * @mux_regs_ptr:
+	 *
+	 * Pointer to tuples of u32 values (register address, value) for mux
+	 * registers.  Expected length of buffer is (2 * sizeof(u32) *
+	 * &n_mux_regs).
+	 */
+	__u64 mux_regs_ptr;
+
+	/**
+	 * @boolean_regs_ptr:
+	 *
+	 * Pointer to tuples of u32 values (register address, value) for mux
+	 * registers.  Expected length of buffer is (2 * sizeof(u32) *
+	 * &n_boolean_regs).
+	 */
+	__u64 boolean_regs_ptr;
+
+	/**
+	 * @flex_regs_ptr:
+	 *
+	 * Pointer to tuples of u32 values (register address, value) for mux
+	 * registers.  Expected length of buffer is (2 * sizeof(u32) *
+	 * &n_flex_regs).
+	 */
+	__u64 flex_regs_ptr;
+};
+
 #if defined(__cplusplus)
 }
 #endif
 
-#endif /* _UAPI_XE_DRM_H_ */
+#endif /* _XE_DRM_H_ */

index f535ad8534dd..b8f973b0931b 100644
@@ -503,6 +503,14 @@ uint32_t xe_min_page_size(int fd, uint64_t region)
  */
 xe_dev_FN(xe_config, config, struct drm_xe_query_config *);
 
+/**
+ * xe_gts:
+ * @fd: xe device fd
+ *
+ * Returns query gts of xe device @fd.
+ */
+xe_dev_FN(xe_gts, gts, struct drm_xe_query_gts *);
+
 /**
  * xe_number_hw_engine:
  * @fd: xe device fd

index 68ca5a680c6e..8d3f0983166e 100644
@@ -88,6 +88,7 @@ const char *xe_region_name(uint64_t region);
 uint16_t xe_region_class(int fd, uint64_t region);
 uint32_t xe_min_page_size(int fd, uint64_t region);
 struct drm_xe_query_config *xe_config(int fd);
+struct drm_xe_query_gts *xe_gts(int fd);
 unsigned int xe_number_hw_engines(int fd);
 bool xe_has_vram(int fd);
 uint64_t xe_vram_size(int fd, int gt);

index ddadb53b61c8..5b08c983918a 100644
@@ -37,10 +37,12 @@
 
 #include <i915_drm.h>
 
+#include "drmtest.h"
 #include "i915_pciids.h"
-
 #include "intel_chipset.h"
+#include "linux_scaffold.h"
 #include "perf.h"
+#include "xe/xe_query.h"
 
 #include "i915_perf_metrics_hsw.h"
 #include "i915_perf_metrics_bdw.h"

@@ -68,8 +70,6 @@
 #include "i915_perf_metrics_mtlgt2.h"
 #include "i915_perf_metrics_mtlgt3.h"
 
-#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
-
 static int
 perf_ioctl(int fd, unsigned long request, void *arg)
 {

@@ -609,6 +609,54 @@ intel_sysfs_attr_id_to_name(int sysfs_dirfd, intel_sysfs_attr_id id, int gt)
 		intel_sysfs_attr_name[0][id];
 }
 
+static struct intel_perf *
+xe_perf_for_fd(int drm_fd, int gt)
+{
+	u32 device_id;
+	u32 device_revision = 0;
+	u32 timestamp_frequency;
+	u64 gt_min_freq;
+	u64 gt_max_freq;
+	struct intel_perf *ret;
+	int sysfs_dir_fd = open_master_sysfs_dir(drm_fd);
+	char path_min[64], path_max[64];
+
+	if (sysfs_dir_fd < 0) {
+		igt_warn("open_master_sysfs_dir failed\n");
+		return NULL;
+	}
+
+	if (IS_PONTEVECCHIO(xe_dev_id(drm_fd))) {
+		sprintf(path_min, "device/tile%d/gt%d/freq_min", gt, gt);
+		sprintf(path_max, "device/tile%d/gt%d/freq_max", gt, gt);
+	} else {
+		sprintf(path_min, "device/tile0/gt%d/freq_min", gt);
+		sprintf(path_max, "device/tile0/gt%d/freq_max", gt);
+	}
+
+	if (!read_sysfs(sysfs_dir_fd, path_min, &gt_min_freq) ||
+	    !read_sysfs(sysfs_dir_fd, path_max, &gt_max_freq)) {
+		igt_warn("Unable to read freqs from sysfs\n");
+		close(sysfs_dir_fd);
+		return NULL;
+	}
+	close(sysfs_dir_fd);
+
+	device_id = intel_get_drm_devid(drm_fd);
+	timestamp_frequency = xe_gts(drm_fd)->gts[0].oa_timestamp_freq;
+
+	ret = intel_perf_for_devinfo(device_id,
+				     device_revision,
+				     timestamp_frequency,
+				     gt_min_freq * 1000000,
+				     gt_max_freq * 1000000,
+				     NULL);
+	if (!ret)
+		igt_warn("intel_perf_for_devinfo failed\n");
+
+	return ret;
+}
+
 struct intel_perf *
 intel_perf_for_fd(int drm_fd, int gt)
 {

@@ -621,6 +669,9 @@ intel_perf_for_fd(int drm_fd, int gt)
 	struct intel_perf *ret;
 	int sysfs_dir_fd = open_master_sysfs_dir(drm_fd);
 
+	if (is_xe_device(drm_fd))
+		return xe_perf_for_fd(drm_fd, gt);
+
 	if (sysfs_dir_fd < 0)
 		return NULL;
 

index 5b08c983918a..0bb1aa59045c 100644
@@ -38,8 +38,10 @@
 #include <i915_drm.h>
 
 #include "drmtest.h"
+#include "igt_aux.h"
 #include "i915_pciids.h"
 #include "intel_chipset.h"
+#include "ioctl_wrappers.h"
 #include "linux_scaffold.h"
 #include "perf.h"
 #include "xe/xe_query.h"

@@ -609,6 +611,108 @@ intel_sysfs_attr_id_to_name(int sysfs_dirfd, intel_sysfs_attr_id id, int gt)
 		intel_sysfs_attr_name[0][id];
 }
 
+struct drm_i915_query_topology_info *
+xe_fill_i915_topology_info(int drm_fd)
+{
+	struct drm_i915_query_topology_info i915_topinfo = {};
+	struct drm_i915_query_topology_info *i915_topo;
+	struct drm_xe_query_topology_mask *xe_topo;
+	int total_size, pos = 0;
+	u8 *ptr;
+	struct drm_xe_device_query query = {
+		.extensions = 0,
+		.query = DRM_XE_DEVICE_QUERY_GT_TOPOLOGY,
+		.size = 0,
+		.data = 0,
+	};
+
+	/* Fixed fields, see fill_topology_info() and intel_sseu_set_info() in i915 */
+	i915_topinfo.max_slices = 1;			/* always 1 */
+	if (IS_PONTEVECCHIO(xe_dev_id(drm_fd))) {
+		i915_topinfo.max_subslices = 64;
+		i915_topinfo.max_eus_per_subslice = 8;
+	} else if (intel_graphics_ver(xe_dev_id(drm_fd)) >= IP_VER(12, 50)) {
+		i915_topinfo.max_subslices = 32;
+		i915_topinfo.max_eus_per_subslice = 16;
+	} else if (intel_graphics_ver(xe_dev_id(drm_fd)) >= IP_VER(12, 0)) {
+		i915_topinfo.max_subslices = 6;
+		i915_topinfo.max_eus_per_subslice = 16;
+	} else {
+		igt_assert(0);
+	}
+	i915_topinfo.subslice_offset = 1;		/* always 1 */
+	i915_topinfo.subslice_stride = DIV_ROUND_UP(i915_topinfo.max_subslices, 8);
+	i915_topinfo.eu_offset = i915_topinfo.subslice_offset + i915_topinfo.subslice_stride;
+	i915_topinfo.eu_stride = DIV_ROUND_UP(i915_topinfo.max_eus_per_subslice, 8);
+
+	/* Allocate and start filling the struct to return */
+	total_size = sizeof(i915_topinfo) + i915_topinfo.eu_offset +
+			i915_topinfo.max_subslices * i915_topinfo.eu_stride;
+	i915_topo = malloc(total_size);
+	igt_assert(i915_topo);
+
+	memcpy(i915_topo, &i915_topinfo, sizeof(i915_topinfo));
+	ptr = (u8 *)i915_topo + sizeof(i915_topinfo);
+	*ptr++ = 0x1;					/* slice mask */
+
+	/* Get xe topology masks */
+	igt_assert_eq(igt_ioctl(drm_fd, DRM_IOCTL_XE_DEVICE_QUERY, &query), 0);
+	igt_assert_neq(query.size, 0);
+
+	xe_topo = malloc(query.size);
+	igt_assert(xe_topo);
+
+	query.data = to_user_pointer(xe_topo);
+	igt_assert_eq(igt_ioctl(drm_fd, DRM_IOCTL_XE_DEVICE_QUERY, &query), 0);
+	igt_debug("Topology size: %d\n", query.size);
+
+	while (query.size >= sizeof(struct drm_xe_query_topology_mask)) {
+		struct drm_xe_query_topology_mask *topo =
+			(struct drm_xe_query_topology_mask *)((unsigned char *)xe_topo + pos);
+		int i, sz = sizeof(struct drm_xe_query_topology_mask) + topo->num_bytes;
+		u64 geom_mask, compute_mask;
+
+		igt_debug(" gt_id: %d type: %d n:%d [%d] ",
+			  topo->gt_id, topo->type, topo->num_bytes, sz);
+		for (int j = 0; j < topo->num_bytes; j++)
+			igt_debug(" %02x", topo->mask[j]);
+		igt_debug("\n");
+
+		/* i915 only returns topology for gt 0, do the same here */
+		if (topo->gt_id)
+			continue;
+
+		/* Follow the same order as in xe query_gt_topology() */
+		switch (topo->type) {
+		case XE_TOPO_DSS_GEOMETRY:
+			igt_assert_lte(i915_topo->subslice_stride, 8);	/* Fit in u64 mask */
+			memcpy(&geom_mask, topo->mask, i915_topo->subslice_stride);
+			break;
+		case XE_TOPO_DSS_COMPUTE:
+			memcpy(&compute_mask, topo->mask, i915_topo->subslice_stride);
+			geom_mask |= compute_mask;
+			memcpy(ptr, &geom_mask, i915_topo->subslice_stride);
+			ptr += i915_topo->subslice_stride;
+			break;
+		case XE_TOPO_EU_PER_DSS:
+			for (i = 0; i < i915_topo->max_subslices; i++) {
+				memcpy(ptr, topo->mask, i915_topo->eu_stride);
+				ptr += i915_topo->eu_stride;
+			}
+			break;
+		default:
+			igt_assert(0);
+		}
+
+		query.size -= sz;
+		pos += sz;
+	}
+
+	free(xe_topo);
+
+	return i915_topo;
+}
+
 static struct intel_perf *
 xe_perf_for_fd(int drm_fd, int gt)
 {

@@ -617,6 +721,7 @@ xe_perf_for_fd(int drm_fd, int gt)
 	u32 timestamp_frequency;
 	u64 gt_min_freq;
 	u64 gt_max_freq;
+	struct drm_i915_query_topology_info *topology;
 	struct intel_perf *ret;
 	int sysfs_dir_fd = open_master_sysfs_dir(drm_fd);
 	char path_min[64], path_max[64];

@@ -645,15 +750,23 @@ xe_perf_for_fd(int drm_fd, int gt)
 	device_id = intel_get_drm_devid(drm_fd);
 	timestamp_frequency = xe_gts(drm_fd)->gts[0].oa_timestamp_freq;
 
+	topology = xe_fill_i915_topology_info(drm_fd);
+	if (!topology) {
+		igt_warn("xe_fill_i915_topology_info failed\n");
+		return NULL;
+	}
+
 	ret = intel_perf_for_devinfo(device_id,
 				     device_revision,
 				     timestamp_frequency,
 				     gt_min_freq * 1000000,
 				     gt_max_freq * 1000000,
-				     NULL);
+				     topology);
 	if (!ret)
 		igt_warn("intel_perf_for_devinfo failed\n");
 
+	free(topology);
+
 	return ret;
 }
 

index 8a71ac635e78..f3df578ddc5f 100644
@@ -318,6 +318,7 @@ intel_perf_devinfo_eu_available(const struct intel_perf_devinfo *devinfo,
 	return (devinfo->eu_masks[subslice_offset + eu / 8] & (1U << eu % 8)) != 0;
 }
 
+struct drm_i915_query_topology_info *xe_fill_i915_topology_info(int drm_fd);
 struct intel_perf *intel_perf_for_fd(int drm_fd, int gt);
 struct intel_perf *intel_perf_for_devinfo(uint32_t device_id,
 					  uint32_t revision,

index 3565d61cc393..6ab371857847 100644
@@ -45,6 +45,8 @@
 #include "igt_perf.h"
 #include "igt_sysfs.h"
 #include "drm.h"
+#include "xe/xe_query.h"
+
 /**
  * TEST: perf
  * Description: Test the i915 perf metrics streaming interface

@@ -419,6 +421,12 @@ static struct oa_format mtl_oa_formats[I915_OA_FORMAT_MAX] = {
 		.report_hdr_64bit = true, },
 };
 
+/* Track variables which have different values between i915 and xe */
+static struct i915_xe {
+	char sysctl_path_paranoid[80];
+	char sysctl_path_max_sample_rate[80];
+} i9xe;
+
 static bool hsw_undefined_a_counters[45] = {
 	[4] = true,
 	[6] = true,

@@ -1416,7 +1424,7 @@ test_system_wide_paranoid(void)
 			.properties_ptr = to_user_pointer(properties),
 		};
 
-		write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+		write_u64_file(i9xe.sysctl_path_paranoid, 1);
 
 		igt_drop_root();
 

@@ -1441,7 +1449,7 @@ test_system_wide_paranoid(void)
 			.num_properties = ARRAY_SIZE(properties) / 2,
 			.properties_ptr = to_user_pointer(properties),
 		};
-		write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 0);
+		write_u64_file(i9xe.sysctl_path_paranoid, 0);
 
 		igt_drop_root();
 

@@ -1452,7 +1460,7 @@ test_system_wide_paranoid(void)
 	igt_waitchildren();
 
 	/* leave in paranoid state */
-	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+	write_u64_file(i9xe.sysctl_path_paranoid, 1);
 }
 
 static void

@@ -2287,7 +2295,7 @@ test_invalid_oa_exponent(void)
 static void
 test_low_oa_exponent_permissions(void)
 {
-	int max_freq = read_u64_file("/proc/sys/dev/i915/oa_max_sample_rate");
+	int max_freq = read_u64_file(i9xe.sysctl_path_max_sample_rate);
 	int bad_exponent = max_oa_exponent_for_freq_gt(max_freq);
 	int ok_exponent = bad_exponent + 1;
 	uint64_t properties[] = {

@@ -2309,7 +2317,7 @@ test_low_oa_exponent_permissions(void)
 	igt_assert_eq(max_freq, 100000);
 
 	/* Avoid EACCES errors opening a stream without CAP_SYS_ADMIN */
-	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 0);
+	write_u64_file(i9xe.sysctl_path_paranoid, 0);
 
 	igt_fork(child, 1) {
 		igt_drop_root();

@@ -2332,7 +2340,7 @@ test_low_oa_exponent_permissions(void)
 
 	oa_period = timebase_scale(2 << ok_exponent);
 	oa_freq = NSEC_PER_SEC / oa_period;
-	write_u64_file("/proc/sys/dev/i915/oa_max_sample_rate", oa_freq - 100);
+	write_u64_file(i9xe.sysctl_path_max_sample_rate, oa_freq - 100);
 
 	igt_fork(child, 1) {
 		igt_drop_root();

@@ -2343,8 +2351,8 @@ test_low_oa_exponent_permissions(void)
 	igt_waitchildren();
 
 	/* restore the defaults */
-	write_u64_file("/proc/sys/dev/i915/oa_max_sample_rate", 100000);
-	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+	write_u64_file(i9xe.sysctl_path_max_sample_rate, 100000);
+	write_u64_file(i9xe.sysctl_path_paranoid, 1);
 }
 
 static void

@@ -2369,7 +2377,7 @@ test_per_context_mode_unprivileged(void)
 	};
 
 	/* should be default, but just to be sure... */
-	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+	write_u64_file(i9xe.sysctl_path_paranoid, 1);
 
 	igt_fork(child, 1) {
 		uint32_t ctx_id = 0xffffffff; /* invalid id */

@@ -3567,7 +3575,7 @@ gen12_test_mi_rpc(const struct intel_execution_engine2 *e)
 	struct oa_format format = get_oa_format(fmt);
 
 	/* Ensure perf_stream_paranoid is set to 1 by default */
-	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+	write_u64_file(i9xe.sysctl_path_paranoid, 1);
 
 	bops = buf_ops_create(drm_fd);
 	ctx_id = gem_context_create(drm_fd);

@@ -3749,7 +3757,7 @@ hsw_test_single_ctx_counters(void)
 	};
 
 	/* should be default, but just to be sure... */
-	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+	write_u64_file(i9xe.sysctl_path_paranoid, 1);
 
 	igt_fork(child, 1) {
 		struct buf_ops *bops;

@@ -3988,7 +3996,7 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
 	struct igt_helper_process child = {};
 
 	/* should be default, but just to be sure... */
-	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+	write_u64_file(i9xe.sysctl_path_paranoid, 1);
 
 	do {
 

@@ -4694,7 +4702,7 @@ gen12_test_single_ctx_render_target_writes_a_counter(const struct intel_executio
 	struct igt_helper_process child = {};
 
 	/* Ensure perf_stream_paranoid is set to 1 by default */
-	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+	write_u64_file(i9xe.sysctl_path_paranoid, 1);
 
 	do {
 		igt_fork_helper(&child) {

@@ -5010,7 +5018,7 @@ test_global_sseu_config(const intel_ctx_t *ctx, const struct intel_execution_eng
 
 	igt_require(__builtin_popcount(default_sseu.subslice_mask) > 1);
 
-	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 0);
+	write_u64_file(i9xe.sysctl_path_paranoid, 0);
 
 	sseu_param = make_valid_reduced_sseu_config(default_sseu,
 						    e->class,

@@ -5027,7 +5035,7 @@ test_global_sseu_config(const intel_ctx_t *ctx, const struct intel_execution_eng
 
 	igt_waitchildren();
 
-	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+	write_u64_file(i9xe.sysctl_path_paranoid, 1);
 
 	stream_fd = __perf_open(drm_fd, &param, false);
 	__perf_close(stream_fd);

@@ -5509,8 +5517,8 @@ test_i915_ref_count(void)
 static void
 test_sysctl_defaults(void)
 {
-	int paranoid = read_u64_file("/proc/sys/dev/i915/perf_stream_paranoid");
-	int max_freq = read_u64_file("/proc/sys/dev/i915/oa_max_sample_rate");
+	int paranoid = read_u64_file(i9xe.sysctl_path_paranoid);
+	int max_freq = read_u64_file(i9xe.sysctl_path_max_sample_rate);
 
 	igt_assert_eq(paranoid, 1);
 	igt_assert_eq(max_freq, 100000);

@@ -5912,9 +5920,9 @@ igt_main
 		 */
 		drm_load_module(DRIVER_INTEL);
 
-		igt_require(stat("/proc/sys/dev/i915/perf_stream_paranoid", &sb)
+		igt_require(stat(i9xe.sysctl_path_paranoid, &sb)
 			    == 0);
-		igt_require(stat("/proc/sys/dev/i915/oa_max_sample_rate", &sb)
+		igt_require(stat(i9xe.sysctl_path_max_sample_rate, &sb)
 			    == 0);
 	}
 

@@ -5931,8 +5939,17 @@ igt_main
 		igt_assert_eq(drm_fd, -1);
 
 		/* Avoid the normal exithandler, our perf-fd interferes */
-		drm_fd = __drm_open_driver(DRIVER_INTEL);
-		igt_require_gem(drm_fd);
+		drm_fd = __drm_open_driver(DRIVER_INTEL | DRIVER_XE);
+		igt_require(is_intel_device(drm_fd));
+		if (is_xe_device(drm_fd)) {
+			xe_device_get(drm_fd);
+			sprintf(i9xe.sysctl_path_paranoid, "/proc/sys/dev/xe/perf_stream_paranoid");
+			sprintf(i9xe.sysctl_path_max_sample_rate, "/proc/sys/dev/xe/oa_max_sample_rate");
+		} else {
+			igt_require_gem(drm_fd);
+			sprintf(i9xe.sysctl_path_paranoid, "/proc/sys/dev/i915/perf_stream_paranoid");
+			sprintf(i9xe.sysctl_path_max_sample_rate, "/proc/sys/dev/i915/oa_max_sample_rate");
+		}
 
 		devid = intel_get_drm_devid(drm_fd);
 		sysfs = perf_sysfs_open(drm_fd);

@@ -5941,8 +5958,8 @@ igt_main
 
 		ctx = intel_ctx_create_all_physical(drm_fd);
 		set_default_engine(ctx);
-		write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
-		write_u64_file("/proc/sys/dev/i915/oa_max_sample_rate", 100000);
+		write_u64_file(i9xe.sysctl_path_paranoid, 1);
+		write_u64_file(i9xe.sysctl_path_max_sample_rate, 100000);
 
 		gt_max_freq_mhz = sysfs_read(RPS_RP0_FREQ_MHZ);
 		perf_oa_groups = get_engine_groups(drm_fd, &num_perf_oa_groups);

@@ -6184,8 +6201,8 @@ igt_main
 
 	igt_fixture {
 		/* leave sysctl options in their default state... */
-		write_u64_file("/proc/sys/dev/i915/oa_max_sample_rate", 100000);
-		write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+		write_u64_file(i9xe.sysctl_path_max_sample_rate, 100000);
+		write_u64_file(i9xe.sysctl_path_paranoid, 1);
 
 		if (intel_perf)
 			intel_perf_free(intel_perf);

index 6ab371857847..9fb11f9e0730 100644
@@ -6147,12 +6147,14 @@ igt_main
 		 */
 		igt_describe("Verify exclusivity of perf streams with sample oa option");
 		igt_subtest("gen12-group-exclusive-stream-sample-oa") {
+			igt_require(!is_xe_device(drm_fd));
 			igt_require(intel_gen(devid) >= 12);
 			test_group_exclusive_stream(ctx, true);
 		}
 
 		igt_describe("Verify exclusivity of perf streams with ctx handle");
 		igt_subtest("gen12-group-exclusive-stream-ctx-handle") {
+			igt_require(!is_xe_device(drm_fd));
 			igt_require(intel_gen(devid) >= 12);
 			test_group_exclusive_stream(ctx, false);
 		}

@@ -6177,14 +6179,18 @@ igt_main
 		}
 
 		igt_describe("Verify invalid SSEU opening parameters");
-		igt_subtest_with_dynamic("global-sseu-config-invalid")
+		igt_subtest_with_dynamic("global-sseu-config-invalid") {
+			igt_require(!is_xe_device(drm_fd));
 			__for_random_engine_in_each_group(perf_oa_groups, ctx, e)
 				test_global_sseu_config_invalid(ctx, e);
+		}
 
 		igt_describe("Verify specifying SSEU opening parameters");
-		igt_subtest_with_dynamic("global-sseu-config")
+		igt_subtest_with_dynamic("global-sseu-config") {
+			igt_require(!is_xe_device(drm_fd));
 			__for_random_engine_in_each_group(perf_oa_groups, ctx, e)
 				test_global_sseu_config(ctx, e);
+		}
 	}
 
 	igt_subtest("invalid-create-userspace-config")

index 9fb11f9e0730..03af968d9484 100644
@@ -564,6 +564,12 @@ static int i915_perf_revision(int fd)
 	drm_i915_getparam_t gp;
 	int value = 1, ret;
 
+#define FINAL_I915_PERF_REV 7
+
+	if (is_xe_device(drm_fd))
+		return FINAL_I915_PERF_REV +
+			xe_config(drm_fd)->info[XE_QUERY_OA_IOCTL_VERSION];
+
 	gp.param = I915_PARAM_PERF_REVISION;
 	gp.value = &value;
 	ret = igt_ioctl(drm_fd, DRM_IOCTL_I915_GETPARAM, &gp);

index 03af968d9484..292afda9a434 100644
@@ -643,7 +643,20 @@ sysfs_read(enum i915_attr_id id)
 {
 	unsigned long value;
 
-	igt_assert(igt_sysfs_rps_scanf(sysfs, id, "%lu", &value) == 1);
+	if (is_xe_device(drm_fd)) {
+		switch (id) {
+		case RPS_RP0_FREQ_MHZ:
+			igt_assert(igt_sysfs_scanf(sysfs, "device/tile0/gt0/freq_rp0", "%lu", &value) == 1);
+			break;
+		case RC6_RESIDENCY_MS:
+			igt_assert(igt_sysfs_scanf(sysfs, "device/tile0/gt0/rc6_residency", "%lu", &value) == 1);
+			break;
+		default:
+			igt_assert(0);
+		}
+	} else {
+		igt_assert(igt_sysfs_rps_scanf(sysfs, id, "%lu", &value) == 1);
+	}
 
 	return value;
 }

@@ -5436,6 +5449,9 @@ static int perf_sysfs_open(int i915)
 {
 	int dirfd, gt;
 
+	if (is_xe_device(drm_fd))
+		return igt_sysfs_open(drm_fd);
+
 	/* use the first available sysfs interface */
 	for_each_sysfs_gt_dirfd(i915, dirfd, gt)
 		break;

index 292afda9a434..ef2d56e319f8 100644
@@ -5418,18 +5418,21 @@ test_whitelisted_registers_userspace_config(void)
 }
 
 static unsigned
-read_i915_module_ref(void)
+read_i915_module_ref(bool is_xe)
 {
 	FILE *fp = fopen("/proc/modules", "r");
 	char *line = NULL;
 	size_t line_buf_size = 0;
 	int len = 0;
 	unsigned ref_count;
+	char mod[8];
+	int modn = is_xe ? 3 : 5;
 
 	igt_assert(fp);
 
+	strcpy(mod, is_xe ? "xe " : "i915 ");
 	while ((len = getline(&line, &line_buf_size, fp)) > 0) {
-		if (strncmp(line, "i915 ", 5) == 0) {
+		if (strncmp(line, mod, modn) == 0) {
 			unsigned long mem;
 			int ret = sscanf(line + 5, "%lu %u", &mem, &ref_count);
 			igt_assert(ret == 2);

@@ -5484,17 +5487,26 @@ test_i915_ref_count(void)
 	unsigned baseline, ref_count0, ref_count1;
 	uint32_t oa_report0[64];
 	uint32_t oa_report1[64];
+	bool is_xe;
 
 	/* This should be the first test before the first fixture so no drm_fd
 	 * should have been opened so far...
 	 */
 	igt_assert_eq(drm_fd, -1);
 
-	baseline = read_i915_module_ref();
+	/* Tell read_i915_module_ref if we are on xe or i915 (because drm_fd is -1) */
+	drm_fd = __drm_open_driver(DRIVER_INTEL | DRIVER_XE);
+	is_xe = is_xe_device(drm_fd);
+	drm_close_driver(drm_fd);
+	close(sysfs);
+	drm_fd = -1;
+
+	baseline = read_i915_module_ref(is_xe);
 	igt_debug("baseline ref count (drm fd closed) = %u\n", baseline);
 
-	drm_fd = __drm_open_driver(DRIVER_INTEL);
-	igt_require_i915(drm_fd);
+	drm_fd = __drm_open_driver(DRIVER_INTEL | DRIVER_XE);
+	if (is_xe_device(drm_fd))
+		xe_device_get(drm_fd);
 	devid = intel_get_drm_devid(drm_fd);
 	sysfs = perf_sysfs_open(drm_fd);
 

@@ -5506,12 +5518,12 @@ test_i915_ref_count(void)
 	properties[5] = default_test_set->perf_oa_format;
 	properties[7] = oa_exp_1_millisec;
 
-	ref_count0 = read_i915_module_ref();
+	ref_count0 = read_i915_module_ref(is_xe);
 	igt_debug("initial ref count with drm_fd open = %u\n", ref_count0);
 	igt_assert(ref_count0 > baseline);
 
 	stream_fd = __perf_open(drm_fd, &param, false);
-	ref_count1 = read_i915_module_ref();
+	ref_count1 = read_i915_module_ref(is_xe);
 	igt_debug("ref count after opening i915 perf stream = %u\n", ref_count1);
 	igt_assert(ref_count1 > ref_count0);
 

@@ -5519,7 +5531,7 @@ test_i915_ref_count(void)
 	close(sysfs);
 	drm_fd = -1;
 	sysfs = -1;
-	ref_count0 = read_i915_module_ref();
+	ref_count0 = read_i915_module_ref(is_xe);
 	igt_debug("ref count after closing drm fd = %u\n", ref_count0);
 
 	igt_assert(ref_count0 > baseline);

@@ -5531,7 +5543,7 @@ test_i915_ref_count(void)
 			  false); /* not just timer reports */
 
 	__perf_close(stream_fd);
-	ref_count0 = read_i915_module_ref();
+	ref_count0 = read_i915_module_ref(is_xe);
 	igt_debug("ref count after closing i915 perf stream fd = %u\n", ref_count0);
 	igt_assert_eq(ref_count0, baseline);
 }

index ef2d56e319f8..6f10e1d035cb 100644
@@ -5726,6 +5726,9 @@ static struct perf_engine_group *get_engine_groups(int i915, uint32_t *num_group
 	struct perf_engine_group *groups = NULL;
 	uint32_t id = UINT32_MAX, num_grps = 0, i = 0, j;
 
+	if (is_xe_device(drm_fd))
+		return default_engine_group(num_groups);
+
 	qinfo = query_engine_info(i915);
 	if (!qinfo)
 		return default_engine_group(num_groups);

@@ -5996,6 +5999,7 @@ igt_main
 		write_u64_file(i9xe.sysctl_path_max_sample_rate, 100000);
 
 		gt_max_freq_mhz = sysfs_read(RPS_RP0_FREQ_MHZ);
+
 		perf_oa_groups = get_engine_groups(drm_fd, &num_perf_oa_groups);
 		igt_assert(perf_oa_groups && num_perf_oa_groups);
 

index 6f10e1d035cb..7cbf3f7ca287 100644
@@ -5564,13 +5564,18 @@ __ci_to_e2(const intel_ctx_t *ctx, struct i915_engine_class_instance *ci)
 	static struct intel_execution_engine2 e2;
 	struct intel_execution_engine2 *e;
 
+	if (is_xe_device(drm_fd)) {
+		strncpy(e2.name, "rcs", sizeof(e2.name));
+		goto exit;
+	}
+
 	for_each_ctx_engine(drm_fd, ctx, e) {
 		if (e->class == ci->engine_class && e->instance == ci->engine_instance) {
 			e2 = *e;
 			break;
 		}
 	}
-
+exit:
 	return &e2;
 }
 

index 7cbf3f7ca287..e0afbbc45ea2 100644
@@ -5952,22 +5952,6 @@ igt_main
 	const intel_ctx_t *ctx;
 	const struct intel_execution_engine2 *e;
 
-	igt_fixture {
-		struct stat sb;
-
-		/*
-		 * Prior tests may have unloaded i915 or failed while
-		 * loading/unloading i915. Load i915 here before we stat the
-		 * files.
-		 */
-		drm_load_module(DRIVER_INTEL);
-
-		igt_require(stat(i9xe.sysctl_path_paranoid, &sb)
-			    == 0);
-		igt_require(stat(i9xe.sysctl_path_max_sample_rate, &sb)
-			    == 0);
-	}
-
 	igt_subtest("i915-ref-count")
 		test_i915_ref_count();
 

index e0afbbc45ea2..78e68462ad06 100644
@@ -5955,9 +5955,6 @@ igt_main
 	igt_subtest("i915-ref-count")
 		test_i915_ref_count();
 
-	igt_subtest("sysctl-defaults")
-		test_sysctl_defaults();
-
 	igt_fixture {
 		/* We expect that the ref count test before these fixtures
 		 * should have closed drm_fd...

@@ -5996,6 +5993,9 @@ igt_main
 			render_copy = igt_get_render_copyfunc(devid);
 	}
 
+	igt_subtest("sysctl-defaults")
+		test_sysctl_defaults();
+
 	igt_subtest("non-system-wide-paranoid")
 		test_system_wide_paranoid();
 

index 78e68462ad06..df6cb7edd017 100644
@@ -5816,6 +5816,12 @@ static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
 {
 	int fd;
 
+	if (is_xe_device(drm_fd)) {
+		if (class == I915_ENGINE_CLASS_RENDER && !IS_PONTEVECCHIO(devid))
+			return true;
+		return false;
+	}
+
 	fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
 	if (fd >= 0) {
 		close(fd);

index df6cb7edd017..0efa7f71477d 100644
@@ -5995,7 +5995,8 @@ igt_main
 		perf_oa_groups = get_engine_groups(drm_fd, &num_perf_oa_groups);
 		igt_assert(perf_oa_groups && num_perf_oa_groups);
 
-		if (has_class_instance(drm_fd, I915_ENGINE_CLASS_RENDER, 0))
+		if (has_class_instance(drm_fd, I915_ENGINE_CLASS_RENDER, 0) &&
+		    !is_xe_device(drm_fd))
 			render_copy = igt_get_render_copyfunc(devid);
 	}
 

index 0efa7f71477d..bfe4dd6ee533 100644
@@ -5955,7 +5955,7 @@ test_group_concurrent_oa_buffer_read(void)
 
 igt_main
 {
-	const intel_ctx_t *ctx;
+	const intel_ctx_t *ctx = NULL;
 	const struct intel_execution_engine2 *e;
 
 	igt_subtest("i915-ref-count")

@@ -5985,8 +5985,11 @@ igt_main
 
 		igt_require(init_sys_info());
 
-		ctx = intel_ctx_create_all_physical(drm_fd);
-		set_default_engine(ctx);
+		if (!is_xe_device(drm_fd)) {
+			ctx = intel_ctx_create_all_physical(drm_fd);
+			set_default_engine(ctx);
+		}
+
 		write_u64_file(i9xe.sysctl_path_paranoid, 1);
 		write_u64_file(i9xe.sysctl_path_max_sample_rate, 100000);
 

index bfe4dd6ee533..27408e7909f5 100644
@@ -6153,8 +6153,14 @@ igt_main
 		igt_describe("Test MI REPORT PERF COUNT for Gen 12");
 		igt_subtest_with_dynamic("gen12-mi-rpc") {
 			igt_require(has_class_instance(drm_fd, I915_ENGINE_CLASS_RENDER, 0));
-			__for_each_render_engine(drm_fd, e)
-				gen12_test_mi_rpc(e);
+			if (is_xe_device(drm_fd)) {
+				const struct intel_execution_engine2 e2 = {};
+				igt_dynamic_f("%s", "rcs")
+					gen12_test_mi_rpc(&e2);
+			} else {
+				__for_each_render_engine(drm_fd, e)
+					gen12_test_mi_rpc(e);
+			}
 		}
 
 		igt_describe("Test OA TLB invalidate");

@@ -6166,8 +6172,14 @@ igt_main
 		igt_subtest_with_dynamic("gen12-unprivileged-single-ctx-counters") {
 			igt_require(has_class_instance(drm_fd, I915_ENGINE_CLASS_RENDER, 0));
 			igt_require_f(render_copy, "no render-copy function\n");
-			__for_each_render_engine(drm_fd, e)
-				gen12_test_single_ctx_render_target_writes_a_counter(e);
+			if (is_xe_device(drm_fd)) {
+				const struct intel_execution_engine2 e2 = {};
+				igt_dynamic_f("%s", "rcs")
+					gen12_test_single_ctx_render_target_writes_a_counter(&e2);
+			} else {
+				__for_each_render_engine(drm_fd, e)
+					gen12_test_single_ctx_render_target_writes_a_counter(e);
+			}
 		}
 	}
 

index 27408e7909f5..cd1087b2e954 100644
@@ -901,15 +901,19 @@ oar_unit_default_format(void)
  * Temporary wrapper to distinguish mappings on !llc platforms,
  * where it seems cache over GEM_MMAP_OFFSET is not flushed before execution.
  */
-static void *buf_map(int i915, struct intel_buf *buf, bool write)
+static void *buf_map(int fd, struct intel_buf *buf, bool write)
 {
 	void *p;
 
-	if (gem_has_llc(i915))
-		p = intel_buf_cpu_map(buf, write);
-	else
-		p = intel_buf_device_map(buf, write);
-
+	if (is_xe_device(fd)) {
+		buf->ptr = xe_bo_map(fd, buf->handle, buf->surface[0].size);
+		p = buf->ptr;
+	} else {
+		if (gem_has_llc(fd))
+			p = intel_buf_cpu_map(buf, write);
+		else
+			p = intel_buf_device_map(buf, write);
+	}
 	return p;
 }
 

@@ -3620,7 +3624,7 @@ gen12_test_mi_rpc(const struct intel_execution_engine2 *e)
 	intel_bb_flush_render(ibb);
 	intel_bb_sync(ibb);
 
-	intel_buf_cpu_map(buf, false);
+	buf_map(drm_fd, buf, false);
 	report32 = buf->ptr;
 	format_size_32 = format.size >> 2;
 	dump_report(report32, format_size_32, "mi-rpc");

index cd1087b2e954..0e54fa8f13a9 100644
@@ -45,6 +45,7 @@
 #include "igt_perf.h"
 #include "igt_sysfs.h"
 #include "drm.h"
+#include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 
 /**

@@ -3593,6 +3594,7 @@ gen12_test_mi_rpc(const struct intel_execution_engine2 *e)
 	struct intel_buf *buf;
 #define INVALID_CTX_ID 0xffffffff
 	uint32_t ctx_id = INVALID_CTX_ID;
+	uint32_t vm = 0;
 	uint32_t *report32;
 	size_t format_size_32;
 	struct oa_format format = get_oa_format(fmt);

@@ -3601,11 +3603,16 @@ gen12_test_mi_rpc(const struct intel_execution_engine2 *e)
 	write_u64_file(i9xe.sysctl_path_paranoid, 1);
 
 	bops = buf_ops_create(drm_fd);
-	ctx_id = gem_context_create(drm_fd);
+	if (is_xe_device(drm_fd)) {
+		vm = xe_vm_create(drm_fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+		ctx_id = xe_engine_create(drm_fd, vm, xe_hw_engine(drm_fd, 0), 0);
+	} else {
+		ctx_id = gem_context_create(drm_fd);
+	}
 	igt_assert_neq(ctx_id, INVALID_CTX_ID);
 	properties[1] = ctx_id;
 
-	ibb = intel_bb_create_with_context(drm_fd, ctx_id, 0, NULL, BATCH_SZ);
+	ibb = intel_bb_create_with_context(drm_fd, ctx_id, vm, NULL, BATCH_SZ);
 	buf = intel_buf_create(bops, 4096, 1, 8, 64,
 			       I915_TILING_NONE, I915_COMPRESSION_NONE);
 

@@ -3650,7 +3657,12 @@ gen12_test_mi_rpc(const struct intel_execution_engine2 *e)
 	intel_buf_unmap(buf);
 	intel_buf_destroy(buf);
 	intel_bb_destroy(ibb);
-	gem_context_destroy(drm_fd, ctx_id);
+	if (is_xe_device(drm_fd)) {
+		xe_engine_destroy(drm_fd, ctx_id);
+		xe_vm_destroy(drm_fd, vm);
+	} else {
+		gem_context_destroy(drm_fd, ctx_id);
+	}
 	buf_ops_destroy(bops);
 	__perf_close(stream_fd);
 }