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FAILED: patch "[PATCH] drm/i915/gt: Poll aux invalidation register bit on" failed to apply to 6.4-stable tree

PATCH [email protected] 1 participant 1 message Aug 7, 2023

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Stable branch DRM drivers Intel i915
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The patch below does not apply to the 6.4-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

To reproduce the conflict and resubmit, you may use the following commands:

git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.4.y
git checkout FETCH_HEAD
git cherry-pick -x 0fde2f23516a00fd90dfb980b66b4665fcbfa659
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2023080727-spray-payee-2e18@gregkh' --subject-prefix 'PATCH 6.4.y' HEAD^..

Possible dependencies:

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 0fde2f23516a00fd90dfb980b66b4665fcbfa659 Mon Sep 17 00:00:00 2001
From: Jonathan Cavitt <[email protected]>
Date: Tue, 25 Jul 2023 02:19:49 +0200
Subject: [PATCH] drm/i915/gt: Poll aux invalidation register bit on
invalidation

For platforms that use Aux CCS, wait for aux invalidation to complete by checking the aux invalidation register bit is cleared.

Fixes 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by Jonathan Cavitt <[email protected]>
Signed-off-by Andi Shyti <[email protected]>
Cc <[email protected]> # v5.8+
Reviewed-by Nirmoy Das <[email protected]>
Reviewed-by Andrzej Hajda <[email protected]>
Reviewed-by Matt Roper <[email protected]>
Link https://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit d459c86f00aa98028d155a012c65dc42f7c37e76)
Signed-off-by Tvrtko Ursulin <[email protected]>
drivers/gpu/drm/i915/gt/gen8_engine_cs.c +12 -5
index ec54d36eaef7..ec7a0ddf9e12 100644
@@ -184,7 +184,15 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
 	*cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
 	*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;
 	*cs++ = AUX_INV;
-	*cs++ = MI_NOOP;
+
+	*cs++ = MI_SEMAPHORE_WAIT_TOKEN |
+		MI_SEMAPHORE_REGISTER_POLL |
+		MI_SEMAPHORE_POLL |
+		MI_SEMAPHORE_SAD_EQ_SDD;
+	*cs++ = 0;
+	*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;
+	*cs++ = 0;
+	*cs++ = 0;
 
 	return cs;
 }

@@ -292,10 +300,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 		else if (engine->class == COMPUTE_CLASS)
 			flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
 
+		count = 8;
 		if (gen12_needs_ccs_aux_inv(rq->engine))
-			count = 8 + 4;
-		else
-			count = 8;
+			count += 8;
 
 		cs = intel_ring_begin(rq, count);
 		if (IS_ERR(cs))

@@ -338,7 +345,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
 			aux_inv = rq->engine->mask &
 				~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0);
 			if (aux_inv)
-				cmd += 4;
+				cmd += 8;
 		}
 	}
drivers/gpu/drm/i915/gt/intel_gpu_commands.h +1 -0
index 5df7cce23197..2bd8d98d2110 100644
@@ -121,6 +121,7 @@
 #define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
 #define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
 #define MI_SEMAPHORE_WAIT_TOKEN	MI_INSTR(0x1c, 3) /* GEN12+ */
+#define   MI_SEMAPHORE_REGISTER_POLL	(1 << 16)
 #define   MI_SEMAPHORE_POLL		(1 << 15)
 #define   MI_SEMAPHORE_SAD_GT_SDD	(0 << 12)
 #define   MI_SEMAPHORE_SAD_GTE_SDD	(1 << 12)