usb: dwc3: dwc3-octeon: Verify clock divider
Subsystems (4)
PATCH 1/1 usb: dwc3: dwc3-octeon: Verify clock divider
From: Ladislav Michl <[email protected]>
Although valid USB clock divider will be calculated for all valid Octeon core frequencies, make code formally correct limiting divider not to be greater that 7 so it fits into H_CLKDIV_SEL field.
---
Greg, if you want to resent whole serie, just drop me a note. Otherwise, this patch is meant to be applied on to of it. Thank you.
drivers/usb/dwc3/dwc3-octeon.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
drivers/usb/dwc3/dwc3-octeon.c +6 -2
@@ -251,11 +251,11 @@ static int dwc3_octeon_get_divider(void)while (div <ARRAY_SIZE (clk_div)) {uint64_t rate =octeon_get_io_clock_rate () / clk_div[div];if (rate <=300000000 && rate >=150000000 ) -break ; +return div; div++; } -return div; +return -EINVAL ; } static int dwc3_octeon_setup(struct dwc3_octeon *octeon,
@@ -289,6 +289,10 @@ static int dwc3_octeon_setup(struct dwc3_octeon *octeon,/* Step 4b: Select controller clock frequency. */ div =dwc3_octeon_get_divider (); +if (div <0 ) { +dev_err (dev,"clock divider invalid\n" ); +return div; + } val =dwc3_octeon_readq (uctl_ctl_reg); val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL ; val |=FIELD_PREP (USBDRD_UCTL_CTL_H_CLKDIV_SEL , div);
Signature · 1 line
2.39.2
Greg Kroah-Hartman
maintainerQuoted 7 lines · Ladislav Michl
From: Ladislav Michl <[email protected]>
Although valid USB clock divider will be calculated for all valid Octeon core frequencies, make code formally correct limiting divider not to be greater that 7 so it fits into
H_CLKDIV_SELfield.
Quoted 6 lines
Signed-off-by Ladislav Michl <[email protected]>---
Greg, if you want to resent whole serie, just drop me a note. Otherwise, this patch is meant to be applied on to of it.
On top of what series?
confused,
greg k-h
Quoted 8 lines · Greg Kroah-Hartman
Quoted 7 lines · Ladislav Michl
From: Ladislav Michl <[email protected]>
Although valid USB clock divider will be calculated for all valid Octeon core frequencies, make code formally correct limiting divider not to be greater that 7 so it fits into
H_CLKDIV_SELfield.
Quoted 8 lines
Quoted 6 lines
Signed-off-by Ladislav Michl <[email protected]>---
Greg, if you want to resent whole serie, just drop me a note. Otherwise, this patch is meant to be applied on to of it.On top of what series?
I'm sorry, "[PATCH v5 0/7] Cleanup Octeon DWC3 glue code". In your usb-next, last patch of serie is:d9216d3ef538 ("usb: dwc3: dwc3-octeon: Add SPDX header and copyright")
Thanks,
l.
Greg Kroah-Hartman
maintainerQuoted 16 lines · Ladislav Michl
Quoted 15 lines · Greg Kroah-Hartman
Quoted 13 lines · Ladislav Michl
From: Ladislav Michl <[email protected]>
Although valid USB clock divider will be calculated for all valid Octeon core frequencies, make code formally correct limiting divider not to be greater that 7 so it fits into
H_CLKDIV_SELfield.Signed-off-by Ladislav Michl <[email protected]>---
Greg, if you want to resent whole serie, just drop me a note. Otherwise, this patch is meant to be applied on to of it.
Quoted 5 lines
Quoted 1 line
On top of what series?
I'm sorry, "[PATCH v5 0/7] Cleanup Octeon DWC3 glue code". In your usb-next, last patch of serie is:
d9216d3ef538("usb: dwc3: dwc3-octeon: Add SPDX header and copyright")
I already took that series, so this is fine, I don't want to revert that and have to add it all back :)
thanks,
greg k-h
Quoted 50 lines · Ladislav Michl
From: Ladislav Michl <[email protected]>
Although valid USB clock divider will be calculated for all valid Octeon core frequencies, make code formally correct limiting divider not to be greater that 7 so it fits into
H_CLKDIV_SELfield.Signed-off-by Ladislav Michl <[email protected]>---
Greg, if you want to resent whole serie, just drop me a note. Otherwise, this patch is meant to be applied on to of it. Thank you.drivers/usb/dwc3/dwc3-octeon.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)drivers/usb/dwc3/dwc3-octeon.c +6
-2@@ -251,11 +251,11 @@ static int dwc3_octeon_get_divider(void)while (div <ARRAY_SIZE (clk_div)) {uint64_t rate =octeon_get_io_clock_rate () / clk_div[div];if (rate <=300000000 && rate >=150000000 ) -break ; +return div; div++; } -return div; +return -EINVAL ; } static int dwc3_octeon_setup(struct dwc3_octeon *octeon,@@ -289,6 +289,10 @@ static int dwc3_octeon_setup(struct dwc3_octeon *octeon,/* Step 4b: Select controller clock frequency. */ div =dwc3_octeon_get_divider (); +if (div <0 ) { +dev_err (dev,"clock divider invalid\n" ); +return div; + } val =dwc3_octeon_readq (uctl_ctl_reg); val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL ; val |=FIELD_PREP (USBDRD_UCTL_CTL_H_CLKDIV_SEL , div);Signature · 1 line
2.39.2
Thanks,
Thinh
Quoted 10 lines · Ladislav Michl
From: Ladislav Michl <[email protected]>
Although valid USB clock divider will be calculated for all valid Octeon core frequencies, make code formally correct limiting divider not to be greater that 7 so it fits into
H_CLKDIV_SELfield.
Quoted 7 lines
---
Greg, if you want to resent whole serie, just drop me a note. Otherwise, this patch is meant to be applied on to of it. Thank you.drivers/usb/dwc3/dwc3-octeon.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)