Add Anbernic RG-Nano
Subsystems (7)
v3 cover Add Anbernic RG-Nano
From: Chris Morgan <[email protected]>
Add support for the Anbernic RG-Nano handheld gaming device
Changes since V2:
- Add display support.
- Add USB host support.
- Removed CPU frequency and voltage parameters, as CPU regulator may be tied into additional areas that need further testing.
- Added regulator names back, as they appear to have been accidentally dropped in v2.
- Updated notes to denote all hardware tested and working.
Changes since V1:
- Added additional pwm pin configs to sun8i-v3s.dtsi and removed default config for pwm0 in lieu of defining it for each board.
- Noted in patch notes that additional hardware of UART debug port, USB port (in gadget mode) also work, and that USB host mode does not work.
- Identified GPIO responsible for enabling external speaker amplifier and defined it, allowing onboard audio to work.
- Removed ac_power_supply node.
- Set regulator min and max values to the same value as defined in the schematics.
- Removed definition for reg_ldo1. This regulator is hardware configured so the value did not affect anything, however the driver must be updated to support the correct value of 3.3v in this case.
- Removed usb0_id_det-gpios as I cannot confirm these are correct.
Chris Morgan (8):
dt-bindings: vendor-prefixes: document Saef Technology
dt-bindings: display: panel: mipi-dbi-spi: add Saef SF-TC154B
arm: dts: sun8i: V3s: Add pinctrl for pwm
dt-bindings: usb: Add V3s compatible string for EHCI
dt-bindings: usb: Add V3s compatible string for OHCI
ARM: dts: sun8i: v3s: add EHCI and OHCI to v3s dts
dt-bindings: arm: sunxi: add Anbernic RG-Nano
ARM: dts: sunxi: add support for Anbernic RG-Nano
.../devicetree/bindings/arm/sunxi.yaml | 5 + .../display/panel/panel-mipi-dbi-spi.yaml | 1 + .../devicetree/bindings/usb/generic-ehci.yaml | 1 + .../devicetree/bindings/usb/generic-ohci.yaml | 1 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 275 ++++++++++++++++++ arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 31 ++ 8 files changed, 317 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Signature · 1 line
2.34.1
PATCH v3 1/8 dt-bindings: vendor-prefixes: document Saef Technology
From: Chris Morgan <[email protected]>
Document Saef Technology (https://www.saefdisplay.com/).
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/vendor-prefixes.yaml +2 -0
@@ -1151,6 +1151,8 @@ patternProperties: description: Shenzhen Roofull Technology Co, Ltd "^roseapplepi,.*": description: RoseapplePi.org + "^saef,.*": + description: Saef Technology Limited "^samsung,.*": description: Samsung Semiconductor "^samtec,.*":
Signature · 1 line
2.34.1
Re: [PATCH V3 1/8] dt-bindings: vendor-prefixes: document Saef Technology
Quoted 5 lines · Chris Morgan
From: Chris Morgan <[email protected]>
Document Saef Technology (https://www.saefdisplay.com/).
Signed-off-by Chris Morgan <[email protected]>
Thanks,
Conor.
Quoted 20 lines
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/vendor-prefixes.yaml +2
-0@@ -1151,6 +1151,8 @@ patternProperties: description: Shenzhen Roofull Technology Co, Ltd "^roseapplepi,.*": description: RoseapplePi.org + "^saef,.*": + description: Saef Technology Limited "^samsung,.*": description: Samsung Semiconductor "^samtec,.*":Signature · 1 line
2.34.1
PATCH v3 2/8 dt-bindings: display: panel: mipi-dbi-spi: add Saef SF-TC154B
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
The Saef SF-TC154B is a 1.54 inch 240x240 square panel with a MIPI DBI compatible interface. The panel is used on the Anbernic RG-Nano handheld gaming device.
The initialization of the panel requires a firmware binary which can be made with the mipi-dbi-cmd[1] tool. The command sequence needed can be found in both source[2] and binary form[3].
[1]: https://github.com/notro/panel-mipi-dbi
[2]: https://github.com/macromorgan/panel-mipi-dbi-firmware/raw/main/saef%2Csftc154b.txt
[3]: https://github.com/macromorgan/panel-mipi-dbi-firmware/raw/main/saef%2Csftc154b.bin
--- .../devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml +1 -0
@@ -66,6 +66,7 @@ properties: compatible: items: - enum: + - saef,sftc154b - sainsmart18 - shineworld,lh133k - const: panel-mipi-dbi-spi
Signature · 1 line
2.34.1
Re: [PATCH V3 2/8] dt-bindings: display: panel: mipi-dbi-spi: add Saef SF-TC154B
Quoted 10 lines · Chris Morgan
From: Chris Morgan <[email protected]>
The Saef SF-TC154B is a 1.54 inch 240x240 square panel with a MIPI DBI compatible interface. The panel is used on the Anbernic RG-Nano handheld gaming device.
The initialization of the panel requires a firmware binary which can be made with the mipi-dbi-cmd[1] tool. The command sequence needed can be found in both source[2] and binary form[3].
Quoted 5 lines
[1]: https://github.com/notro/panel-mipi-dbi
[2]: https://github.com/macromorgan/panel-mipi-dbi-firmware/raw/main/saef%2Csftc154b.txt
[3]: https://github.com/macromorgan/panel-mipi-dbi-firmware/raw/main/saef%2Csftc154b.binSigned-off-by Chris Morgan <[email protected]>
Thanks,
Conor.
Quoted 19 lines
--- .../devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml +1
-0@@ -66,6 +66,7 @@ properties: compatible: items: - enum: + - saef,sftc154b - sainsmart18 - shineworld,lh133k - const: panel-mipi-dbi-spiSignature · 1 line
2.34.1
Re: [PATCH V3 2/8] dt-bindings: display: panel: mipi-dbi-spi: add Saef SF-TC154B
In reply to Chris MorganQuoted 10 lines · Chris Morgan
From: Chris Morgan <[email protected]>
The Saef SF-TC154B is a 1.54 inch 240x240 square panel with a MIPI DBI compatible interface. The panel is used on the Anbernic RG-Nano handheld gaming device.
The initialization of the panel requires a firmware binary which can be made with the mipi-dbi-cmd[1] tool. The command sequence needed can be found in both source[2] and binary form[3].
Quoted 6 lines
[1]: https://github.com/notro/panel-mipi-dbi
[2]: https://github.com/macromorgan/panel-mipi-dbi-firmware/raw/main/saef%2Csftc154b.txt
[3]: https://github.com/macromorgan/panel-mipi-dbi-firmware/raw/main/saef%2Csftc154b.binSigned-off-by Chris Morgan <[email protected]>---
Quoted 15 lines
.../devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml +1
-0@@ -66,6 +66,7 @@ properties: compatible: items: - enum: + - saef,sftc154b - sainsmart18 - shineworld,lh133k - const: panel-mipi-dbi-spi
PATCH v3 3/8 arm: dts: sun8i: V3s: Add pinctrl for pwm
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
Add pinctrl nodes for pwm0 and pwm1.
--- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +12 -0
@@ -414,6 +414,18 @@ mmc1_pins: mmc1-pins { bias-pull-up; }; + /omit-if-no-ref/ + pwm0_pin: pwm0-pin { + pins = "PB4"; + function = "pwm0"; + }; + + /omit-if-no-ref/ + pwm1_pin: pwm1-pin { + pins = "PB5"; + function = "pwm1"; + }; + spi0_pins: spi0-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0";
Signature · 1 line
2.34.1
PATCH v3 4/8 dt-bindings: usb: Add V3s compatible string for EHCI
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
The Allwinner V3s uses a generic EHCI and OHCI for USB host communication and the MUSB controller for OTG mode. Add compatible strings for the EHCI node.
--- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/usb/generic-ehci.yaml +1 -0
@@ -38,6 +38,7 @@ properties: - allwinner,sun8i-a83t-ehci - allwinner,sun8i-h3-ehci - allwinner,sun8i-r40-ehci + - allwinner,sun8i-v3s-ehci - allwinner,sun9i-a80-ehci - allwinner,sun20i-d1-ehci - aspeed,ast2400-ehci
Signature · 1 line
2.34.1
Re: [PATCH V3 4/8] dt-bindings: usb: Add V3s compatible string for EHCI
Quoted 7 lines · Chris Morgan
From: Chris Morgan <[email protected]>
The Allwinner V3s uses a generic EHCI and OHCI for USB host communication and the MUSB controller for OTG mode. Add compatible strings for the EHCI node.
Signed-off-by Chris Morgan <[email protected]>
Thanks,
Conor.
Quoted 19 lines
--- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/usb/generic-ehci.yaml +1
-0@@ -38,6 +38,7 @@ properties: - allwinner,sun8i-a83t-ehci - allwinner,sun8i-h3-ehci - allwinner,sun8i-r40-ehci + - allwinner,sun8i-v3s-ehci - allwinner,sun9i-a80-ehci - allwinner,sun20i-d1-ehci - aspeed,ast2400-ehciSignature · 1 line
2.34.1
PATCH v3 5/8 dt-bindings: usb: Add V3s compatible string for OHCI
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
The Allwinner V3s uses a generic EHCI and OHCI for USB host communication and the MUSB controller for OTG mode. Add compatible strings for the EHCI node.
--- Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/usb/generic-ohci.yaml +1 -0
@@ -25,6 +25,7 @@ properties: - allwinner,sun8i-a83t-ohci - allwinner,sun8i-h3-ohci - allwinner,sun8i-r40-ohci + - allwinner,sun8i-v3s-ohci - allwinner,sun9i-a80-ohci - allwinner,sun20i-d1-ohci - brcm,bcm3384-ohci
Signature · 1 line
2.34.1
Re: [PATCH V3 5/8] dt-bindings: usb: Add V3s compatible string for OHCI
Quoted 16 lines · Chris Morgan
From: Chris Morgan <[email protected]>
The Allwinner V3s uses a generic EHCI and OHCI for USB host communication and the MUSB controller for OTG mode. Add compatible strings for the EHCI node.
Signed-off-by Chris Morgan <[email protected]>--- Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/usb/generic-ohci.yaml +0
-0
Documentation/devicetree/bindings/usb/generic-ohci.yaml properties: · line 31
Quoted 7 lines
Documentation/devicetree/bindings/usb/generic-ohci.yaml +1
-0@@ -25,6 +25,7 @@ properties: - allwinner,sun8i-a83t-ohci - allwinner,sun8i-h3-ohci - allwinner,sun8i-r40-ohci + - allwinner,sun8i-v3s-ohci - allwinner,sun9i-a80-ohci - allwinner,sun20i-d1-ohci - brcm,bcm3384-ohci
Thanks,
Conor.
PATCH v3 6/8 ARM: dts: sun8i: v3s: add EHCI and OHCI to v3s dts
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
Add the EHCI and OHCI controller to the Allwinner v3s to support using USB in host mode.
--- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +19 -0
@@ -319,6 +319,25 @@ usbphy: phy@1c19400 { #phy-cells = <1>; }; + ehci: usb@1c1a000 { + compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status = "disabled"; + }; + + ohci: usb@1c1a400 { + compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>;
Signature · 1 line
2.34.1
Re: [PATCH V3 6/8] ARM: dts: sun8i: v3s: add EHCI and OHCI to v3s dts
On Wed, 23 Aug 2023 16:25:52 -0500
Chris Morgan <[email protected]> wrote:
Hi Chris,
Quoted 4 lines
From: Chris Morgan <[email protected]>
Add the EHCI and OHCI controller to the Allwinner v3s to support using USB in host mode.
Alright, so was it really that easy? I was afraid we left out host mode for a reason back then ....
Quoted 11 lines
Signed-off-by Chris Morgan <[email protected]>--- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +0
-0
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi usbphy: phy@1c19400 { · line 327
Quoted 9 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +6
-0@@ -319,6 +319,25 @@ usbphy: phy@1c19400 { #phy-cells = <1>; }; + ehci: usb@1c1a000 { + compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
Please add the link the PHY here:
phys = <&usbphy 0>; phy-names = "usb";
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi usbphy: phy@1c19400 { · line 337
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +10
-0+ status = "disabled"; + }; + + ohci: usb@1c1a400 { + compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
... and here.
That would be definitely the right thing to do, but please check whether it still works, especially OTG operation.
The addresses, clocks, resets and interrupts match the manual.
Cheers,
Andre.
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +3
-0+ status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>;
Re: [PATCH V3 6/8] ARM: dts: sun8i: v3s: add EHCI and OHCI to v3s dts
Quoted 5 lines · Andre Przywara
On Wed, 23 Aug 2023 16:25:52 -0500
Chris Morgan <[email protected]> wrote:Hi Chris,
Quoted 7 lines
Quoted 4 lines
From: Chris Morgan <[email protected]>
Add the EHCI and OHCI controller to the Allwinner v3s to support using USB in host mode.
Alright, so was it really that easy? I was afraid we left out host mode for a reason back then ....
Can't speak to that, but it is working for me as both a host and a gadget.
Quoted 23 lines
Quoted 12 lines
Signed-off-by Chris Morgan <[email protected]>--- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +0
-0arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi usbphy: phy@1c19400 { · line 327
Quoted 9 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +6
-0@@ -319,6 +319,25 @@ usbphy: phy@1c19400 { #phy-cells = <1>; }; + ehci: usb@1c1a000 { + compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;Please add the link the PHY here:
Quoted 2 lines
phys = <&usbphy 0>; phy-names = "usb";
usbphy 0 doesn't work, but if I do phys = <&usbphy 1>; for here and the OHCI node it does work. Is that expected/acceptable? By "doesn't work" I mean the device is always in HOST mode if I use 0 and switches correctly (the extcon shows HOST=0 when unplugged or plugged into my computer, and shows HOST=1 if I plug in a device which I assume is the desired behavior).
Quoted 23 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi usbphy: phy@1c19400 { · line 337
Quoted 11 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +10
-0+ status = "disabled"; + }; + + ohci: usb@1c1a400 { + compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;... and here.
That would be definitely the right thing to do, but please check whether it still works, especially OTG operation.
The addresses, clocks, resets and interrupts match the manual.
Cheers,
Andre.
Quoted 7 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi usbphy: phy@1c19400 { · line 343
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +3
-0+ status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>;
Thank you,
Chris
Re: [PATCH V3 6/8] ARM: dts: sun8i: v3s: add EHCI and OHCI to v3s dts
On Fri, 25 Aug 2023 10:58:00 -0500
Chris Morgan <[email protected]> wrote:
Hi Chris,
Quoted 43 lines · Andre Przywara
Quoted 5 lines
On Wed, 23 Aug 2023 16:25:52 -0500
Chris Morgan <[email protected]> wrote:Hi Chris,
Quoted 7 lines
Quoted 4 lines
From: Chris Morgan <[email protected]>
Add the EHCI and OHCI controller to the Allwinner v3s to support using USB in host mode.
Alright, so was it really that easy? I was afraid we left out host mode for a reason back then ....
Can't speak to that, but it is working for me as both a host and a gadget.
Quoted 23 lines
Quoted 12 lines
Signed-off-by Chris Morgan <[email protected]>--- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +0
-0arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi usbphy: phy@1c19400 { · line 327
Quoted 9 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +6
-0@@ -319,6 +319,25 @@ usbphy: phy@1c19400 { #phy-cells = <1>; }; + ehci: usb@1c1a000 { + compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;Please add the link the PHY here:
Quoted 2 lines
phys = <&usbphy 0>; phy-names = "usb";
Quoted 2 lines
usbphy 0 doesn't work, but if I do phys = <&usbphy 1>; for here and the OHCI node it does work. Is that expected/acceptable?
Well, that means it doesn't work, because the V3s has only one PHY, so "1" is invalid, and will either be ignored or rejected (any hints in dmesg?)
Quoted 5 lines
By "doesn't work"
I mean the device is always in HOST mode if I use 0 and switches correctly (the extcon shows HOST=0 when unplugged or plugged into my computer, and shows HOST=1 if I plug in a device which I assume is the desired behavior).
You mean the latter part was with <usbphy 1>, and that's the same behaviour as without the property?
That would mean that this part is still broken - I think somewhere in the PHY driver. But this is a generic issue, and not specific to the V3s, and your patch is just revealing it.
I will try to have a look in the next few days, to find the real culprit.
Cheers,
Andre
Quoted 33 lines
Quoted 22 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi usbphy: phy@1c19400 { · line 337
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +10
-0+ status = "disabled"; + }; + + ohci: usb@1c1a400 { + compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;... and here.
That would be definitely the right thing to do, but please check whether it still works, especially OTG operation.
The addresses, clocks, resets and interrupts match the manual.
Cheers,
Andre.Quoted 7 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi usbphy: phy@1c19400 { · line 343
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +3
-0+ status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>;Thank you,
Chris
Re: [PATCH V3 6/8] ARM: dts: sun8i: v3s: add EHCI and OHCI to v3s dts
Quoted 48 lines · Andre Przywara
On Fri, 25 Aug 2023 10:58:00 -0500
Chris Morgan <[email protected]> wrote:Hi Chris,
Quoted 43 lines · Andre Przywara
Quoted 5 lines
On Wed, 23 Aug 2023 16:25:52 -0500
Chris Morgan <[email protected]> wrote:Hi Chris,
Quoted 7 lines
Quoted 4 lines
From: Chris Morgan <[email protected]>
Add the EHCI and OHCI controller to the Allwinner v3s to support using USB in host mode.
Alright, so was it really that easy? I was afraid we left out host mode for a reason back then ....
Can't speak to that, but it is working for me as both a host and a gadget.
Quoted 25 lines
Quoted 12 lines
Signed-off-by Chris Morgan <[email protected]>--- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +0
-0arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi usbphy: phy@1c19400 { · line 327
Quoted 9 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +6
-0@@ -319,6 +319,25 @@ usbphy: phy@1c19400 { #phy-cells = <1>; }; + ehci: usb@1c1a000 { + compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;Please add the link the PHY here:
phys = <&usbphy 0>; phy-names = "usb";
Quoted 6 lines
Quoted 2 lines
usbphy 0 doesn't work, but if I do phys = <&usbphy 1>; for here and the OHCI node it does work. Is that expected/acceptable?
Well, that means it doesn't work, because the V3s has only one PHY, so "1" is invalid, and will either be ignored or rejected (any hints in dmesg?)
Nothing in dmesg that I can see.
Quoted 7 lines
Quoted 6 lines
By "doesn't work"
I mean the device is always in HOST mode if I use 0 and switches correctly (the extcon shows HOST=0 when unplugged or plugged into my computer, and shows HOST=1 if I plug in a device which I assume is the desired behavior).
Quoted 8 lines
You mean the latter part was with <usbphy 1>, and that's the same behaviour as without the property?
That would mean that this part is still broken - I think somewhere in the PHY driver. But this is a generic issue, and not specific to the V3s, and your patch is just revealing it.I will try to have a look in the next few days, to find the real culprit.
Yep. <usbphy 0> means it stays in host mode; no phy or <usbphy 1> means it works in both. For now I'll set it to the proper usbphy 0 and note that for the moment otg doesn't work. Unlike the problem with the RTC regulator this doesn't really harm the overall experience; and for now anyone making custom firmware that relies on OTG can simply delete the phy property and it will work.
V4 incoming soon. Thank you.
Chris
Quoted 38 lines
Cheers,
AndreQuoted 33 lines
Quoted 22 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi usbphy: phy@1c19400 { · line 337
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +10
-0+ status = "disabled"; + }; + + ohci: usb@1c1a400 { + compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;... and here.
That would be definitely the right thing to do, but please check whether it still works, especially OTG operation.
The addresses, clocks, resets and interrupts match the manual.
Cheers,
Andre.Quoted 7 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi usbphy: phy@1c19400 { · line 343
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +3
-0+ status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>;Thank you,
Chris
PATCH v3 7/8 dt-bindings: arm: sunxi: add Anbernic RG-Nano
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a portable handheld console from Anbernic which uses the Allwinner V3s SoC.
--- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+)
Documentation/devicetree/bindings/arm/sunxi.yaml +5 -0
@@ -56,6 +56,11 @@ properties: - const: amarula,a64-relic - const: allwinner,sun50i-a64 + - description: Anbernic RG-Nano + items: + - const: anbernic,rg-nano + - const: allwinner,sun8i-v3s + - description: Auxtek T003 A10s HDMI TV Stick items: - const: allwinner,auxtek-t003
Signature · 1 line
2.34.1
PATCH v3 8/8 ARM: dts: sunxi: add support for Anbernic RG-Nano
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a small portable game device based on the Allwinner V3s SoC. It has GPIO buttons on the face and side for input, a single mono speaker, a 240x240 SPI controlled display, a USB-C OTG port, an SD card slot for booting, and 64MB of RAM included in the SoC.
Working/Tested:
- SDMMC
- UART (for debugging)
- Buttons
- Charging/battery/PMIC
- Speaker
- USB Host and Gadget
- Display (at 60hz)
--- arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 275 ++++++++++++++++++ 2 files changed, 276 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
arch/arm/boot/dts/allwinner/Makefile +1 -0
@@ -237,6 +237,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-anbernic-rg-nano.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtb
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +275 -0
275 lines not on this page · raw message
Signature · 1 line
2.34.1
Re: [PATCH V3 8/8] ARM: dts: sunxi: add support for Anbernic RG-Nano
On Wed, 23 Aug 2023 16:25:54 -0500
Chris Morgan <[email protected]> wrote:
Hi,
Quoted 8 lines
From: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a small portable game device based on the Allwinner V3s SoC. It has GPIO buttons on the face and side for input, a single mono speaker, a 240x240 SPI controlled display, a USB-C OTG port, an SD card slot for booting, and 64MB of RAM included in the SoC.
Quoted 8 lines
Working/Tested:
- SDMMC
- UART (for debugging)
- Buttons
- Charging/battery/PMIC
- Speaker
- USB Host and Gadget
- Display (at 60hz)
So this works now purely in software, by the panel driver constantly scanning out a framebuffer region via SPI?
I wonder if enabling DMA support for SPI then helps the CPU load? Though this might be a performance optimisation in a later patch set (as it requires adding support for the V3s DMA controller).
Quoted 125 lines
Signed-off-by Chris Morgan <[email protected]>--- arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 275 ++++++++++++++++++ 2 files changed, 276 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dtsarch/arm/boot/dts/allwinner/Makefile +1
-0@@ -237,6 +237,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-anbernic-rg-nano.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtbarch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +99
-0@@ -0,0 +1,275 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "sun8i-v3s.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Anbernic RG Nano"; + compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s"; + + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>; + default-brightness-level = <11>; + power-supply = <®_vcc5v0>; + pwms = <&pwm 0 40000 1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + button-a { + gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-A"; + linux,code = <BTN_EAST>; + }; + + button-b { + gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-B"; + linux,code = <BTN_SOUTH>; + }; + + button-down { + gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-left { + gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-right { + gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-se { + gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-SELECT"; + linux,code = <BTN_SELECT>; + }; + + button-st { + gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-START"; + linux,code = <BTN_START>; + }; + + button-tl { + gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-L"; + linux,code = <BTN_TL>; + }; + + button-tr { + gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-R"; + linux,code = <BTN_TR>; + }; + + button-up { + gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-X"; + linux,code = <BTN_NORTH>; + }; + + button-y { + gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-Y";
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 109
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ linux,code = <BTN_WEST>; + }; + }; +}; + +&codec { + allwinner,audio-routing = "Speaker", "HP", + "MIC1", "Mic", + "Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
Can you please specify the pin number (PF6) as a comment here, as done in the other DTs? Because reading this "5 6" is not very intuitive. Same for the other &pio GPIO references.
Quoted 27 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +27
-0+ status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; + vcc-supply = <®_vcc3v3>; + }; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; + };
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 146
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +#include "axp209.dtsi" + +/* Out of alphabetical order for dependencies sake. */
I think you don't need this comment here.
Quoted 15 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +15
-0+&battery_power_supply { + status = "okay"; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&ohci { + status = "okay";
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 171
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+}; + +&pio { + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + spi0_3wire_pins: spi0-3wire-pins { + pins = "PC1", "PC2", "PC3";
Huh, interesting, is that because the display chip is purely unidirectional? In any case, can you add a comment saying what's going on, I guess: "MISO is not connected"?
And I wonder if "3 wire mode" is somewhat misleading here, since this seems to refer to bidirectional SPI over a combined MISO/MOSI line, and requires explicit controller support? Which the Allwinner controllers lack?
I think for the node and alias name that's fine, but a comment would clear things up.
The rest looks fine, though we would still need to fix the USB PHY issue.
Cheers,
Andre
Quoted 104 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +104
-0+ function = "spi0"; + }; +}; + +&pwm { + pinctrl-0 = <&pwm0_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */ +®_dcdc2 { + regulator-always-on; + regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1250000>; + regulator-name = "vdd-cpu"; +}; + +/* DCDC3 wired into every 3.3v input that isn't the RTC. */ +®_dcdc3 { + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +/* + * LDO1 wired into RTC, voltage is hard-wired at 3.3v and cannot be + * software modified. Note that setting voltage here to 3.3v for accuracy + * sake causes an issue with the driver that causes it to fail to probe + * because of a voltage constraint in the driver. + */ +®_ldo1 { + regulator-always-on; + regulator-name = "vcc-rtc"; +}; + +/* LDO2 wired into VCC-PLL and audio codec. */ +®_ldo2 { + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc-pll"; +}; + +/* LDO3, LDO4, and LDO5 unused. */ +®_ldo3 { + status = "disabled"; +}; + +®_ldo4 { + status = "disabled"; +}; + +&spi0 { + pinctrl-0 = <&spi0_3wire_pins>; + pinctrl-names = "default"; + status = "okay"; + + display@0 { + compatible = "saef,sftc154b", "panel-mipi-dbi-spi"; + reg = <0>; + backlight = <&backlight>; + dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <100000000>; + + height-mm = <39>; + width-mm = <39>; + + /* Set hb-porch to compensate for non-visible area */ + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <80>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + status = "okay"; +};
Re: [PATCH V3 8/8] ARM: dts: sunxi: add support for Anbernic RG-Nano
Quoted 22 lines · Andre Przywara
On Wed, 23 Aug 2023 16:25:54 -0500
Chris Morgan <[email protected]> wrote:Hi,
Quoted 8 lines
From: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a small portable game device based on the Allwinner V3s SoC. It has GPIO buttons on the face and side for input, a single mono speaker, a 240x240 SPI controlled display, a USB-C OTG port, an SD card slot for booting, and 64MB of RAM included in the SoC.
Quoted 8 lines
Working/Tested:
- SDMMC
- UART (for debugging)
- Buttons
- Charging/battery/PMIC
- Speaker
- USB Host and Gadget
- Display (at 60hz)
Quoted 5 lines
So this works now purely in software, by the panel driver constantly scanning out a framebuffer region via SPI?
I wonder if enabling DMA support for SPI then helps the CPU load? Though this might be a performance optimisation in a later patch set (as it requires adding support for the V3s DMA controller).
I think it's already enabled, at least I see it in /sys/kernel/debug/dmaengine/summary:
dma0chan0 | 1c68000.spi:tx
dma0chan1 | 1c68000.spi:rx
The idle CPU usage and CPU usage when running kmscube don't seem too terrible, but I'm always open to improvements.
Quoted 132 lines
Quoted 132 lines
Signed-off-by Chris Morgan <[email protected]>--- arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 275 ++++++++++++++++++ 2 files changed, 276 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dtsarch/arm/boot/dts/allwinner/Makefile +1
-0@@ -237,6 +237,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-anbernic-rg-nano.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtbarch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +105
-0@@ -0,0 +1,275 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "sun8i-v3s.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Anbernic RG Nano"; + compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s"; + + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>; + default-brightness-level = <11>; + power-supply = <®_vcc5v0>; + pwms = <&pwm 0 40000 1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + button-a { + gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-A"; + linux,code = <BTN_EAST>; + }; + + button-b { + gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-B"; + linux,code = <BTN_SOUTH>; + }; + + button-down { + gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-left { + gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-right { + gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-se { + gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-SELECT"; + linux,code = <BTN_SELECT>; + }; + + button-st { + gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-START"; + linux,code = <BTN_START>; + }; + + button-tl { + gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-L"; + linux,code = <BTN_TL>; + }; + + button-tr { + gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-R"; + linux,code = <BTN_TR>; + }; + + button-up { + gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-X"; + linux,code = <BTN_NORTH>; + }; + + button-y { + gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-Y"; + linux,code = <BTN_WEST>; + }; + }; +}; + +&codec {
Quoted 9 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 109
Quoted 4 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +4
-0+ allwinner,audio-routing = "Speaker", "HP", + "MIC1", "Mic", + "Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;Can you please specify the pin number (PF6) as a comment here, as done in the other DTs? Because reading this "5 6" is not very intuitive. Same for the other &pio GPIO references.
Will do. Thank you.
Quoted 31 lines
Quoted 31 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +31
-0+ status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; + vcc-supply = <®_vcc3v3>; + }; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>;
Quoted 9 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 146
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ }; +}; + +#include "axp209.dtsi" + +/* Out of alphabetical order for dependencies sake. */I think you don't need this comment here.
Okay, I'll remove it. It just looked out of order so I thought explaining it was warranted.
Quoted 27 lines
Quoted 15 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +15
-0+&battery_power_supply { + status = "okay"; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&ohci { + status = "okay";arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 171
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+}; + +&pio { + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + spi0_3wire_pins: spi0-3wire-pins { + pins = "PC1", "PC2", "PC3";Huh, interesting, is that because the display chip is purely
Quoted 8 lines
unidirectional? In any case, can you add a comment saying what's going on, I guess: "MISO is not connected"?
And I wonder if "3 wire mode" is somewhat misleading here, since this seems to refer to bidirectional SPI over a combined MISO/MOSI line, and requires explicit controller support? Which the Allwinner controllers lack?
I think for the node and alias name that's fine, but a comment would clear things up.
Yeah, I originally thought that's what it was doing but nope. The MOSI, CLK, and CS pins are hooked up to the MOSI, CLK, and CS pins of the panel. The MISO pin is hooked up to the RS/DC pin (which switches between command and data mode). There's also a reset pin as well as a tear pin that's hooked to PB1. I'll rename the node to be less confusing and leave a comment as such. If it turns out we need the tear pin I'll either find a way to add it to the generic driver I'm using now or write a driver just for this panel.
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The rest looks fine, though we would still need to fix the USB PHY issue.
Yeah, crazy thing that defining it correctly (where OHCI, EHCI and OTG are all on <usbphy 0>) actually appears to cause it to not work. I got a single message in my dmesg log that it was setting it to host mode, and when I unplugged it the extcon kept saying it was host. However, when I didn't have the phy defined on OHCI/EHCI or I set it incorrect as <usbphy 1> it worked. Of course defining ldo1 correctly also broke stuff...
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Cheers,
AndreQuoted 96 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +96
-0+ function = "spi0"; + }; +}; + +&pwm { + pinctrl-0 = <&pwm0_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */ +®_dcdc2 { + regulator-always-on; + regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1250000>; + regulator-name = "vdd-cpu"; +}; + +/* DCDC3 wired into every 3.3v input that isn't the RTC. */ +®_dcdc3 { + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +/* + * LDO1 wired into RTC, voltage is hard-wired at 3.3v and cannot be + * software modified. Note that setting voltage here to 3.3v for accuracy + * sake causes an issue with the driver that causes it to fail to probe + * because of a voltage constraint in the driver. + */ +®_ldo1 { + regulator-always-on; + regulator-name = "vcc-rtc"; +}; + +/* LDO2 wired into VCC-PLL and audio codec. */ +®_ldo2 { + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc-pll"; +}; + +/* LDO3, LDO4, and LDO5 unused. */ +®_ldo3 { + status = "disabled"; +}; + +®_ldo4 { + status = "disabled"; +}; + +&spi0 { + pinctrl-0 = <&spi0_3wire_pins>; + pinctrl-names = "default"; + status = "okay"; + + display@0 { + compatible = "saef,sftc154b", "panel-mipi-dbi-spi"; + reg = <0>; + backlight = <&backlight>; + dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <100000000>; + + height-mm = <39>; + width-mm = <39>; + + /* Set hb-porch to compensate for non-visible area */ + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <80>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; +
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 275
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +8
-0+&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + status = "okay"; +};
Thank you,
Chris