riscv: errata: improve T-Head CMO
v2 cover riscv: errata: improve T-Head CMO
This is a renew of Icenowy patch series[1], patch1 is necessary to make T-Head C910 powered SoCs CMO work correctly. patch2 is to name those instructions following thead-extension-spec.
Icenowy Zheng (2):
riscv: errata: fix T-Head dcache.cva encoding
riscv: errata: prefix T-Head mnemonics with th.
arch/riscv/include/asm/errata_list.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
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PATCH v2 1/2 riscv: errata: fix T-Head dcache.cva encoding
From: Icenowy Zheng <[email protected]>
The dcache.cva encoding shown in the comments are wrong, it's for dcache.cval1 (which is restricted to L1) instead.
Fix this in the comment and in the hardcoded instruction.
--- arch/riscv/include/asm/errata_list.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/riscv/include/asm/errata_list.h +2 -2
@@ -100,7 +100,7 @@ asm volatile(ALTERNATIVE( \* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000001 01001 rs1 000 00000 0001011 * dcache.cva rs1 (clean, virtual address) -* 0000001 00100 rs1 000 00000 0001011 +* 0000001 00101 rs1 000 00000 0001011 * * dcache.cipa rs1 (clean then invalidate, physical address) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
@@ -113,7 +113,7 @@ asm volatile(ALTERNATIVE( \* 0000000 11001 00000 000 00000 0001011 */ #define THEAD_inval_A0 ".long 0x0265000b" -#define THEAD_clean_A0 ".long 0x0245000b" +#define THEAD_clean_A0 ".long 0x0255000b"#define THEAD_flush_A0 ".long 0x0275000b"#define THEAD_SYNC_S ".long 0x0190000b"
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Re: [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding
Quoted 40 lines · Jisheng Zhang
From: Icenowy Zheng <[email protected]>
The dcache.cva encoding shown in the comments are wrong, it's for dcache.cval1 (which is restricted to L1) instead.
Fix this in the comment and in the hardcoded instruction.
Signed-off-by Icenowy Zheng <[email protected]>Tested-by Sergey Matyukevich <[email protected]>Reviewed-by Heiko Stuebner <[email protected]>Reviewed-by Guo Ren <[email protected]>--- arch/riscv/include/asm/errata_list.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)arch/riscv/include/asm/errata_list.h +2
-2@@ -100,7 +100,7 @@ asm volatile(ALTERNATIVE( \* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000001 01001 rs1 000 00000 0001011 * dcache.cva rs1 (clean, virtual address) -* 0000001 00100 rs1 000 00000 0001011 +* 0000001 00101 rs1 000 00000 0001011 * * dcache.cipa rs1 (clean then invalidate, physical address) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | @@ -113,7 +113,7 @@ asm volatile(ALTERNATIVE( \* 0000000 11001 00000 000 00000 0001011 */ #define THEAD_inval_A0 ".long 0x0265000b" -#define THEAD_clean_A0 ".long 0x0245000b" +#define THEAD_clean_A0 ".long 0x0255000b"#define THEAD_flush_A0 ".long 0x0275000b"#define THEAD_SYNC_S ".long 0x0190000b"Signature · 1 line
2.40.1
I applied this on top of the emmc series [1] and the dma-noncoherent dts patch [2]. SDMA is now working with this patch applied. Before this patch, the filesystems on the emmc were corrupted after mounting. It makes sense that problem is solved by the correct cache clean instruction being used.
Thanks,
Drew
[1] https://lore.kernel.org/linux-riscv/[email protected]/
[2] https://lore.kernel.org/linux-riscv/ZOIBQI3L4kP7c%2FT1@xhacker/
Re: [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding
Quoted 44 lines · Drew Fustini
Quoted 40 lines · Jisheng Zhang
From: Icenowy Zheng <[email protected]>
The dcache.cva encoding shown in the comments are wrong, it's for dcache.cval1 (which is restricted to L1) instead.
Fix this in the comment and in the hardcoded instruction.
Signed-off-by Icenowy Zheng <[email protected]>Tested-by Sergey Matyukevich <[email protected]>Reviewed-by Heiko Stuebner <[email protected]>Reviewed-by Guo Ren <[email protected]>--- arch/riscv/include/asm/errata_list.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)arch/riscv/include/asm/errata_list.h +2
-2@@ -100,7 +100,7 @@ asm volatile(ALTERNATIVE( \* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000001 01001 rs1 000 00000 0001011 * dcache.cva rs1 (clean, virtual address) -* 0000001 00100 rs1 000 00000 0001011 +* 0000001 00101 rs1 000 00000 0001011 * * dcache.cipa rs1 (clean then invalidate, physical address) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | @@ -113,7 +113,7 @@ asm volatile(ALTERNATIVE( \* 0000000 11001 00000 000 00000 0001011 */ #define THEAD_inval_A0 ".long 0x0265000b" -#define THEAD_clean_A0 ".long 0x0245000b" +#define THEAD_clean_A0 ".long 0x0255000b"#define THEAD_flush_A0 ".long 0x0275000b"#define THEAD_SYNC_S ".long 0x0190000b"Signature · 1 line
2.40.1Tested-by Drew Fustini <[email protected]>
Quoted 5 lines
I applied this on top of the emmc series [1] and the dma-noncoherent dts patch [2]. SDMA is now working with this patch applied. Before this patch, the filesystems on the emmc were corrupted after mounting. It makes sense that problem is solved by the correct cache clean instruction being used.
Even better, ADMA is now working in sdhci-of-dwcmshc too.
I'll respin my eMMC series.
Thanks,
Drew
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PATCH v2 2/2 riscv: errata: prefix T-Head mnemonics with th.
In reply to Jisheng ZhangFrom: Icenowy Zheng <[email protected]>
T-Head now maintains some specification for their extended instructions at [1], in which all instructions are prefixed "th.".
Follow this practice in the kernel comments.
--- arch/riscv/include/asm/errata_list.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
arch/riscv/include/asm/errata_list.h +7 -7
@@ -90,25 +90,25 @@ asm volatile(ALTERNATIVE( \#endif /* -* dcache.ipa rs1 (invalidate, physical address) +* th.dcache.ipa rs1 (invalidate, physical address) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000001 01010 rs1 000 00000 0001011 -* dache.iva rs1 (invalida, virtual address) +* th.dache.iva rs1 (invalida, virtual address) * 0000001 00110 rs1 000 00000 0001011 * -* dcache.cpa rs1 (clean, physical address) +* th.dcache.cpa rs1 (clean, physical address) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000001 01001 rs1 000 00000 0001011 -* dcache.cva rs1 (clean, virtual address) +* th.dcache.cva rs1 (clean, virtual address) * 0000001 00101 rs1 000 00000 0001011 * -* dcache.cipa rs1 (clean then invalidate, physical address) +* th.dcache.cipa rs1 (clean then invalidate, physical address) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000001 01011 rs1 000 00000 0001011 -* dcache.civa rs1 (... virtual address) +* th.dcache.civa rs1 (... virtual address) * 0000001 00111 rs1 000 00000 0001011 * -* sync.s (make sure all cache operations finished) +* th.sync.s (make sure all cache operations finished) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000000 11001 00000 000 00000 0001011 */
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Re: [PATCH v2 2/2] riscv: errata: prefix T-Head mnemonics with th.
Quoted 38 lines · Jisheng Zhang
From: Icenowy Zheng <[email protected]>
T-Head now maintains some specification for their extended instructions at [1], in which all instructions are prefixed "th.".
Follow this practice in the kernel comments.
Signed-off-by Icenowy Zheng <[email protected]>--- arch/riscv/include/asm/errata_list.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)arch/riscv/include/asm/errata_list.h +4
-4@@ -90,25 +90,25 @@ asm volatile(ALTERNATIVE( \#endif /* -* dcache.ipa rs1 (invalidate, physical address) +* th.dcache.ipa rs1 (invalidate, physical address) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000001 01010 rs1 000 00000 0001011 -* dache.iva rs1 (invalida, virtual address) +* th.dache.iva rs1 (invalida, virtual address) * 0000001 00110 rs1 000 00000 0001011 * -* dcache.cpa rs1 (clean, physical address) +* th.dcache.cpa rs1 (clean, physical address) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000001 01001 rs1 000 00000 0001011 -* dcache.cva rs1 (clean, virtual address) +* th.dcache.cva rs1 (clean, virtual address) * 0000001 00101 rs1 000 00000 0001011 *
arch/riscv/include/asm/errata_list.h asm volatile(ALTERNATIVE( \ · line 111
Quoted 10 lines
arch/riscv/include/asm/errata_list.h +3
-3-* dcache.cipa rs1 (clean then invalidate, physical address) +* th.dcache.cipa rs1 (clean then invalidate, physical address) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000001 01011 rs1 000 00000 0001011 -* dcache.civa rs1 (... virtual address) +* th.dcache.civa rs1 (... virtual address) * 0000001 00111 rs1 000 00000 0001011 * -* sync.s (make sure all cache operations finished) +* th.sync.s (make sure all cache operations finished)
Quoted 6 lines
arch/riscv/include/asm/errata_list.h +0
-1* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000000 11001 00000 000 00000 0001011 */ --2.40.1
--
Best Regards
Guo Ren
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Quoted 3 lines · Jisheng Zhang
This is a renew of Icenowy patch series[1], patch1 is necessary to make T-Head C910 powered SoCs CMO work correctly. patch2 is to name those instructions following thead-extension-spec.
Original series:
https://lore.kernel.org/linux-riscv/[email protected]/
Quoted 16 lines
Icenowy Zheng (2):
riscv: errata: fix T-Head dcache.cva encoding
riscv: errata: prefix T-Head mnemonics with th.arch/riscv/include/asm/errata_list.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)Signature · 7 lines
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This series was applied to riscv/linux.git (fixes) by Palmer Dabbelt <[email protected]>:
Hello:
This series was applied to riscv/linux.git (fixes) by Palmer Dabbelt <[email protected]>:
Quoted 9 lines · On Sun, 27 Aug 2023 17:08:11 +0800 you wrote:
This is a renew of Icenowy patch series[1], patch1 is necessary to make T-Head C910 powered SoCs CMO work correctly. patch2 is to name those instructions following thead-extension-spec.
Icenowy Zheng (2):
riscv: errata: fix T-Head dcache.cva encoding
riscv: errata: prefix T-Head mnemonics with th.[...]
Here is the summary with links:
- [v2,1/2] riscv: errata: fix T-Head dcache.cva encoding
https://git.kernel.org/riscv/c/8eb8fe67e2c8
- [v2,2/2] riscv: errata: prefix T-Head mnemonics with th. (no matching commit)
You are awesome, thank you!
Signature · 2 lines
Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <[email protected]>:
Hello:
This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <[email protected]>:
Quoted 9 lines · On Sun, 27 Aug 2023 17:08:11 +0800 you wrote:
This is a renew of Icenowy patch series[1], patch1 is necessary to make T-Head C910 powered SoCs CMO work correctly. patch2 is to name those instructions following thead-extension-spec.
Icenowy Zheng (2):
riscv: errata: fix T-Head dcache.cva encoding
riscv: errata: prefix T-Head mnemonics with th.[...]
Here is the summary with links:
- [v2,1/2] riscv: errata: fix T-Head dcache.cva encoding (no matching commit)
- [v2,2/2] riscv: errata: prefix T-Head mnemonics with th.
https://git.kernel.org/riscv/c/c1c99e5f1b13
You are awesome, thank you!
Signature · 9 lines
Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv