pinctrl: nuvoton: add pinmux and GPIO driver for NPCM8XX
Subsystems (4)
Tomer Maimon
maintainerv6 cover pinctrl: nuvoton: add pinmux and GPIO driver for NPCM8XX
This patch set adds pinmux and GPIO controller for the Arbel NPCM8XX Baseboard Management Controller (BMC).
Arbel BMC NPCM8XX pinctrl driver based on Poleg NPCM7XX, except the pin mux mapping difference the NPCM8XX GPIO supports adjust debounce period time.
Arbel BMC NPCM8XX Pinmux functions accessible only for pin groups and pin configuration parameters available only for individual pins.
Arbel BMC NPCM8XX has eight identical GPIO modules, each module has 32 GPIO ports.
Most of the GPIO ports are multiplexed with other system functions.
The NPCM8XX pinctrl and GPIO driver were tested on NPCM845 evaluation board.
Addressed comments from:
- Rob Herring: https://lore.kernel.org/lkml/[email protected]/
- Krzysztof Kozlowski: https://lore.kernel.org/lkml/[email protected]/
Changes since version 5:
- Pin controller dt-binding
- Modify gpio unit-address.
- Remove blank line at EOF.
Changes since version 4:
- Pin controller driver
- Modify DS definition.
- Pin controller dt-binding
- Modify -mux pattern.
- Remove tabs.
Changes since version 3:
- Pin controller driver
- Remove unused line in Kconfig.
- Add GPIO 183-189 GPIO support.
- Add SPI1 CS pins.
- Modify SMB23b pin list.
- Remove unused module pins.
- Fix PIN-CONFIG_OUTPUT setting.
- Pin controller dt-binding
- Modify pin and function items.
- Use consistent quotes.
- drop unneseccary quote.
- pincrtl node name modify to pinctrl@f0800260 since
the pin controller handling was done in 0xf0800260
offset.Changes since version 2:
- Pin controller driver
- Modify kernel configuration.
- Adding and removing include files.
- Using the same register format size.
- Reducing lines by command combination.
- Remove unnecessary parentheses use.
- Use GENMASK and BIT macros.
- Using traditional patterns.
- Pin controller dt-binding
- Modify GPIO description.
- pintcrtl node name, Sorry, I know we have a long discussion about it. Still, I think the best header pinctrl node name is pinctrl@f0800000. because the pin mux is handled through the GCR.
BTW, same pinctrl header name is used in the NPCM7XX pinctrl version. https://elixir.bootlin.com/linux/v6.0-rc6/source/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi#L560
Changes since version 1:
- Pin controller driver
- Remove unnecessary debug prints and comments.
- Use fwnode functions.
- Remove Redundant 'else'.
- Use switch case instead of else if.
- Use GENMASK and BIT macros.
- Use dev_err_probe in probe error.
- Use callback GPIO range.
- Add GCR phandle property.
- Parameter order in reversed xmas
- Pin controller dt-binding
- Modify name from pin to mux.
- Add phandle property.
Tomer Maimon (2):
dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation
pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO driver
.../pinctrl/nuvoton,npcm845-pinctrl.yaml | 214 ++ drivers/pinctrl/nuvoton/Kconfig | 14 + drivers/pinctrl/nuvoton/Makefile | 1 + drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 2491 +++++++++++++++++ 4 files changed, 2720 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
Signature · 1 line
2.33.0
Tomer Maimon
maintainerPATCH v6 1/2 dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation
Added device tree binding documentation for Nuvoton Arbel BMC NPCM8XX pinmux and GPIO controller.
--- .../pinctrl/nuvoton,npcm845-pinctrl.yaml | 214 ++++++++++++++++++ 1 file changed, 214 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +214 -0
@@ -0,0 +1,214 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,npcm845-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM845 Pin Controller and GPIO + +maintainers: + - Tomer Maimon <[email protected]> + +description: + The Nuvoton BMC NPCM8XX Pin Controller multi-function routed through + the multiplexing block, Each pin supports GPIO functionality (GPIOx) + and multiple functions that directly connect the pin to different + hardware blocks. + +properties: + compatible: + const: nuvoton,npcm845-pinctrl + + ranges: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + nuvoton,sysgcr: + $ref: /schemas/types.yaml#/definitions/phandle + description: a phandle to access GCR registers. + +patternProperties: + '^gpio@': + type: object + + description: + Eight GPIO banks that each contain 32 GPIOs. + + properties: + gpio-controller: true + + '#gpio-cells': + const: 2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-ranges: + maxItems: 1 + + required: + - gpio-controller + - '#gpio-cells' + - reg + - interrupts + - gpio-ranges + + '-mux$': + $ref: pinmux-node.yaml# + + properties: + groups: + description: + One or more groups of pins to mux to a certain function + items: + enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, + smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b, + smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21, + smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3, + spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2, + spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2, + bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen, + r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3, + fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10, + fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2, + pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2, + ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, + smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, + sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, + mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk, + scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1, + spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den, + smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix, + spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4, + hgpio5, hgpio6, hgpio7 ] + + function: + description: + The function that a group of pins is muxed to + enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, + smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b, + smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21, + smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3, + spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2, + spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2, + bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen, + r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3, + fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10, + fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2, + pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2, + ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, + smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, + sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, + mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk, + scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1, + spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den, + smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix, + spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4, + hgpio5, hgpio6, hgpio7 ] + + dependencies: + groups: [ function ] + function: [ groups ] + + additionalProperties: false + + '^pin': + $ref: pincfg-node.yaml# + + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-low: true + + output-high: true + + drive-push-pull: true + + drive-open-drain: true + + input-debounce: + description: + Debouncing periods in microseconds, one period per interrupt + bank found in the controller + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + + slew-rate: + description: | + 0: Low rate + 1: High rate + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + drive-strength: + enum: [ 0, 1, 2, 4, 8, 12 ] + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - ranges + - '#address-cells' + - '#size-cells' + - nuvoton,sysgcr + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl: pinctrl@f0800260 { + compatible = "nuvoton,npcm845-pinctrl"; + ranges = <0x0 0x0 0xf0010000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + nuvoton,sysgcr = <&gcr>; + + gpio0: gpio@0 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0xB0>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 0 32>; + }; + + fanin0_pin: fanin0-mux { + groups = "fanin0"; + function = "fanin0"; + }; + + pin34_slew: pin34-slew { + pins = "GPIO34/I3C4_SDA"; + bias-disable; + }; + }; + };
Signature · 1 line
2.33.0
Re: [PATCH v6 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation
Quoted 8 lines · Tomer Maimon
Added device tree binding documentation for Nuvoton Arbel BMC NPCM8XX pinmux and GPIO controller.
Signed-off-by Tomer Maimon <[email protected]>Reviewed-by Rob Herring <[email protected]>---
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml line 130
Quoted 8 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +8
-0+ '^pin': + $ref: pincfg-node.yaml# + + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing
What pin names are allowed?
Quoted 49 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +49
-0+ + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-low: true + + output-high: true + + drive-push-pull: true + + drive-open-drain: true + + input-debounce: + description: + Debouncing periods in microseconds, one period per interrupt + bank found in the controller + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + + slew-rate: + description: | + 0: Low rate + 1: High rate + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + drive-strength: + enum: [ 0, 1, 2, 4, 8, 12 ] + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - ranges + - '#address-cells' + - '#size-cells' + - nuvoton,sysgcr + +additionalProperties: false +
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml line 189
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Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +10
-0+examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl: pinctrl@f0800260 {
Nothing improved here. Test your DTS. This is being reported - I checked.
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml line 199
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +10
-0+ compatible = "nuvoton,npcm845-pinctrl"; + ranges = <0x0 0x0 0xf0010000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + nuvoton,sysgcr = <&gcr>; + + gpio0: gpio@0 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0xB0>;
Keep lowercase hex.
Best regards,
Krzysztof
Tomer Maimon
maintainerRe: [PATCH v6 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation
Hi Krzysztof,
Thanks for your comments
Quoted 19 lines · Krzysztof Kozlowski
Quoted 8 lines · Tomer Maimon
Added device tree binding documentation for Nuvoton Arbel BMC NPCM8XX pinmux and GPIO controller.
Signed-off-by Tomer Maimon <[email protected]>Reviewed-by Rob Herring <[email protected]>---
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml line 130
Quoted 8 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +8
-0+ '^pin': + $ref: pincfg-node.yaml# + + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing
Quoted 1 line
What pin names are allowed?
Do you mean to describe all the allowed pin items?
for example:
items:
pattern:
'GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA|GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL' or
items:
pattern: '^GPIO([0-9]|[0-9][0-9]|[1-2][0-4][0-9]|25[0-6])$'is good enough?
Quoted 54 lines
Quoted 54 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +53
-0+ + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-low: true + + output-high: true + + drive-push-pull: true + + drive-open-drain: true + + input-debounce: + description: + Debouncing periods in microseconds, one period per interrupt + bank found in the controller + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + + slew-rate: + description: | + 0: Low rate + 1: High rate + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + drive-strength: + enum: [ 0, 1, 2, 4, 8, 12 ] + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - ranges + - '#address-cells' + - '#size-cells' + - nuvoton,sysgcr + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h>
Quoted 8 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml line 189
Quoted 6 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +6
-0+ + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl: pinctrl@f0800260 {Nothing improved here. Test your DTS. This is being reported - I checked.
what do you suggest since the pinctrl doesn't have a reg parameter, maybe pinctrl: pinctrl@0?
BTW, I have run both dt_binding_check and W=1 dtbs_check, and didn't see an issue related to the pinctrl: pinctrl@f0800260, do I need to add another flag to see the issue?
Quoted 12 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml line 199
Quoted 11 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +10
-0+ compatible = "nuvoton,npcm845-pinctrl"; + ranges = <0x0 0x0 0xf0010000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + nuvoton,sysgcr = <&gcr>; + + gpio0: gpio@0 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0xB0>;
Quoted 1 line
Keep lowercase hex.
will be done in V7
Quoted 5 lines
Best regards,
Krzysztof
Best regards,
Tomer
Re: [PATCH v6 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation
Quoted 32 lines · Tomer Maimon
Hi Krzysztof,
Thanks for your comments
Quoted 19 lines · Krzysztof Kozlowski
Quoted 8 lines · Tomer Maimon
Added device tree binding documentation for Nuvoton Arbel BMC NPCM8XX pinmux and GPIO controller.
Signed-off-by Tomer Maimon <[email protected]>Reviewed-by Rob Herring <[email protected]>---
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml line 130
Quoted 8 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +8
-0+ '^pin': + $ref: pincfg-node.yaml# + + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncingQuoted 1 line
What pin names are allowed?
Do you mean to describe all the allowed pin items?
for example:
items:
pattern:
'GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA|GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL' or
Quoted 4 lines
items: pattern: '^GPIO([0-9]|[0-9][0-9]|[1-2][0-4][0-9]|25[0-6])$'is good enough?
Something like this. Whichever is correct.
Quoted 19 lines
Quoted 5 lines
Quoted 4 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +3
-0+ + bias-disable: true +Quoted 14 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml line 189
Quoted 12 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +12
-0+additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl: pinctrl@f0800260 {Nothing improved here. Test your DTS. This is being reported - I checked.
Quoted 2 lines
what do you suggest since the pinctrl doesn't have a reg parameter, maybe pinctrl: pinctrl@0?
It has ranges, so yes @0 looks correct here. Which leds to second question - how pinctrl could have @0? It's already taken by SoC! So your DTS here - unit address and ranges - are clearly wrong.
Quoted 3 lines
BTW, I have run both
dt_binding_checkand W=1dtbs_check, and didn't see an issue related to the pinctrl: pinctrl@f0800260, do I need to add another flag to see the issue?
Did you read my message last time? I said - it's about DTS, not the binding.
Best regards,
Krzysztof
Re: [PATCH v6 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation
Quoted 59 lines · Krzysztof Kozlowski
Quoted 32 lines · Tomer Maimon
Hi Krzysztof,
Thanks for your comments
Quoted 19 lines · Krzysztof Kozlowski
Quoted 8 lines · Tomer Maimon
Added device tree binding documentation for Nuvoton Arbel BMC NPCM8XX pinmux and GPIO controller.
Signed-off-by Tomer Maimon <[email protected]>Reviewed-by Rob Herring <[email protected]>---
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml line 130
Quoted 8 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +8
-0+ '^pin': + $ref: pincfg-node.yaml# + + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncingQuoted 1 line
What pin names are allowed?
Do you mean to describe all the allowed pin items?
for example:
items:
pattern:
'GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA|GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL' orQuoted 4 lines
items: pattern: '^GPIO([0-9]|[0-9][0-9]|[1-2][0-4][0-9]|25[0-6])$'is good enough?
Something like this. Whichever is correct.
Quoted 19 lines
Quoted 19 lines
Quoted 7 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +5
-0+ + bias-disable: true + +additionalProperties: false +Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml line 189
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +10
-0+examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl: pinctrl@f0800260 {Nothing improved here. Test your DTS. This is being reported - I checked.
Quoted 4 lines
Quoted 2 lines
what do you suggest since the pinctrl doesn't have a reg parameter, maybe pinctrl: pinctrl@0?
It has ranges, so yes @0 looks correct here.
Wait, your address according to ranges is 0xf0010000, not 0x0, not 0xf0800260...
Quoted 10 lines
Which leds to second
question - how pinctrl could have @0? It's already taken by SoC! So your DTS here - unit address and ranges - are clearly wrong.Quoted 3 lines
BTW, I have run both
dt_binding_checkand W=1dtbs_check, and didn't see an issue related to the pinctrl: pinctrl@f0800260, do I need to add another flag to see the issue?Did you read my message last time? I said - it's about DTS, not the binding.
Best regards,
Krzysztof
Tomer Maimon
maintainerRe: [PATCH v6 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation
Hi Krzysztof,
Thanks for your clarifications
Quoted 61 lines · Krzysztof Kozlowski
Quoted 59 lines · Krzysztof Kozlowski
Quoted 32 lines · Tomer Maimon
Hi Krzysztof,
Thanks for your comments
Quoted 19 lines · Krzysztof Kozlowski
Quoted 8 lines · Tomer Maimon
Added device tree binding documentation for Nuvoton Arbel BMC NPCM8XX pinmux and GPIO controller.
Signed-off-by Tomer Maimon <[email protected]>Reviewed-by Rob Herring <[email protected]>---
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml line 130
Quoted 8 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +8
-0+ '^pin': + $ref: pincfg-node.yaml# + + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncingQuoted 1 line
What pin names are allowed?
Do you mean to describe all the allowed pin items?
for example:
items:
pattern:
'GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA|GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL' orQuoted 4 lines
items: pattern: '^GPIO([0-9]|[0-9][0-9]|[1-2][0-4][0-9]|25[0-6])$'is good enough?
Something like this. Whichever is correct.
Quoted 19 lines
Quoted 19 lines
Quoted 7 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +5
-0+ + bias-disable: true + +additionalProperties: false +Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml line 189
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Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file +10
-0+examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl: pinctrl@f0800260 {Nothing improved here. Test your DTS. This is being reported - I checked.
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what do you suggest since the pinctrl doesn't have a reg parameter, maybe pinctrl: pinctrl@0?
It has ranges, so yes @0 looks correct here.
Wait, your address according to ranges is
0xf0010000, not0x0, not0xf0800260...
I will modify it to pinctrl: pinctrl@f0010000
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Which leds to second
question - how pinctrl could have @0? It's already taken by SoC! So your DTS here - unit address and ranges - are clearly wrong.
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BTW, I have run both
dt_binding_checkand W=1dtbs_check, and didn't see an issue related to the pinctrl: pinctrl@f0800260, do I need to add another flag to see the issue?Did you read my message last time? I said - it's about DTS, not the binding.
yes, understood doesn't the dtbs_check check the DTS?
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Best regards,
Krzysztof
Best regards,
Tomer
Re: [PATCH v6 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation
Quoted 6 lines · Tomer Maimon
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Which leds to second
question - how pinctrl could have @0? It's already taken by SoC! So your DTS here - unit address and ranges - are clearly wrong.
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BTW, I have run both
dt_binding_checkand W=1dtbs_check, and didn't see an issue related to the pinctrl: pinctrl@f0800260, do I need to add another flag to see the issue?Did you read my message last time? I said - it's about DTS, not the binding.
yes, understood doesn't the
dtbs_checkcheck the DTS?
Yes, it does, and the first error is being reported (just like several others for your DTS...). The second about gpio node, I think is not.
Best regards,
Krzysztof
Tomer Maimon
maintainerPATCH v6 2/2 pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO driver
In reply to Tomer MaimonAdd pinctrl and GPIO controller driver support to Arbel BMC NPCM8XX SoC.
Arbel BMC NPCM8XX pinctrl driver based on Poleg NPCM7XX, except the pin mux mapping difference the NPCM8XX GPIO supports adjust debounce period time.
--- drivers/pinctrl/nuvoton/Kconfig | 14 + drivers/pinctrl/nuvoton/Makefile | 1 + drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 2491 +++++++++++++++++++++ 3 files changed, 2506 insertions(+) create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
drivers/pinctrl/nuvoton/Kconfig +14 -0
@@ -32,3 +32,17 @@ config PINCTRL_NPCM7XX help Say Y here to enable pin controller and GPIO support for Nuvoton NPCM750/730/715/705 SoCs. + +config PINCTRL_NPCM8XX + tristate "Pinctrl and GPIO driver for Nuvoton NPCM8XX" + depends on ARCH_NPCM || COMPILE_TEST + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + help + Say Y or M here to enable pin controller and GPIO support for + the Nuvoton NPCM8XX SoC. This is strongly recommended when + building a kernel that will run on this chip.
drivers/pinctrl/nuvoton/Makefile +1 -0
@@ -3,3 +3,4 @@ obj-$(CONFIG_PINCTRL_WPCM450) += pinctrl-wpcm450.o obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o +obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c new file +2491 -0
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2.33.0
Re: [PATCH v6 2/2] pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO driver
Quoted 27 lines · Tomer Maimon
Add pinctrl and GPIO controller driver support to Arbel BMC NPCM8XX SoC.
Arbel BMC NPCM8XX pinctrl driver based on Poleg NPCM7XX, except the pin mux mapping difference the NPCM8XX GPIO supports adjust debounce period time.
Signed-off-by Tomer Maimon <[email protected]>--- drivers/pinctrl/nuvoton/Kconfig | 14 + drivers/pinctrl/nuvoton/Makefile | 1 + drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 2491 +++++++++++++++++++++ 3 files changed, 2506 insertions(+) create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.cdrivers/pinctrl/nuvoton/Kconfig +5
-0@@ -32,3 +32,17 @@ config PINCTRL_NPCM7XX help Say Y here to enable pin controller and GPIO support for Nuvoton NPCM750/730/715/705 SoCs. + +config PINCTRL_NPCM8XX + tristate "Pinctrl and GPIO driver for Nuvoton NPCM8XX" + depends on ARCH_NPCM || COMPILE_TEST + select PINMUX
drivers/pinctrl/nuvoton/Kconfig config PINCTRL_NPCM7XX · line 48
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drivers/pinctrl/nuvoton/Kconfig +9
-0+ select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + help + Say Y or M here to enable pin controller and GPIO support for + the Nuvoton NPCM8XX SoC. This is strongly recommended when + building a kernel that will run on this chip.
Still wrong. Please check your commit or your patches before sending.
Best regards,
Krzysztof