Add Anbernic RG-Nano
Subsystems (7)
v4 cover Add Anbernic RG-Nano
From: Chris Morgan <[email protected]>
Add support for the Anbernic RG-Nano handheld gaming device
Changes since V3:
- Added PHY to the OHCI and EHCI nodes. Note that the PHY driver currently forces the PHY to host mode always; a correction to the PHY driver or removal of the phy values from the OHCI and EHCI nodes are necessary to get otg mode working properly.
- Disabled SoC RTC in favor of external clock. The SoC RTC is not set up correctly in hardware and runs fast, whereas the external RTC keeps accurate time. This matches the BSP.
- Added labels to GPIO pins to aid in readability.
Changes since V2:
- Add display support.
- Add USB host support.
- Removed CPU frequency and voltage parameters, as CPU regulator may be tied into additional areas that need further testing.
- Added regulator names back, as they appear to have been accidentally dropped in v2.
- Updated notes to denote all hardware tested and working.
Changes since V1:
- Added additional pwm pin configs to sun8i-v3s.dtsi and removed default config for pwm0 in lieu of defining it for each board.
- Noted in patch notes that additional hardware of UART debug port, USB port (in gadget mode) also work, and that USB host mode does not work.
- Identified GPIO responsible for enabling external speaker amplifier and defined it, allowing onboard audio to work.
- Removed ac_power_supply node.
- Set regulator min and max values to the same value as defined in the schematics.
- Removed definition for reg_ldo1. This regulator is hardware configured so the value did not affect anything, however the driver must be updated to support the correct value of 3.3v in this case.
- Removed usb0_id_det-gpios as I cannot confirm these are correct.
Chris Morgan (8):
dt-bindings: vendor-prefixes: document Saef Technology
dt-bindings: display: panel: mipi-dbi-spi: add Saef SF-TC154B
arm: dts: sun8i: V3s: Add pinctrl for pwm
dt-bindings: usb: Add V3s compatible string for EHCI
dt-bindings: usb: Add V3s compatible string for OHCI
ARM: dts: sun8i: v3s: add EHCI and OHCI to v3s dts
dt-bindings: arm: sunxi: add Anbernic RG-Nano
ARM: dts: sunxi: add support for Anbernic RG-Nano
.../devicetree/bindings/arm/sunxi.yaml | 5 + .../display/panel/panel-mipi-dbi-spi.yaml | 1 + .../devicetree/bindings/usb/generic-ehci.yaml | 1 + .../devicetree/bindings/usb/generic-ohci.yaml | 1 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 284 ++++++++++++++++++ arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 35 +++ 8 files changed, 330 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Signature · 1 line
2.34.1
PATCH v4 1/8 dt-bindings: vendor-prefixes: document Saef Technology
From: Chris Morgan <[email protected]>
Document Saef Technology (https://www.saefdisplay.com/).
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/vendor-prefixes.yaml +2 -0
@@ -1151,6 +1151,8 @@ patternProperties: description: Shenzhen Roofull Technology Co, Ltd "^roseapplepi,.*": description: RoseapplePi.org + "^saef,.*": + description: Saef Technology Limited "^samsung,.*": description: Samsung Semiconductor "^samtec,.*":
Signature · 1 line
2.34.1
Re: [PATCH V4 1/8] dt-bindings: vendor-prefixes: document Saef Technology
Quoted 10 lines · Chris Morgan
From: Chris Morgan <[email protected]>
Document Saef Technology (https://www.saefdisplay.com/).
Signed-off-by Chris Morgan <[email protected]>Acked-by Conor Dooley <[email protected]>--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)
Applied, thanks!
PATCH v4 2/8 dt-bindings: display: panel: mipi-dbi-spi: add Saef SF-TC154B
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
The Saef SF-TC154B is a 1.54 inch 240x240 square panel with a MIPI DBI compatible interface. The panel is used on the Anbernic RG-Nano handheld gaming device.
The initialization of the panel requires a firmware binary which can be made with the mipi-dbi-cmd[1] tool. The command sequence needed can be found in both source[2] and binary form[3].
[1]: https://github.com/notro/panel-mipi-dbi
[2]: https://github.com/macromorgan/panel-mipi-dbi-firmware/raw/main/saef%2Csftc154b.txt
[3]: https://github.com/macromorgan/panel-mipi-dbi-firmware/raw/main/saef%2Csftc154b.bin
--- .../devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml +1 -0
@@ -66,6 +66,7 @@ properties: compatible: items: - enum: + - saef,sftc154b - sainsmart18 - shineworld,lh133k - const: panel-mipi-dbi-spi
Signature · 1 line
2.34.1
Re: [PATCH V4 2/8] dt-bindings: display: panel: mipi-dbi-spi: add Saef SF-TC154B
Quoted 14 lines · Chris Morgan
From: Chris Morgan <[email protected]>
The Saef SF-TC154B is a 1.54 inch 240x240 square panel with a MIPI DBI compatible interface. The panel is used on the Anbernic RG-Nano handheld gaming device.
The initialization of the panel requires a firmware binary which can be made with the mipi-dbi-cmd[1] tool. The command sequence needed can be found in both source[2] and binary form[3].
[1]: https://github.com/notro/panel-mipi-dbi
[2]: https://github.com/macromorgan/panel-mipi-dbi-firmware/raw/main/saef%2Csftc154b.txt
[3]: https://github.com/macromorgan/panel-mipi-dbi-firmware/raw/main/saef%2Csftc154b.bin
Quoted 7 lines
Signed-off-by Chris Morgan <[email protected]>Acked-by Conor Dooley <[email protected]>Acked-by Noralf Trønnes <[email protected]>--- .../devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml | 1 + 1 file changed, 1 insertion(+)
Applied, thanks!
PATCH v4 3/8 arm: dts: sun8i: V3s: Add pinctrl for pwm
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
Add pinctrl nodes for pwm0 and pwm1.
--- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +12 -0
@@ -414,6 +414,18 @@ mmc1_pins: mmc1-pins { bias-pull-up; }; + /omit-if-no-ref/ + pwm0_pin: pwm0-pin { + pins = "PB4"; + function = "pwm0"; + }; + + /omit-if-no-ref/ + pwm1_pin: pwm1-pin { + pins = "PB5"; + function = "pwm1"; + }; + spi0_pins: spi0-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0";
Signature · 1 line
2.34.1
Re: [PATCH V4 3/8] arm: dts: sun8i: V3s: Add pinctrl for pwm
On Mon, 28 Aug 2023 13:19:36 -0500
Chris Morgan <[email protected]> wrote:
Hi,
Quoted 5 lines
From: Chris Morgan <[email protected]>
Add pinctrl nodes for pwm0 and pwm1.
Signed-off-by Chris Morgan <[email protected]>
Thanks for the changes, looks good now:
Cheers,
Andre
Quoted 27 lines
--- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +12
-0@@ -414,6 +414,18 @@ mmc1_pins: mmc1-pins { bias-pull-up; }; + /omit-if-no-ref/ + pwm0_pin: pwm0-pin { + pins = "PB4"; + function = "pwm0"; + }; + + /omit-if-no-ref/ + pwm1_pin: pwm1-pin { + pins = "PB5"; + function = "pwm1"; + }; + spi0_pins: spi0-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0";
PATCH v4 4/8 dt-bindings: usb: Add V3s compatible string for EHCI
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
The Allwinner V3s uses a generic EHCI and OHCI for USB host communication and the MUSB controller for OTG mode. Add compatible strings for the EHCI node.
--- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/usb/generic-ehci.yaml +1 -0
@@ -38,6 +38,7 @@ properties: - allwinner,sun8i-a83t-ehci - allwinner,sun8i-h3-ehci - allwinner,sun8i-r40-ehci + - allwinner,sun8i-v3s-ehci - allwinner,sun9i-a80-ehci - allwinner,sun20i-d1-ehci - aspeed,ast2400-ehci
Signature · 1 line
2.34.1
Rob Herring
maintainerRe: [PATCH V4 4/8] dt-bindings: usb: Add V3s compatible string for EHCI
Quoted 11 lines · Chris Morgan
From: Chris Morgan <[email protected]>
The Allwinner V3s uses a generic EHCI and OHCI for USB host communication and the MUSB controller for OTG mode. Add compatible strings for the EHCI node.
Signed-off-by Chris Morgan <[email protected]>Acked-by Conor Dooley <[email protected]>--- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + 1 file changed, 1 insertion(+)
Normally, Greg would take this, but neither he nor linux-usb were Cc'ed. Please use get_maintainer.pl.
Rob
Re: [PATCH V4 4/8] dt-bindings: usb: Add V3s compatible string for EHCI
In reply to Chris MorganQuoted 6 lines · Chris Morgan
From: Chris Morgan <[email protected]>
The Allwinner V3s uses a generic EHCI and OHCI for USB host communication and the MUSB controller for OTG mode. Add compatible strings for the EHCI node.
Quoted 6 lines
Signed-off-by Chris Morgan <[email protected]>Acked-by Conor Dooley <[email protected]>--- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + 1 file changed, 1 insertion(+)
Applied, thanks!
Re: [PATCH V4 4/8] dt-bindings: usb: Add V3s compatible string for EHCI
In reply to Chris MorganQuoted 8 lines · On Mon, 28 Aug 2023 13:19:37 -0500 Chris Morgan <[email protected]> wrote:
From: Chris Morgan <[email protected]>
The Allwinner V3s uses a generic EHCI and OHCI for USB host communication and the MUSB controller for OTG mode. Add compatible strings for the EHCI node.
Signed-off-by Chris Morgan <[email protected]>Acked-by Conor Dooley <[email protected]>
That looks alright, but you can squash this and the next patch into one - but only in case you need to re-send anyway.
Cheers,
Andre
Quoted 16 lines
--- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/usb/generic-ehci.yaml +1
-0@@ -38,6 +38,7 @@ properties: - allwinner,sun8i-a83t-ehci - allwinner,sun8i-h3-ehci - allwinner,sun8i-r40-ehci + - allwinner,sun8i-v3s-ehci - allwinner,sun9i-a80-ehci - allwinner,sun20i-d1-ehci - aspeed,ast2400-ehci
PATCH v4 5/8 dt-bindings: usb: Add V3s compatible string for OHCI
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
The Allwinner V3s uses a generic EHCI and OHCI for USB host communication and the MUSB controller for OTG mode. Add compatible strings for the EHCI node.
--- Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/usb/generic-ohci.yaml +1 -0
@@ -25,6 +25,7 @@ properties: - allwinner,sun8i-a83t-ohci - allwinner,sun8i-h3-ohci - allwinner,sun8i-r40-ohci + - allwinner,sun8i-v3s-ohci - allwinner,sun9i-a80-ohci - allwinner,sun20i-d1-ohci - brcm,bcm3384-ohci
Signature · 1 line
2.34.1
Re: [PATCH V4 5/8] dt-bindings: usb: Add V3s compatible string for OHCI
Quoted 6 lines · Chris Morgan
From: Chris Morgan <[email protected]>
The Allwinner V3s uses a generic EHCI and OHCI for USB host communication and the MUSB controller for OTG mode. Add compatible strings for the EHCI node.
Quoted 6 lines
Signed-off-by Chris Morgan <[email protected]>Acked-by Conor Dooley <[email protected]>--- Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 + 1 file changed, 1 insertion(+)
Applied, thanks!
PATCH v4 6/8 ARM: dts: sun8i: v3s: add EHCI and OHCI to v3s dts
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
Add the EHCI and OHCI controller to the Allwinner v3s to support using USB in host mode.
--- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+)
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +23 -0
@@ -319,6 +319,29 @@ usbphy: phy@1c19400 { #phy-cells = <1>; }; + ehci: usb@1c1a000 { + compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci: usb@1c1a400 { + compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>;
Signature · 1 line
2.34.1
Re: [PATCH V4 6/8] ARM: dts: sun8i: v3s: add EHCI and OHCI to v3s dts
On Mon, 28 Aug 2023 13:19:39 -0500
Chris Morgan <[email protected]> wrote:
Hi,
Quoted 6 lines
From: Chris Morgan <[email protected]>
Add the EHCI and OHCI controller to the Allwinner v3s to support using USB in host mode.
Signed-off-by Chris Morgan <[email protected]>
Looks good now, and the PHY connection is correct, even though the current code is ... interesting in this regard. It looks like the problem is more with the sunxi MUSB glue driver, though. Anyway:
Addresses, IRQs, clocks and resets checked against the manual:
Cheers,
Andre
Quoted 38 lines
--- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+)arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +23
-0@@ -319,6 +319,29 @@ usbphy: phy@1c19400 { #phy-cells = <1>; }; + ehci: usb@1c1a000 { + compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci: usb@1c1a400 { + compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>;
PATCH v4 7/8 dt-bindings: arm: sunxi: add Anbernic RG-Nano
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a portable handheld console from Anbernic which uses the Allwinner V3s SoC.
--- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+)
Documentation/devicetree/bindings/arm/sunxi.yaml +5 -0
@@ -56,6 +56,11 @@ properties: - const: amarula,a64-relic - const: allwinner,sun50i-a64 + - description: Anbernic RG-Nano + items: + - const: anbernic,rg-nano + - const: allwinner,sun8i-v3s + - description: Auxtek T003 A10s HDMI TV Stick items: - const: allwinner,auxtek-t003
Signature · 1 line
2.34.1
PATCH v4 8/8 ARM: dts: sunxi: add support for Anbernic RG-Nano
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a small portable game device based on the Allwinner V3s SoC. It has GPIO buttons on the face and side for input, a single mono speaker, a 240x240 SPI controlled display, a USB-C OTG port, an SD card slot for booting, and 64MB of RAM included in the SoC.
Working/Tested:
- SDMMC
- UART (for debugging)
- Buttons
- Charging/battery/PMIC
- Speaker
- RTC
- USB Host and Gadget*
- Display (at 60hz)
*There is an issue with the usb_phy where it forces the device to host mode. Until the phy driver is fixed this can be bypassed by either removing the phy references from the ohci and ehci nodes or by setting the usbphy on the ohci and ehci nodes to 1 (which is incorrect).
--- arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 284 ++++++++++++++++++ 2 files changed, 285 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
arch/arm/boot/dts/allwinner/Makefile +1 -0
@@ -237,6 +237,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-anbernic-rg-nano.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtb
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +284 -0
284 lines not on this page · raw message
Signature · 1 line
2.34.1
Re: [PATCH V4 8/8] ARM: dts: sunxi: add support for Anbernic RG-Nano
Quoted 18 lines · CEST Chris Morgan
From: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a small portable game device based on the Allwinner V3s SoC. It has GPIO buttons on the face and side for input, a single mono speaker, a 240x240 SPI controlled display, a USB-C OTG port, an SD card slot for booting, and 64MB of RAM included in the SoC.
Working/Tested:
- SDMMC
- UART (for debugging)
- Buttons
- Charging/battery/PMIC
- Speaker
- RTC
- USB Host and Gadget*
- Display (at 60hz)
Quoted 4 lines
*There is an issue with the
usb_phywhere it forces the device to host mode. Until the phy driver is fixed this can be bypassed by either removing the phy references from the ohci and ehci nodes or by setting the usbphy on the ohci and ehci nodes to 1 (which is incorrect).
DT is HW description, so driver independent and above comment should be removed from commit message.
Otherwise:
Best regards,
Jernej
Quoted 51 lines
Signed-off-by Chris Morgan <[email protected]>--- arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 284 ++++++++++++++++++ 2 files changed, 285 insertions(+) create mode 100644
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts(quoted diff) +0
-0b/arch/arm/boot/dts/allwinner/Makefile index
589a1ce1120a..2be83a1edcbb100644arch/arm/boot/dts/allwinner/Makefile +1
-0@@ -237,6 +237,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-anbernic-rg-nano.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtb(quoted diff) +0
-0
b/arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dtsnew file mode 100644
index 000000000000..bcccb0d3f9cearch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +22
-0@@ -0,0 +1,284 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "sun8i-v3s.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Anbernic RG Nano"; + compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s"; + + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>; + default-brightness-level = <11>; + power-supply = <®_vcc5v0>; + pwms = <&pwm 0 40000 1>; + };
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 32
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + button-a { + gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-A"; + linux,code = <BTN_EAST>; + }; + + button-b { + gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-B"; + linux,code = <BTN_SOUTH>; + }; + + button-down { + gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-left { + gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-right { + gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-se { + gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-SELECT"; + linux,code = <BTN_SELECT>; + }; + + button-st { + gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-START"; + linux,code = <BTN_START>; + }; + + button-tl { + gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-L"; + linux,code = <BTN_TL>; + }; + + button-tr { + gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-R"; + linux,code = <BTN_TR>; + }; + + button-up { + gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-X"; + linux,code = <BTN_NORTH>; + }; + + button-y { + gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
Quoted 5 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +5
-0+ label = "BTN-Y"; + linux,code = <BTN_WEST>; + }; + }; +};
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ +&ccu { + clocks = <&osc24M>, <&osc32k>; +}; + +&codec { + allwinner,audio-routing = "Speaker", "HP", + "MIC1", "Mic", + "Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
/* PF6
Quoted 16 lines
*/ + status = "okay";
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +15
-0+}; + +&ehci { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>;
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */ + vcc-supply = <®_vcc3v3>; + }; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5
*/
Quoted 133 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +133
-0+ }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +#include "axp209.dtsi" + +&battery_power_supply { + status = "okay"; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pio { + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + spi0_no_miso_pins: spi0-no-miso-pins { + pins = "PC1", "PC2", "PC3"; + function = "spi0"; + }; +}; + +&pwm { + pinctrl-0 = <&pwm0_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */ +®_dcdc2 { + regulator-always-on; + regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1250000>; + regulator-name = "vdd-cpu"; +}; + +/* DCDC3 wired into every 3.3v input that isn't the RTC. */ +®_dcdc3 { + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +/* + * LDO1 wired into RTC, voltage is hard-wired at 3.3v and cannot be + * software modified. Note that setting voltage here to 3.3v for accuracy + * sake causes an issue with the driver that causes it to fail to probe + * because of a voltage constraint in the driver. + */ +®_ldo1 { + regulator-always-on; + regulator-name = "vcc-rtc"; +}; + +/* LDO2 wired into VCC-PLL and audio codec. */ +®_ldo2 { + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc-pll"; +}; + +/* LDO3, LDO4, and LDO5 unused. */ +®_ldo3 { + status = "disabled"; +}; + +®_ldo4 { + status = "disabled"; +}; + +/* External RTC used instead, internal RTC runs fast. */ +&rtc { + status = "disabled"; +}; + +&spi0 { + pinctrl-0 = <&spi0_no_miso_pins>; + pinctrl-names = "default"; + status = "okay"; + + display@0 { + compatible = "saef,sftc154b", "panel-mipi-dbi-spi"; + reg = <0>; + backlight = <&backlight>; + dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */ + reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + spi-max-frequency = <100000000>; + + height-mm = <39>; + width-mm = <39>; + + /* Set hb-porch to compensate for non-visible area */ + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <80>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg {
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /*
PG5 */
Quoted 2 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +2
-0+ status = "okay"; +};
Re: [PATCH V4 8/8] ARM: dts: sunxi: add support for Anbernic RG-Nano
Quoted 24 lines · Jernej Škrabec
Quoted 18 lines · CEST Chris Morgan
From: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a small portable game device based on the Allwinner V3s SoC. It has GPIO buttons on the face and side for input, a single mono speaker, a 240x240 SPI controlled display, a USB-C OTG port, an SD card slot for booting, and 64MB of RAM included in the SoC.
Working/Tested:
- SDMMC
- UART (for debugging)
- Buttons
- Charging/battery/PMIC
- Speaker
- RTC
- USB Host and Gadget*
- Display (at 60hz)Quoted 4 lines
*There is an issue with the
usb_phywhere it forces the device to host mode. Until the phy driver is fixed this can be bypassed by either removing the phy references from the ohci and ehci nodes or by setting the usbphy on the ohci and ehci nodes to 1 (which is incorrect).
Quoted 8 lines
DT is HW description, so driver independent and above comment should be removed from commit message.
Otherwise:
Acked-by Jernej Skrabec <[email protected]>Best regards,
Jernej
Should I resubmit with the text removed, or can it be edited before being sent upstream?
Thank you.
Quoted 333 lines
Quoted 52 lines
Signed-off-by Chris Morgan <[email protected]>--- arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 284 ++++++++++++++++++ 2 files changed, 285 insertions(+) create mode 100644
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts(quoted diff) +0
-0b/arch/arm/boot/dts/allwinner/Makefile index
589a1ce1120a..2be83a1edcbb100644arch/arm/boot/dts/allwinner/Makefile +1
-0@@ -237,6 +237,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-anbernic-rg-nano.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtb(quoted diff) +0
-0
b/arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dtsnew file mode 100644
index 000000000000..bcccb0d3f9cearch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +22
-0@@ -0,0 +1,284 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "sun8i-v3s.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Anbernic RG Nano"; + compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s"; + + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>; + default-brightness-level = <11>; + power-supply = <®_vcc5v0>; + pwms = <&pwm 0 40000 1>; + };arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 32
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + button-a { + gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-A"; + linux,code = <BTN_EAST>; + }; + + button-b { + gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-B"; + linux,code = <BTN_SOUTH>; + }; + + button-down { + gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-left { + gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-right { + gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-se { + gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-SELECT"; + linux,code = <BTN_SELECT>; + }; + + button-st { + gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-START"; + linux,code = <BTN_START>; + }; + + button-tl { + gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-L"; + linux,code = <BTN_TL>; + }; + + button-tr { + gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-R"; + linux,code = <BTN_TR>; + }; + + button-up { + gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 6 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-X"; + linux,code = <BTN_NORTH>; + }; + + button-y { + gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;Quoted 5 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +5
-0+ label = "BTN-Y"; + linux,code = <BTN_WEST>; + }; + }; +};arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ +&ccu { + clocks = <&osc24M>, <&osc32k>; +}; + +&codec { + allwinner,audio-routing = "Speaker", "HP", + "MIC1", "Mic", + "Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;/* PF6
Quoted 16 lines
*/ + status = "okay";
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +15
-0+}; + +&ehci { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */ + vcc-supply = <®_vcc3v3>; + }; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5*/
Quoted 133 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +133
-0+ }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +#include "axp209.dtsi" + +&battery_power_supply { + status = "okay"; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pio { + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + spi0_no_miso_pins: spi0-no-miso-pins { + pins = "PC1", "PC2", "PC3"; + function = "spi0"; + }; +}; + +&pwm { + pinctrl-0 = <&pwm0_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */ +®_dcdc2 { + regulator-always-on; + regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1250000>; + regulator-name = "vdd-cpu"; +}; + +/* DCDC3 wired into every 3.3v input that isn't the RTC. */ +®_dcdc3 { + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +/* + * LDO1 wired into RTC, voltage is hard-wired at 3.3v and cannot be + * software modified. Note that setting voltage here to 3.3v for accuracy + * sake causes an issue with the driver that causes it to fail to probe + * because of a voltage constraint in the driver. + */ +®_ldo1 { + regulator-always-on; + regulator-name = "vcc-rtc"; +}; + +/* LDO2 wired into VCC-PLL and audio codec. */ +®_ldo2 { + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc-pll"; +}; + +/* LDO3, LDO4, and LDO5 unused. */ +®_ldo3 { + status = "disabled"; +}; + +®_ldo4 { + status = "disabled"; +}; + +/* External RTC used instead, internal RTC runs fast. */ +&rtc { + status = "disabled"; +}; + +&spi0 { + pinctrl-0 = <&spi0_no_miso_pins>; + pinctrl-names = "default"; + status = "okay"; + + display@0 { + compatible = "saef,sftc154b", "panel-mipi-dbi-spi"; + reg = <0>; + backlight = <&backlight>; + dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */ + reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + spi-max-frequency = <100000000>; + + height-mm = <39>; + width-mm = <39>; + + /* Set hb-porch to compensate for non-visible area */ + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <80>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg {arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /*PG5 */
Quoted 2 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +2
-0+ status = "okay"; +};
Jernej Škrabec
maintainerRe: [PATCH V4 8/8] ARM: dts: sunxi: add support for Anbernic RG-Nano
Quoted 28 lines · CEST Chris Morgan
Quoted 27 lines · Jernej Škrabec
Quoted 18 lines · CEST Chris Morgan
From: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a small portable game device based on the Allwinner V3s SoC. It has GPIO buttons on the face and side for input, a single mono speaker, a 240x240 SPI controlled display, a USB-C OTG port, an SD card slot for booting, and 64MB of RAM included in the SoC.
Working/Tested:
- SDMMC
- UART (for debugging)
- Buttons
- Charging/battery/PMIC
- Speaker
- RTC
- USB Host and Gadget*
- Display (at 60hz)Quoted 4 lines
*There is an issue with the
usb_phywhere it forces the device to host mode. Until the phy driver is fixed this can be bypassed by either removing the phy references from the ohci and ehci nodes or by setting the usbphy on the ohci and ehci nodes to 1 (which is incorrect).DT is HW description, so driver independent and above comment should be removed from commit message.
Quoted 8 lines
Quoted 5 lines
Otherwise:
Acked-by Jernej Skrabec <[email protected]>Best regards,
JernejShould I resubmit with the text removed, or can it be edited before being sent upstream?
It can be edited if nothing else pops up. In any case, it will be applied after 6.6-rc1 is released.
Best regards,
Jernej
Quoted 62 lines
Thank you.
Quoted 59 lines
Quoted 59 lines
Signed-off-by Chris Morgan <[email protected]>---
arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 284 ++++++++++++++++++ 2 files changed, 285 insertions(+) create mode 100644
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts(quoted diff) +0
-0b/arch/arm/boot/dts/allwinner/Makefile index
589a1ce1120a..2be83a1edcbb100644arch/arm/boot/dts/allwinner/Makefile +1
-0@@ -237,6 +237,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-anbernic-rg-nano.dtb \arch/arm/boot/dts/allwinner/Makefile +0
-0sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtb(quoted diff) +0
-0
b/arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dtsnew file mode
100644
index 000000000000..bcccb0d3f9cearch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +24
-0@@ -0,0 +1,284 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "sun8i-v3s.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Anbernic RG Nano"; + compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s"; + + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>; + default-brightness-level = <11>; + power-supply = <®_vcc5v0>; + pwms = <&pwm 0 40000 1>; + }; + + chosen {
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +8
-0+ stdout-path = "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + button-a { + gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW
|
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GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-A"; + linux,code = <BTN_EAST>; + }; + + button-b { + gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW
|
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GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-B"; + linux,code = <BTN_SOUTH>; + }; + + button-down { + gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-left { + gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-right { + gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-se { + gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-SELECT"; + linux,code = <BTN_SELECT>; + }; + + button-st { + gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-START"; + linux,code = <BTN_START>; + }; + + button-tl { + gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-L"; + linux,code = <BTN_TL>; + }; + + button-tr { + gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW
|
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GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-R"; + linux,code = <BTN_TR>; + }; + + button-up { + gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW
|
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GPIO_PULL_UP)>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +6
-0+ label = "BTN-X"; + linux,code = <BTN_NORTH>; + }; + + button-y { + gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW
|
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GPIO_PULL_UP)>;Quoted 5 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +5
-0+ label = "BTN-Y"; + linux,code = <BTN_WEST>; + }; + }; +};arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ +&ccu { + clocks = <&osc24M>, <&osc32k>; +}; + +&codec { + allwinner,audio-routing = "Speaker", "HP", + "MIC1", "Mic", + "Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;/* PF6
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*/ + status = "okay";
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +15
-0+}; + +&ehci { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>;arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */ + vcc-supply = <®_vcc3v3>; + }; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5*/
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +65
-0+ }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +#include "axp209.dtsi" + +&battery_power_supply { + status = "okay"; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pio { + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + spi0_no_miso_pins: spi0-no-miso-pins { + pins = "PC1", "PC2", "PC3"; + function = "spi0"; + }; +}; + +&pwm { + pinctrl-0 = <&pwm0_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */ +®_dcdc2 { + regulator-always-on; + regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1250000>; + regulator-name = "vdd-cpu"; +}; + +/* DCDC3 wired into every 3.3v input that isn't the RTC. */ +®_dcdc3 { + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +/* + * LDO1 wired into RTC, voltage is hard-wired at 3.3v and cannot be + * software modified. Note that setting voltage here to 3.3v foraccuracy
+ * sake causes an issue with the driver that causes it to fail to probe
+ * because of a voltage constraint in the driver.
+ */
+®_ldo1 {arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +66
-0+ regulator-always-on; + regulator-name = "vcc-rtc"; +}; + +/* LDO2 wired into VCC-PLL and audio codec. */ +®_ldo2 { + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc-pll"; +}; + +/* LDO3, LDO4, and LDO5 unused. */ +®_ldo3 { + status = "disabled"; +}; + +®_ldo4 { + status = "disabled"; +}; + +/* External RTC used instead, internal RTC runs fast. */ +&rtc { + status = "disabled"; +}; + +&spi0 { + pinctrl-0 = <&spi0_no_miso_pins>; + pinctrl-names = "default"; + status = "okay"; + + display@0 { + compatible = "saef,sftc154b", "panel-mipi-dbi-spi"; + reg = <0>; + backlight = <&backlight>; + dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */ + reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + spi-max-frequency = <100000000>; + + height-mm = <39>; + width-mm = <39>; + + /* Set hb-porch to compensate for non-visible area */ + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <80>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay";
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +8
-0+}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /
*
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PG5 */
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +2
-0+ status = "okay"; +};
Samuel Holland
maintainerRe: [PATCH V4 8/8] ARM: dts: sunxi: add support for Anbernic RG-Nano
In reply to Chris MorganQuoted 145 lines · Chris Morgan
From: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a small portable game device based on the Allwinner V3s SoC. It has GPIO buttons on the face and side for input, a single mono speaker, a 240x240 SPI controlled display, a USB-C OTG port, an SD card slot for booting, and 64MB of RAM included in the SoC.
Working/Tested:
- SDMMC
- UART (for debugging)
- Buttons
- Charging/battery/PMIC
- Speaker
- RTC
- USB Host and Gadget*
- Display (at 60hz)*There is an issue with the
usb_phywhere it forces the device to host mode. Until the phy driver is fixed this can be bypassed by either removing the phy references from the ohci and ehci nodes or by setting the usbphy on the ohci and ehci nodes to 1 (which is incorrect).Signed-off-by Chris Morgan <[email protected]>--- arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 284 ++++++++++++++++++ 2 files changed, 285 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dtsarch/arm/boot/dts/allwinner/Makefile +1
-0@@ -237,6 +237,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-anbernic-rg-nano.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtbarch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +97
-0@@ -0,0 +1,284 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "sun8i-v3s.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Anbernic RG Nano"; + compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s"; + + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>; + default-brightness-level = <11>; + power-supply = <®_vcc5v0>; + pwms = <&pwm 0 40000 1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + button-a { + gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-A"; + linux,code = <BTN_EAST>; + }; + + button-b { + gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-B"; + linux,code = <BTN_SOUTH>; + }; + + button-down { + gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-left { + gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-right { + gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-se { + gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-SELECT"; + linux,code = <BTN_SELECT>; + }; + + button-st { + gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-START"; + linux,code = <BTN_START>; + }; + + button-tl { + gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-L"; + linux,code = <BTN_TL>; + }; + + button-tr { + gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-R"; + linux,code = <BTN_TR>; + }; + + button-up { + gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-X"; + linux,code = <BTN_NORTH>; + }; + + button-y {
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 107
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-Y"; + linux,code = <BTN_WEST>; + }; + }; +}; + +&ccu { + clocks = <&osc24M>, <&osc32k>; +};
This is not accurate. The CCU's 32 kHz clock comes from the internal RTC, whether you lie to the kernel about it or not. :)
If the external 32 kHz crystal represented by &osc32k really exists, then I would expect the internal RTC to be accurate. At least the Linux driver tries to switch to the external crystal.
If it's not using the external crystal... well, the V3s manual says "Note: Internal 32kHz is divided from OSC24MHz". And there's no integer factor of 24 MHz that gets you 32768 Hz, so that would explain the poor accuracy. Even in that case, if you can't use the RTC as an RTC, it should still be enabled in the DT, so the rest of the system can know the actual OSC32K/LOSC clock frequency. Userspace should be able to deal with the system having more than one RTC.
Quoted 51 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +51
-0+ +&codec { + allwinner,audio-routing = "Speaker", "HP", + "MIC1", "Mic", + "Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PF6 */ + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */ + vcc-supply = <®_vcc3v3>; + }; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5 */ + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +#include "axp209.dtsi" + +&battery_power_supply { + status = "okay"; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>;
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 168
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arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ vqmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pio { + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
The same concern applies here.
Regards,
Samuel
Quoted 116 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +116
-0+ vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + spi0_no_miso_pins: spi0-no-miso-pins { + pins = "PC1", "PC2", "PC3"; + function = "spi0"; + }; +}; + +&pwm { + pinctrl-0 = <&pwm0_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */ +®_dcdc2 { + regulator-always-on; + regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1250000>; + regulator-name = "vdd-cpu"; +}; + +/* DCDC3 wired into every 3.3v input that isn't the RTC. */ +®_dcdc3 { + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +/* + * LDO1 wired into RTC, voltage is hard-wired at 3.3v and cannot be + * software modified. Note that setting voltage here to 3.3v for accuracy + * sake causes an issue with the driver that causes it to fail to probe + * because of a voltage constraint in the driver. + */ +®_ldo1 { + regulator-always-on; + regulator-name = "vcc-rtc"; +}; + +/* LDO2 wired into VCC-PLL and audio codec. */ +®_ldo2 { + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc-pll"; +}; + +/* LDO3, LDO4, and LDO5 unused. */ +®_ldo3 { + status = "disabled"; +}; + +®_ldo4 { + status = "disabled"; +}; + +/* External RTC used instead, internal RTC runs fast. */ +&rtc { + status = "disabled"; +}; + +&spi0 { + pinctrl-0 = <&spi0_no_miso_pins>; + pinctrl-names = "default"; + status = "okay"; + + display@0 { + compatible = "saef,sftc154b", "panel-mipi-dbi-spi"; + reg = <0>; + backlight = <&backlight>; + dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */ + reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + spi-max-frequency = <100000000>; + + height-mm = <39>; + width-mm = <39>; + + /* Set hb-porch to compensate for non-visible area */ + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <80>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG5 */ + status = "okay"; +};
Re: [PATCH V4 8/8] ARM: dts: sunxi: add support for Anbernic RG-Nano
In reply to Chris MorganOn Mon, 28 Aug 2023 13:19:41 -0500
Chris Morgan <[email protected]> wrote:
Hi Chris,
thanks for the changes. As Samuel already pointed out, there is now a problem with the RTC...
Quoted 144 lines
From: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a small portable game device based on the Allwinner V3s SoC. It has GPIO buttons on the face and side for input, a single mono speaker, a 240x240 SPI controlled display, a USB-C OTG port, an SD card slot for booting, and 64MB of RAM included in the SoC.
Working/Tested:
- SDMMC
- UART (for debugging)
- Buttons
- Charging/battery/PMIC
- Speaker
- RTC
- USB Host and Gadget*
- Display (at 60hz)*There is an issue with the
usb_phywhere it forces the device to host mode. Until the phy driver is fixed this can be bypassed by either removing the phy references from the ohci and ehci nodes or by setting the usbphy on the ohci and ehci nodes to 1 (which is incorrect).Signed-off-by Chris Morgan <[email protected]>--- arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 284 ++++++++++++++++++ 2 files changed, 285 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dtsarch/arm/boot/dts/allwinner/Makefile +1
-0@@ -237,6 +237,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-anbernic-rg-nano.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtbarch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +96
-0@@ -0,0 +1,284 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "sun8i-v3s.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Anbernic RG Nano"; + compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s"; + + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>; + default-brightness-level = <11>; + power-supply = <®_vcc5v0>; + pwms = <&pwm 0 40000 1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + button-a { + gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-A"; + linux,code = <BTN_EAST>; + }; + + button-b { + gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-B"; + linux,code = <BTN_SOUTH>; + }; + + button-down { + gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-left { + gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-right { + gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-se { + gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-SELECT"; + linux,code = <BTN_SELECT>; + }; + + button-st { + gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-START"; + linux,code = <BTN_START>; + }; + + button-tl { + gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-L"; + linux,code = <BTN_TL>; + }; + + button-tr { + gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-R"; + linux,code = <BTN_TR>; + }; + + button-up { + gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-X"; + linux,code = <BTN_NORTH>; + }; +
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 106
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ button-y { + gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-Y"; + linux,code = <BTN_WEST>; + }; + }; +}; + +&ccu { + clocks = <&osc24M>, <&osc32k>;
Samuel already pointed that out: please don't change that.
Quoted 116 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +116
-0+}; + +&codec { + allwinner,audio-routing = "Speaker", "HP", + "MIC1", "Mic", + "Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PF6 */ + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */ + vcc-supply = <®_vcc3v3>; + }; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5 */ + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +#include "axp209.dtsi" + +&battery_power_supply { + status = "okay"; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pio { + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + spi0_no_miso_pins: spi0-no-miso-pins { + pins = "PC1", "PC2", "PC3"; + function = "spi0"; + }; +}; + +&pwm { + pinctrl-0 = <&pwm0_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */ +®_dcdc2 { + regulator-always-on; + regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1250000>; + regulator-name = "vdd-cpu"; +}; + +/* DCDC3 wired into every 3.3v input that isn't the RTC. */ +®_dcdc3 { + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +/* + * LDO1 wired into RTC, voltage is hard-wired at 3.3v and cannot be + * software modified. Note that setting voltage here to 3.3v for accuracy + * sake causes an issue with the driver that causes it to fail to probe + * because of a voltage constraint in the driver. + */ +®_ldo1 { + regulator-always-on; + regulator-name = "vcc-rtc"; +}; + +/* LDO2 wired into VCC-PLL and audio codec. */ +®_ldo2 { + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc-pll"; +}; + +/* LDO3, LDO4, and LDO5 unused. */ +®_ldo3 {
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 232
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ status = "disabled"; +}; + +®_ldo4 { + status = "disabled"; +}; + +/* External RTC used instead, internal RTC runs fast. */ +&rtc { + status = "disabled";
So as Samuel mentioned, I don't think you should disable the RTC, even if you have another RTC which provides more accurate time reading. On most Allwinner chips the RTC provides more than just the actual timekeeping functionality, as it also provides various derived clocks.
So when you say the "internal RTC runs fast", that sounds like the board does not actually connect an external 32K crystal to the X32KIN/X32KOUT pins?
So what happens if you remove the clocks property from the RTC node? If I read the code correctly, that should make the driver aware of the lack of a crystal, which might improve things?
The manual seems to somewhat suggest that an external oscillator is mandatory - and we modelled the sun8i-v3s.dtsi base after that. Though I believe the RTC supports using the internal RC oscillator, and omitting the "clocks" property should make the driver switch the RTC over.
This is at least my naive and quick interpretation of the code. I am not an Allwinner RTC expert though, so happy to hear Samuel's opinion.
Regarding multiple RTCs: I didn't find anything which assigns a priority level to multiple RTCs in the system. What you can do on the userland side is to have a udev rule that links the PCF device to /dev/rtc, so that most tools would use that as a time source.
Cheers,
Andre
Quoted 52 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +52
-0+}; + +&spi0 { + pinctrl-0 = <&spi0_no_miso_pins>; + pinctrl-names = "default"; + status = "okay"; + + display@0 { + compatible = "saef,sftc154b", "panel-mipi-dbi-spi"; + reg = <0>; + backlight = <&backlight>; + dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */ + reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + spi-max-frequency = <100000000>; + + height-mm = <39>; + width-mm = <39>; + + /* Set hb-porch to compensate for non-visible area */ + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <80>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG5 */ + status = "okay"; +};
Re: [PATCH V4 8/8] ARM: dts: sunxi: add support for Anbernic RG-Nano
Quoted 310 lines · Andre Przywara
On Mon, 28 Aug 2023 13:19:41 -0500
Chris Morgan <[email protected]> wrote:Hi Chris,
thanks for the changes. As Samuel already pointed out, there is now a problem with the RTC...
Quoted 144 lines
From: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a small portable game device based on the Allwinner V3s SoC. It has GPIO buttons on the face and side for input, a single mono speaker, a 240x240 SPI controlled display, a USB-C OTG port, an SD card slot for booting, and 64MB of RAM included in the SoC.
Working/Tested:
- SDMMC
- UART (for debugging)
- Buttons
- Charging/battery/PMIC
- Speaker
- RTC
- USB Host and Gadget*
- Display (at 60hz)*There is an issue with the
usb_phywhere it forces the device to host mode. Until the phy driver is fixed this can be bypassed by either removing the phy references from the ohci and ehci nodes or by setting the usbphy on the ohci and ehci nodes to 1 (which is incorrect).Signed-off-by Chris Morgan <[email protected]>--- arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 284 ++++++++++++++++++ 2 files changed, 285 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dtsarch/arm/boot/dts/allwinner/Makefile +1
-0@@ -237,6 +237,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-anbernic-rg-nano.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtbarch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +96
-0@@ -0,0 +1,284 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "sun8i-v3s.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Anbernic RG Nano"; + compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s"; + + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>; + default-brightness-level = <11>; + power-supply = <®_vcc5v0>; + pwms = <&pwm 0 40000 1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + button-a { + gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-A"; + linux,code = <BTN_EAST>; + }; + + button-b { + gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-B"; + linux,code = <BTN_SOUTH>; + }; + + button-down { + gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-left { + gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-right { + gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-se { + gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-SELECT"; + linux,code = <BTN_SELECT>; + }; + + button-st { + gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-START"; + linux,code = <BTN_START>; + }; + + button-tl { + gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-L"; + linux,code = <BTN_TL>; + }; + + button-tr { + gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-R"; + linux,code = <BTN_TR>; + }; + + button-up { + gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-X"; + linux,code = <BTN_NORTH>; + }; +arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 106
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ button-y { + gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-Y"; + linux,code = <BTN_WEST>; + }; + }; +}; + +&ccu { + clocks = <&osc24M>, <&osc32k>;Samuel already pointed that out: please don't change that.
Quoted 116 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +116
-0+}; + +&codec { + allwinner,audio-routing = "Speaker", "HP", + "MIC1", "Mic", + "Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PF6 */ + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */ + vcc-supply = <®_vcc3v3>; + }; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5 */ + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +#include "axp209.dtsi" + +&battery_power_supply { + status = "okay"; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pio { + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + spi0_no_miso_pins: spi0-no-miso-pins { + pins = "PC1", "PC2", "PC3"; + function = "spi0"; + }; +}; + +&pwm { + pinctrl-0 = <&pwm0_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */ +®_dcdc2 { + regulator-always-on; + regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1250000>; + regulator-name = "vdd-cpu"; +}; + +/* DCDC3 wired into every 3.3v input that isn't the RTC. */ +®_dcdc3 { + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +/* + * LDO1 wired into RTC, voltage is hard-wired at 3.3v and cannot be + * software modified. Note that setting voltage here to 3.3v for accuracy + * sake causes an issue with the driver that causes it to fail to probe + * because of a voltage constraint in the driver. + */ +®_ldo1 { + regulator-always-on; + regulator-name = "vcc-rtc"; +}; + +/* LDO2 wired into VCC-PLL and audio codec. */ +®_ldo2 { + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc-pll"; +}; + +/* LDO3, LDO4, and LDO5 unused. */ +®_ldo3 {arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts line 232
Quoted 10 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +10
-0+ status = "disabled"; +}; + +®_ldo4 { + status = "disabled"; +}; + +/* External RTC used instead, internal RTC runs fast. */ +&rtc { + status = "disabled";So as Samuel mentioned, I don't think you should disable the RTC, even if you have another RTC which provides more accurate time reading. On most Allwinner chips the RTC provides more than just the actual timekeeping functionality, as it also provides various derived clocks.
So when you say the "internal RTC runs fast", that sounds like the board does not actually connect an external 32K crystal to the X32KIN/X32KOUT pins?
So what happens if you remove the clocks property from the RTC node? If I read the code correctly, that should make the driver aware of the lack of a crystal, which might improve things?
The manual seems to somewhat suggest that an external oscillator is mandatory - and we modelled thesun8i-v3s.dtsibase after that. Though I believe the RTC supports using the internal RC oscillator, and omitting the "clocks" property should make the driver switch the RTC over.
Quoted 7 lines
This is at least my naive and quick interpretation of the code. I am not an Allwinner RTC expert though, so happy to hear Samuel's opinion.
Regarding multiple RTCs: I didn't find anything which assigns a priority level to multiple RTCs in the system. What you can do on the userland side is to have a udev rule that links the PCF device to
/dev/rtc, so that most tools would use that as a time source.
You can add DT aliases to override the numbering, thus making an external one rtc0 and the internal one rtc1. See arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts for such an example.
ChenYu
Quoted 56 lines
Cheers,
AndreQuoted 52 lines
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +52
-0+}; + +&spi0 { + pinctrl-0 = <&spi0_no_miso_pins>; + pinctrl-names = "default"; + status = "okay"; + + display@0 { + compatible = "saef,sftc154b", "panel-mipi-dbi-spi"; + reg = <0>; + backlight = <&backlight>; + dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */ + reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + spi-max-frequency = <100000000>; + + height-mm = <39>; + width-mm = <39>; + + /* Set hb-porch to compensate for non-visible area */ + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <80>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG5 */ + status = "okay"; +};
Re: [PATCH V4 8/8] ARM: dts: sunxi: add support for Anbernic RG-Nano
On Mon, 11 Sep 2023 21:35:19 +0800
Chen-Yu Tsai <[email protected]> wrote:
Hi Chen-Yu,
[...]
Quoted 8 lines
Quoted 4 lines
Regarding multiple RTCs: I didn't find anything which assigns a priority level to multiple RTCs in the system. What you can do on the userland side is to have a udev rule that links the PCF device to
/dev/rtc, so that most tools would use that as a time source.You can add DT aliases to override the numbering, thus making an external one rtc0 and the internal one rtc1. See
arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dtsfor such an example.
Ah, excellent, I somehow missed this. That should indeed solve that problem.
Thanks for the heads up!
Andre