amd-pstate preferred core

amd-pstate driver also uses SCHED_MC_PRIO, so decouple the requirement of CPU_SUP_INTEL from the dependencies to allow compilation in kernels without Intel CPU support.

Signed-off-by Meng Li <[email protected]>

---
  arch/x86/Kconfig | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

arch/x86/Kconfig +3 -2

index 8d9e4b362572..887421b5ee8f 100644
@@ -1052,8 +1052,9 @@ config SCHED_MC
 
  config SCHED_MC_PRIO
  	bool "CPU core priorities scheduler support"
-	depends on SCHED_MC && CPU_SUP_INTEL
-	select X86_INTEL_PSTATE
+	depends on SCHED_MC
+	select X86_INTEL_PSTATE if CPU_SUP_INTEL
+	select X86_AMD_PSTATE if CPU_SUP_AMD
  	select CPU_FREQ
  	default y
  	help

amd-pstate driver also uses SCHED_MC_PRIO, so decouple the requirement of CPU_SUP_INTEL from the dependencies to allow compilation in kernels without Intel CPU support.

Signed-off-by Meng Li <[email protected]>

---
 arch/x86/Kconfig | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

arch/x86/Kconfig +3 -2

index 8d9e4b362572..887421b5ee8f 100644
@@ -1052,8 +1052,9 @@ config SCHED_MC
 
 config SCHED_MC_PRIO
 	bool "CPU core priorities scheduler support"
-	depends on SCHED_MC && CPU_SUP_INTEL
-	select X86_INTEL_PSTATE
+	depends on SCHED_MC
+	select X86_INTEL_PSTATE if CPU_SUP_INTEL
+	select X86_AMD_PSTATE if CPU_SUP_AMD
 	select CPU_FREQ
 	default y
 	help

Signature · 1 line

2.34.1

Add support for getting the highest performance to the generic CPPC driver. This enables downstream drivers such as amd-pstate to discover and use these values.

Please refer to the ACPI_Spec for details on continuous performance control of CPPC.

Signed-off-by Meng Li <[email protected]>

Reviewed-by Mario Limonciello <[email protected]>

Reviewed-by Wyes Karny <[email protected]>

Link https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html?highlight=cppc#cpc-continuous-performance-control

---
 drivers/acpi/cppc_acpi.c | 13 +++++++++++++
 include/acpi/cppc_acpi.h |  5 +++++
 2 files changed, 18 insertions(+)

drivers/acpi/cppc_acpi.c +13 -0

index 7ff269a78c20..ad388a0e8484 100644
@@ -1154,6 +1154,19 @@ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
 	return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
 }
 
+/**
+ * cppc_get_highest_perf - Get the highest performance register value.
+ * @cpunum: CPU from which to get highest performance.
+ * @highest_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
+{
+	return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf);
+}
+EXPORT_SYMBOL_GPL(cppc_get_highest_perf);
+
 /**
  * cppc_get_epp_perf - Get the epp register value.
  * @cpunum: CPU from which to get epp preference value.

include/acpi/cppc_acpi.h +5 -0

index 6126c977ece0..c0b69ffe7bdb 100644
@@ -139,6 +139,7 @@ struct cppc_cpudata {
 #ifdef CONFIG_ACPI_CPPC_LIB
 extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf);
 extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf);
+extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf);
 extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs);
 extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
 extern int cppc_set_enable(int cpu, bool enable);

@@ -165,6 +166,10 @@ static inline int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
 {
 	return -ENOTSUPP;
 }
+static inline int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
+{
+	return -ENOTSUPP;
+}
 static inline int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
 {
 	return -ENOTSUPP;

Signature · 1 line

2.34.1

amd-pstate driver utilizes the functions and data structures provided by the ITMT architecture to enable the scheduler to favor scheduling on cores which can be get a higher frequency with lower voltage. We call it amd-pstate preferrred core.

Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. amd-pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority.

The initial core rankings are set up by amd-pstate when the system boots.

Add device attribute for hardware preferred core. It will check if the processor and power firmware support preferred core feature.

Add device attribute for preferred core. Only when hardware supports preferred core and user set enabled in early parameter, it can be set to enabled.

Add one new early parameter disable to allow user to disable the preferred core.

Signed-off-by Perry Yuan <[email protected]>

Co-developed-by Perry Yuan <[email protected]>

Signed-off-by Meng Li <[email protected]>

Co-developed-by Meng Li <[email protected]>

Reviewed-by Mario Limonciello <[email protected]>

---
  drivers/cpufreq/amd-pstate.c | 131 ++++++++++++++++++++++++++++++-----
  1 file changed, 115 insertions(+), 16 deletions(-)

drivers/cpufreq/amd-pstate.c +115 -16

index 9a1e194d5cf8..454eb6e789e7 100644
@@ -37,6 +37,7 @@
  #include <linux/uaccess.h>
  #include <linux/static_call.h>
  #include <linux/amd-pstate.h>
+#include <linux/topology.h>
 
  #include <acpi/processor.h>
  #include <acpi/cppc_acpi.h>

@@ -49,6 +50,8 @@
 
  #define AMD_PSTATE_TRANSITION_LATENCY	20000
  #define AMD_PSTATE_TRANSITION_DELAY	1000
+#define AMD_PSTATE_PREFCORE_THRESHOLD	166
+#define AMD_PSTATE_MAX_CPPC_PERF	255
 
  /*
   * TODO: We need more time to fine tune processors with shared memory solution

@@ -65,6 +68,12 @@ static struct cpufreq_driver amd_pstate_epp_driver;
  static int cppc_state = AMD_PSTATE_UNDEFINED;
  static bool cppc_enabled;
 
+/*HW preferred Core featue is supported*/
+static bool hw_prefcore = true;
+
+/*Preferred Core featue is supported*/
+static bool prefcore = true;
+
  /*
   * AMD Energy Preference Performance (EPP)
   * The EPP is used in the CCLK DPM controller to drive

@@ -290,23 +299,21 @@ static inline int amd_pstate_enable(bool enable)
  static int pstate_init_perf(struct amd_cpudata *cpudata)
  {
  	u64 cap1;
-	u32 highest_perf;
 
  	int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
  				     &cap1);
  	if (ret)
  		return ret;
 
-	/*
-	 * TODO: Introduce AMD specific power feature.
-	 *
-	 * CPPC entry doesn't indicate the highest performance in some ASICs.
+	/* For platforms that do not support the preferred core feature, the
+	 * highest_pef may be configured with 166 or 255, to avoid max frequency
+	 * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as
+	 * the default max perf.
  	 */
-	highest_perf = amd_get_highest_perf();
-	if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1))
-		highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
-
-	WRITE_ONCE(cpudata->highest_perf, highest_perf);
+	if (prefcore)
+		WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD);
+	else
+		WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
 
  	WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
  	WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));

@@ -318,17 +325,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)
  static int cppc_init_perf(struct amd_cpudata *cpudata)
  {
  	struct cppc_perf_caps cppc_perf;
-	u32 highest_perf;
 
  	int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
  	if (ret)
  		return ret;
 
-	highest_perf = amd_get_highest_perf();
-	if (highest_perf > cppc_perf.highest_perf)
-		highest_perf = cppc_perf.highest_perf;
-
-	WRITE_ONCE(cpudata->highest_perf, highest_perf);
+	if (prefcore)
+		WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD);
+	else
+		WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf);
 
  	WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
  	WRITE_ONCE(cpudata->lowest_nonlinear_perf,

@@ -676,6 +681,73 @@ static void amd_perf_ctl_reset(unsigned int cpu)
  	wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0);
  }
 
+/*
+ * Set amd-pstate preferred core enable can't be done directly from cpufreq callbacks
+ * due to locking, so queue the work for later.
+ */
+static void amd_pstste_sched_prefcore_workfn(struct work_struct *work)
+{
+	sched_set_itmt_support();
+}
+static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn);
+
+/*
+ * Get the highest performance register value.
+ * @cpu: CPU from which to get highest performance.
+ * @highest_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf)
+{
+	int ret;
+
+	if (boot_cpu_has(X86_FEATURE_CPPC)) {
+		u64 cap1;
+
+		ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1);
+		if (ret)
+			return ret;
+		WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
+	} else {
+		ret = cppc_get_highest_perf(cpu, highest_perf);
+	}
+
+	return (ret);
+}
+
+static void amd_pstate_init_prefcore(void)
+{
+	int cpu, ret;
+	u64 highest_perf;
+
+	if (!prefcore)
+		return;
+
+	for_each_online_cpu(cpu) {
+		ret = amd_pstate_get_highest_perf(cpu, &highest_perf);
+		if (ret)
+			break;
+
+		sched_set_itmt_core_prio(highest_perf, cpu);
+
+		/* check if CPPC preferred core feature is enabled*/
+		if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) {
+			hw_prefcore = false;
+			prefcore = false;
+			return;
+		}
+	}
+
+	/*
+	 * This code can be run during CPU online under the
+	 * CPU hotplug locks, so sched_set_amd_prefcore_support()
+	 * cannot be called from here.  Queue up a work item
+	 * to invoke it.
+	 */
+	schedule_work(&sched_prefcore_work);
+}
+
  static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
  {
  	int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;

@@ -1037,6 +1109,18 @@ static ssize_t status_store(struct device *a, struct device_attribute *b,
  	return ret < 0 ? ret : count;
  }
 
+static ssize_t hw_prefcore_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "%s\n", hw_prefcore ? "supported" : "unsupported");
+}
+
+static ssize_t prefcore_show(struct device *dev,
+			     struct device_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "%s\n", prefcore ? "enabled" : "disabled");
+}
+
  cpufreq_freq_attr_ro(amd_pstate_max_freq);
  cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
 

@@ -1044,6 +1128,8 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf);
  cpufreq_freq_attr_rw(energy_performance_preference);
  cpufreq_freq_attr_ro(energy_performance_available_preferences);
  static DEVICE_ATTR_RW(status);
+static DEVICE_ATTR_RO(hw_prefcore);
+static DEVICE_ATTR_RO(prefcore);
 
  static struct freq_attr *amd_pstate_attr[] = {
  	&amd_pstate_max_freq,

@@ -1063,6 +1149,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
 
  static struct attribute *pstate_global_attributes[] = {
  	&dev_attr_status.attr,
+	&dev_attr_prefcore.attr,
  	NULL
  };
 

@@ -1506,6 +1593,8 @@ static int __init amd_pstate_init(void)
  		}
  	}
 
+	amd_pstate_init_prefcore();
+
  	return ret;
 
  global_attr_free:

@@ -1527,7 +1616,17 @@ static int __init amd_pstate_param(char *str)
 
  	return amd_pstate_set_driver(mode_idx);
  }
+
+static int __init amd_prefcore_param(char *str)
+{
+	if (!strcmp(str, "disable"))
+		prefcore = false;
+
+	return 0;
+}
+
  early_param("amd_pstate", amd_pstate_param);
+early_param("amd_prefcore", amd_prefcore_param);
 
  MODULE_AUTHOR("Huang Rui <[email protected]>");
  MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");

amd-pstate driver utilizes the functions and data structures provided by the ITMT architecture to enable the scheduler to favor scheduling on cores which can be get a higher frequency with lower voltage. We call it amd-pstate preferrred core.

Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. amd-pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority.

The initial core rankings are set up by amd-pstate when the system boots.

Add device attribute for hardware preferred core. It will check if the processor and power firmware support preferred core feature.

Add device attribute for preferred core. Only when hardware supports preferred core and user set enabled in early parameter, it can be set to enabled.

Add one new early parameter disable to allow user to disable the preferred core.

Signed-off-by Perry Yuan <[email protected]>

Co-developed-by Perry Yuan <[email protected]>

Signed-off-by Meng Li <[email protected]>

Co-developed-by Meng Li <[email protected]>

Reviewed-by Mario Limonciello <[email protected]>

---
 drivers/cpufreq/amd-pstate.c | 131 ++++++++++++++++++++++++++++++-----
 1 file changed, 115 insertions(+), 16 deletions(-)

drivers/cpufreq/amd-pstate.c +65 -16

index 9a1e194d5cf8..454eb6e789e7 100644
@@ -37,6 +37,7 @@
 #include <linux/uaccess.h>
 #include <linux/static_call.h>
 #include <linux/amd-pstate.h>
+#include <linux/topology.h>
 
 #include <acpi/processor.h>
 #include <acpi/cppc_acpi.h>

@@ -49,6 +50,8 @@
 
 #define AMD_PSTATE_TRANSITION_LATENCY	20000
 #define AMD_PSTATE_TRANSITION_DELAY	1000
+#define AMD_PSTATE_PREFCORE_THRESHOLD	166
+#define AMD_PSTATE_MAX_CPPC_PERF	255
 
 /*
  * TODO: We need more time to fine tune processors with shared memory solution

@@ -65,6 +68,12 @@ static struct cpufreq_driver amd_pstate_epp_driver;
 static int cppc_state = AMD_PSTATE_UNDEFINED;
 static bool cppc_enabled;
 
+/*HW preferred Core featue is supported*/
+static bool hw_prefcore = true;
+
+/*Preferred Core featue is supported*/
+static bool prefcore = true;
+
 /*
  * AMD Energy Preference Performance (EPP)
  * The EPP is used in the CCLK DPM controller to drive

@@ -290,23 +299,21 @@ static inline int amd_pstate_enable(bool enable)
 static int pstate_init_perf(struct amd_cpudata *cpudata)
 {
 	u64 cap1;
-	u32 highest_perf;
 
 	int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
 				     &cap1);
 	if (ret)
 		return ret;
 
-	/*
-	 * TODO: Introduce AMD specific power feature.
-	 *
-	 * CPPC entry doesn't indicate the highest performance in some ASICs.
+	/* For platforms that do not support the preferred core feature, the
+	 * highest_pef may be configured with 166 or 255, to avoid max frequency
+	 * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as
+	 * the default max perf.
 	 */
-	highest_perf = amd_get_highest_perf();
-	if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1))
-		highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
-
-	WRITE_ONCE(cpudata->highest_perf, highest_perf);
+	if (prefcore)
+		WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD);
+	else
+		WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
 
 	WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));

@@ -318,17 +325,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)
 static int cppc_init_perf(struct amd_cpudata *cpudata)
 {
 	struct cppc_perf_caps cppc_perf;
-	u32 highest_perf;
 
 	int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
 	if (ret)
 		return ret;
 
-	highest_perf = amd_get_highest_perf();
-	if (highest_perf > cppc_perf.highest_perf)
-		highest_perf = cppc_perf.highest_perf;
-
-	WRITE_ONCE(cpudata->highest_perf, highest_perf);
+	if (prefcore)
+		WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD);
+	else
+		WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf);
 
 	WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf,

@@ -676,6 +681,73 @@ static void amd_perf_ctl_reset(unsigned int cpu)
 	wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0);
 }
 
+/*
+ * Set amd-pstate preferred core enable can't be done directly from cpufreq callbacks
+ * due to locking, so queue the work for later.
+ */
+static void amd_pstste_sched_prefcore_workfn(struct work_struct *work)
+{
+	sched_set_itmt_support();
+}
+static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn);
+
+/*
+ * Get the highest performance register value.
+ * @cpu: CPU from which to get highest performance.
+ * @highest_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf)
+{
+	int ret;
+
+	if (boot_cpu_has(X86_FEATURE_CPPC)) {
+		u64 cap1;
+
+		ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1);
+		if (ret)
+			return ret;
+		WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
+	} else {
+		ret = cppc_get_highest_perf(cpu, highest_perf);
+	}
+
+	return (ret);
+}
+
+static void amd_pstate_init_prefcore(void)
+{
+	int cpu, ret;
+	u64 highest_perf;
+
+	if (!prefcore)
+		return;
+
+	for_each_online_cpu(cpu) {

drivers/cpufreq/amd-pstate.c +13 -0

+			return;
+		}
+	}
+
+	/*
+	 * This code can be run during CPU online under the
+	 * CPU hotplug locks, so sched_set_amd_prefcore_support()
+	 * cannot be called from here.  Queue up a work item
+	 * to invoke it.
+	 */
+	schedule_work(&sched_prefcore_work);
+}
+
 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
 {
 	int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;

drivers/cpufreq/amd-pstate.c +22 -0

+
+static ssize_t prefcore_show(struct device *dev,
+			     struct device_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "%s\n", prefcore ? "enabled" : "disabled");
+}
+
 cpufreq_freq_attr_ro(amd_pstate_max_freq);
 cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
 

@@ -1044,6 +1128,8 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf);
 cpufreq_freq_attr_rw(energy_performance_preference);
 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 static DEVICE_ATTR_RW(status);
+static DEVICE_ATTR_RO(hw_prefcore);
+static DEVICE_ATTR_RO(prefcore);
 
 static struct freq_attr *amd_pstate_attr[] = {
 	&amd_pstate_max_freq,

@@ -1063,6 +1149,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
 
 static struct attribute *pstate_global_attributes[] = {
 	&dev_attr_status.attr,
+	&dev_attr_prefcore.attr,
 	NULL
 };
 

@@ -1506,6 +1593,8 @@ static int __init amd_pstate_init(void)
 		}
 	}
 
+	amd_pstate_init_prefcore();
+
 	return ret;
 
 global_attr_free:

@@ -1527,7 +1616,17 @@ static int __init amd_pstate_param(char *str)
 
 	return amd_pstate_set_driver(mode_idx);
 }
+
+static int __init amd_prefcore_param(char *str)
+{
+	if (!strcmp(str, "disable"))
+		prefcore = false;
+
+	return 0;
+}
+
 early_param("amd_pstate", amd_pstate_param);
+early_param("amd_prefcore", amd_prefcore_param);
 
 MODULE_AUTHOR("Huang Rui <[email protected]>");
 MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");

Signature · 1 line

2.34.1

-----Original Message-----
From: Huang, Ray <[email protected]>
Sent: Wednesday, September 6, 2023 9:53 PM
To: Meng, Li (Jassmine) <[email protected]>
Cc: Rafael J . Wysocki <[email protected]>; linux- [email protected]; [email protected]; [email protected]; linux- [email protected]; Shuah Khan <[email protected]>; linux- [email protected]; Fontenot, Nathan <[email protected]>; Sharma, Deepak <[email protected]>; Deucher, Alexander <[email protected]>; Limonciello, Mario <[email protected]>; Huang, Shimmer <[email protected]>; Yuan, Perry <[email protected]>; Du, Xiaojian <[email protected]>; Viresh Kumar <[email protected]>; Borislav Petkov <[email protected]>
Subject: Re: [PATCH V5 3/7] cpufreq: amd-pstate: Enable amd-pstate preferred core supporting.

Quoted 28 lines · Li (Jassmine)

amd-pstate driver utilizes the functions and data structures provided by the ITMT architecture to enable the scheduler to favor scheduling on cores which can be get a higher frequency with lower voltage. We call it amd-pstate preferrred core.

Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. amd-pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority.

The initial core rankings are set up by amd-pstate when the system boots.

Add device attribute for hardware preferred core. It will check if the processor and power firmware support preferred core feature.

Add device attribute for preferred core. Only when hardware supports preferred core and user set enabled in early parameter, it can be set to enabled.

Add one new early parameter disable to allow user to disable the preferred core.

Signed-off-by Perry Yuan <[email protected]>

Co-developed-by Perry Yuan <[email protected]>

Signed-off-by Meng Li <[email protected]>

Co-developed-by Meng Li <[email protected]>

Reviewed-by Mario Limonciello <[email protected]>

Quoted 7 lines

---
 drivers/cpufreq/amd-pstate.c | 131
++++++++++++++++++++++++++++++-----
 1 file changed, 115 insertions(+), 16 deletions(-)

(quoted diff) +0 -0

b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..454eb6e789e7

100644

Quoted 19 lines

drivers/cpufreq/amd-pstate.c +3 -0

@@ -37,6 +37,7 @@
 #include <linux/uaccess.h>
 #include <linux/static_call.h>
 #include <linux/amd-pstate.h>
+#include <linux/topology.h>
 
 #include <acpi/processor.h>
 #include <acpi/cppc_acpi.h>

@@ -49,6 +50,8 @@
 
 #define AMD_PSTATE_TRANSITION_LATENCY      20000
 #define AMD_PSTATE_TRANSITION_DELAY        1000
+#define AMD_PSTATE_PREFCORE_THRESHOLD      166
+#define AMD_PSTATE_MAX_CPPC_PERF   255
 
 /*
  * TODO: We need more time to fine tune processors with shared memory

Quoted 2 lines

solution @@ -65,6 +68,12 @@ static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state =

AMD_PSTATE_UNDEFINED;

Quoted 14 lines

static bool cppc_enabled;

drivers/cpufreq/amd-pstate.c +6 -0

+/*HW preferred Core featue is supported*/ static bool hw_prefcore =
+true;
+
+/*Preferred Core featue is supported*/ static bool prefcore = true;
+
 /*
  * AMD Energy Preference Performance (EPP)
  * The EPP is used in the CCLK DPM controller to drive @@ -290,23
+299,21 @@ static inline int amd_pstate_enable(bool enable)  static

int pstate_init_perf(struct amd_cpudata *cpudata)  {
    u64 cap1;

drivers/cpufreq/amd-pstate.c +0 -1

-   u32 highest_perf;

drivers/cpufreq/amd-pstate.c static inline int amd_pstate_enable(bool enable)

Quoted 10 lines

drivers/cpufreq/amd-pstate.c +0 -4

 
    int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
                                 &cap1);
    if (ret)
            return ret;
 
-   /*
-    * TODO: Introduce AMD specific power feature.
-    *
-    * CPPC entry doesn't indicate the highest performance in some

ASICs.

drivers/cpufreq/amd-pstate.c

Quoted 2 lines

drivers/cpufreq/amd-pstate.c +2 -0

+   /* For platforms that do not support the preferred core feature, the
+    * highest_pef may be configured with 166 or 255, to avoid max

frequency

Quoted 1 line

+ * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1)

value as

drivers/cpufreq/amd-pstate.c static inline int amd_pstate_enable(bool enable)

Quoted 9 lines

drivers/cpufreq/amd-pstate.c +3 -5

+    * the default max perf.
     */
-   highest_perf = amd_get_highest_perf();
-   if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1))
-           highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
-
-   WRITE_ONCE(cpudata->highest_perf, highest_perf);
+   if (prefcore)
+           WRITE_ONCE(cpudata->highest_perf,

AMD_PSTATE_PREFCORE_THRESHOLD);

drivers/cpufreq/amd-pstate.c

Quoted 2 lines

drivers/cpufreq/amd-pstate.c +2 -0

+   else
+           WRITE_ONCE(cpudata->highest_perf,

AMD_CPPC_HIGHEST_PERF(cap1));

Quoted 2 lines

    WRITE_ONCE(cpudata->nominal_perf,

AMD_CPPC_NOMINAL_PERF(cap1));

Quoted 8 lines

    WRITE_ONCE(cpudata->lowest_nonlinear_perf,
AMD_CPPC_LOWNONLIN_PERF(cap1)); @@ -318,17 +325,15 @@ static int
pstate_init_perf(struct amd_cpudata *cpudata)  static int
cppc_init_perf(struct amd_cpudata *cpudata)  {
    struct cppc_perf_caps cppc_perf;

drivers/cpufreq/amd-pstate.c +0 -1

-   u32 highest_perf;
 
    int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);

drivers/cpufreq/amd-pstate.c static int pstate_init_perf(struct amd_cpudata *cpudata)

Quoted 10 lines

drivers/cpufreq/amd-pstate.c +2 -5

    if (ret)
            return ret;
 
-   highest_perf = amd_get_highest_perf();
-   if (highest_perf > cppc_perf.highest_perf)
-           highest_perf = cppc_perf.highest_perf;
-
-   WRITE_ONCE(cpudata->highest_perf, highest_perf);
+   if (prefcore)
+           WRITE_ONCE(cpudata->highest_perf,

AMD_PSTATE_PREFCORE_THRESHOLD);

drivers/cpufreq/amd-pstate.c

Quoted 2 lines

drivers/cpufreq/amd-pstate.c +2 -0

+   else
+           WRITE_ONCE(cpudata->highest_perf,

cppc_perf.highest_perf);

Quoted 22 lines

    WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
    WRITE_ONCE(cpudata->lowest_nonlinear_perf,

drivers/cpufreq/amd-pstate.c +16 -0

@@ -676,6 +681,73 @@ static void amd_perf_ctl_reset(unsigned int cpu)
    wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0);  }
 
+/*
+ * Set amd-pstate preferred core enable can't be done directly from
+cpufreq callbacks
+ * due to locking, so queue the work for later.
+ */
+static void amd_pstste_sched_prefcore_workfn(struct work_struct
+*work) {
+   sched_set_itmt_support();
+}
+static DECLARE_WORK(sched_prefcore_work,
+amd_pstste_sched_prefcore_workfn);
+
+/*
+ * Get the highest performance register value.
+ * @cpu: CPU from which to get highest performance.
+ * @highest_perf: Return address.

drivers/cpufreq/amd-pstate.c static void amd_perf_ctl_reset(unsigned int cpu) · line 708

Quoted 10 lines

drivers/cpufreq/amd-pstate.c +10 -0

+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf) {
+   int ret;
+
+   if (boot_cpu_has(X86_FEATURE_CPPC)) {
+           u64 cap1;
+
+           ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1,

&cap1);

drivers/cpufreq/amd-pstate.c static void amd_perf_ctl_reset(unsigned int cpu)

Quoted 3 lines

drivers/cpufreq/amd-pstate.c +3 -0

+           if (ret)
+                   return ret;
+           WRITE_ONCE(*highest_perf,

AMD_CPPC_HIGHEST_PERF(cap1));

Quoted 21 lines

drivers/cpufreq/amd-pstate.c +21 -0

+   } else {
+           ret = cppc_get_highest_perf(cpu, highest_perf);
+   }
+
+   return (ret);
+}
+
+static void amd_pstate_init_prefcore(void) {
+   int cpu, ret;
+   u64 highest_perf;
+
+   if (!prefcore)
+           return;
+
+   for_each_online_cpu(cpu) {
+           ret = amd_pstate_get_highest_perf(cpu, &highest_perf);
+           if (ret)
+                   break;
+
+           sched_set_itmt_core_prio(highest_perf, cpu);
+

drivers/cpufreq/amd-pstate.c static void amd_perf_ctl_reset(unsigned int cpu) · line 737

Quoted 4 lines

drivers/cpufreq/amd-pstate.c +4 -0

+           /* check if CPPC preferred core feature is enabled*/
+           if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) {
+                   hw_prefcore = false;
+                   prefcore = false;

I think you should use prefcore which embeds into cpudata structure instead of global variable. Here, actually, you walked through all online cpus, the last cpu's status will overwrite the previous one.

Quoted 5 lines

drivers/cpufreq/amd-pstate.c +5 -0

+                   return;
+           }
+   }
+
+   /*

drivers/cpufreq/amd-pstate.c static void amd_perf_ctl_reset(unsigned int cpu) · line 753

Quoted 10 lines

drivers/cpufreq/amd-pstate.c +8 -0

+    * This code can be run during CPU online under the
+    * CPU hotplug locks, so sched_set_amd_prefcore_support()
+    * cannot be called from here.  Queue up a work item
+    * to invoke it.
+    */
+   schedule_work(&sched_prefcore_work);
+}
+
 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)  {
    int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;

@@

drivers/cpufreq/amd-pstate.c static void amd_perf_ctl_reset(unsigned int cpu) · line 680

Quoted 1 line

drivers/cpufreq/amd-pstate.c +0 -1

-1037,6 +1109,18 @@ static ssize_t status_store(struct device *a, struct

device_attribute *b,

drivers/cpufreq/amd-pstate.c static ssize_t status_store(struct device *a, struct device_attribute *b,

Quoted 7 lines

drivers/cpufreq/amd-pstate.c +4 -0

    return ret < 0 ? ret : count;
 }
 
+static ssize_t hw_prefcore_show(struct device *dev,
+                           struct device_attribute *attr, char *buf) {
+   return sysfs_emit(buf, "%s\n", hw_prefcore ? "supported" :
+"unsupported"); }

Is there any requirement from user space (cpupower or other tool) to query the capacity at runtime? In fact, we can simplify the codes that use a print in the kernel to let user know whether current cpu supports prefcore in hardware side.

Thanks,
Ray

Quoted 55 lines

drivers/cpufreq/amd-pstate.c +19 -1

+
+static ssize_t prefcore_show(struct device *dev,
+                        struct device_attribute *attr, char *buf) {
+   return sysfs_emit(buf, "%s\n", prefcore ? "enabled" : "disabled"); }
+
 cpufreq_freq_attr_ro(amd_pstate_max_freq);
 cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);

@@ -1044,6 +1128,8 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf);
 cpufreq_freq_attr_rw(energy_performance_preference);
 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 static DEVICE_ATTR_RW(status);
+static DEVICE_ATTR_RO(hw_prefcore);
+static DEVICE_ATTR_RO(prefcore);
 
 static struct freq_attr *amd_pstate_attr[] = {
    &amd_pstate_max_freq,

@@ -1063,6 +1149,7 @@ static struct freq_attr *amd_pstate_epp_attr[] =
 {
 
 static struct attribute *pstate_global_attributes[] = {
    &dev_attr_status.attr,
+   &dev_attr_prefcore.attr,
    NULL
 };

@@ -1506,6 +1593,8 @@ static int __init amd_pstate_init(void)
            }
    }
 
+   amd_pstate_init_prefcore();
+
    return ret;
 
 global_attr_free:

@@ -1527,7 +1616,17 @@ static int __init amd_pstate_param(char *str)
 
    return amd_pstate_set_driver(mode_idx);  }
+
+static int __init amd_prefcore_param(char *str) {
+   if (!strcmp(str, "disable"))
+           prefcore = false;
+
+   return 0;
+}
+
 early_param("amd_pstate", amd_pstate_param);
+early_param("amd_prefcore", amd_prefcore_param);
 
 MODULE_AUTHOR("Huang Rui <[email protected]>");
 MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");
--

2.34.1

amd-pstate driver utilizes the functions and data structures provided by the ITMT architecture to enable the scheduler to favor scheduling on cores which can be get a higher frequency with lower voltage. We call it amd-pstate preferrred core.

Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. amd-pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority.

The initial core rankings are set up by amd-pstate when the system boots.

Add device attribute for hardware preferred core. It will check if the processor and power firmware support preferred core feature.

Add device attribute for preferred core. Only when hardware supports preferred core and user set enabled in early parameter, it can be set to enabled.

Add one new early parameter disable to allow user to disable the preferred core.

Signed-off-by Perry Yuan <[email protected]>

Co-developed-by Perry Yuan <[email protected]>

Signed-off-by Meng Li <[email protected]>

Co-developed-by Meng Li <[email protected]>

Reviewed-by Mario Limonciello <[email protected]>

---
 drivers/cpufreq/amd-pstate.c | 131 ++++++++++++++++++++++++++++++-----
 1 file changed, 115 insertions(+), 16 deletions(-)

drivers/cpufreq/amd-pstate.c +13 -5

index 9a1e194d5cf8..454eb6e789e7 100644
@@ -37,6 +37,7 @@
 #include <linux/uaccess.h>
 #include <linux/static_call.h>
 #include <linux/amd-pstate.h>
+#include <linux/topology.h>
 
 #include <acpi/processor.h>
 #include <acpi/cppc_acpi.h>

@@ -49,6 +50,8 @@
 
 #define AMD_PSTATE_TRANSITION_LATENCY	20000
 #define AMD_PSTATE_TRANSITION_DELAY	1000
+#define AMD_PSTATE_PREFCORE_THRESHOLD	166
+#define AMD_PSTATE_MAX_CPPC_PERF	255
 
 /*
  * TODO: We need more time to fine tune processors with shared memory solution

@@ -65,6 +68,12 @@ static struct cpufreq_driver amd_pstate_epp_driver;
 static int cppc_state = AMD_PSTATE_UNDEFINED;
 static bool cppc_enabled;
 
+/*HW preferred Core featue is supported*/
+static bool hw_prefcore = true;
+
+/*Preferred Core featue is supported*/
+static bool prefcore = true;
+
 /*
  * AMD Energy Preference Performance (EPP)
  * The EPP is used in the CCLK DPM controller to drive

@@ -290,23 +299,21 @@ static inline int amd_pstate_enable(bool enable)
 static int pstate_init_perf(struct amd_cpudata *cpudata)
 {
 	u64 cap1;
-	u32 highest_perf;
 
 	int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
 				     &cap1);
 	if (ret)
 		return ret;
 
-	/*
-	 * TODO: Introduce AMD specific power feature.
-	 *
-	 * CPPC entry doesn't indicate the highest performance in some ASICs.
+	/* For platforms that do not support the preferred core feature, the
+	 * highest_pef may be configured with 166 or 255, to avoid max frequency
+	 * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as
+	 * the default max perf.

drivers/cpufreq/amd-pstate.c +0 -1

 	WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));

@@ -318,17 +325,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)
 static int cppc_init_perf(struct amd_cpudata *cpudata)
 {
 	struct cppc_perf_caps cppc_perf;
-	u32 highest_perf;
 
 	int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
 	if (ret)
 		return ret;

drivers/cpufreq/amd-pstate.c +94 -0

 	WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf,

@@ -676,6 +681,73 @@ static void amd_perf_ctl_reset(unsigned int cpu)
 	wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0);
 }
 
+/*
+ * Set amd-pstate preferred core enable can't be done directly from cpufreq callbacks
+ * due to locking, so queue the work for later.
+ */
+static void amd_pstste_sched_prefcore_workfn(struct work_struct *work)
+{
+	sched_set_itmt_support();
+}
+static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn);
+
+/*
+ * Get the highest performance register value.
+ * @cpu: CPU from which to get highest performance.
+ * @highest_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf)
+{
+	int ret;
+
+	if (boot_cpu_has(X86_FEATURE_CPPC)) {
+		u64 cap1;
+
+		ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1);
+		if (ret)
+			return ret;
+		WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
+	} else {
+		ret = cppc_get_highest_perf(cpu, highest_perf);
+	}
+
+	return (ret);
+}
+
+static void amd_pstate_init_prefcore(void)
+{
+	int cpu, ret;
+	u64 highest_perf;
+
+	if (!prefcore)
+		return;
+
+	for_each_online_cpu(cpu) {
+		ret = amd_pstate_get_highest_perf(cpu, &highest_perf);
+		if (ret)
+			break;
+
+		sched_set_itmt_core_prio(highest_perf, cpu);
+
+		/* check if CPPC preferred core feature is enabled*/
+		if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) {
+			hw_prefcore = false;
+			prefcore = false;
+			return;
+		}
+	}
+
+	/*
+	 * This code can be run during CPU online under the
+	 * CPU hotplug locks, so sched_set_amd_prefcore_support()
+	 * cannot be called from here.  Queue up a work item
+	 * to invoke it.
+	 */
+	schedule_work(&sched_prefcore_work);
+}
+
 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
 {
 	int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;

@@ -1037,6 +1109,18 @@ static ssize_t status_store(struct device *a, struct device_attribute *b,
 	return ret < 0 ? ret : count;
 }
 
+static ssize_t hw_prefcore_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "%s\n", hw_prefcore ? "supported" : "unsupported");
+}
+
+static ssize_t prefcore_show(struct device *dev,
+			     struct device_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "%s\n", prefcore ? "enabled" : "disabled");
+}
+
 cpufreq_freq_attr_ro(amd_pstate_max_freq);
 cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
 

@@ -1044,6 +1128,8 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf);
 cpufreq_freq_attr_rw(energy_performance_preference);
 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 static DEVICE_ATTR_RW(status);
+static DEVICE_ATTR_RO(hw_prefcore);
+static DEVICE_ATTR_RO(prefcore);
 
 static struct freq_attr *amd_pstate_attr[] = {
 	&amd_pstate_max_freq,

@@ -1063,6 +1149,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
 
 static struct attribute *pstate_global_attributes[] = {
 	&dev_attr_status.attr,
+	&dev_attr_prefcore.attr,
 	NULL
 };
 

@@ -1506,6 +1593,8 @@ static int __init amd_pstate_init(void)
 		}
 	}
 
+	amd_pstate_init_prefcore();
+
 	return ret;
 
 global_attr_free:

@@ -1527,7 +1616,17 @@ static int __init amd_pstate_param(char *str)
 
 	return amd_pstate_set_driver(mode_idx);
 }
+
+static int __init amd_prefcore_param(char *str)
+{
+	if (!strcmp(str, "disable"))
+		prefcore = false;
+
+	return 0;
+}
+
 early_param("amd_pstate", amd_pstate_param);
+early_param("amd_prefcore", amd_prefcore_param);
 
 MODULE_AUTHOR("Huang Rui <[email protected]>");
 MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");

Signature · 1 line

2.34.1

drivers/cpufreq/amd-pstate.c +4 -0

+	 * cannot be called from here.  Queue up a work item
+	 * to invoke it.
+	 */
+	schedule_work(&sched_prefcore_work);

drivers/cpufreq/amd-pstate.c +31 -0

+static void amd_pstate_init_prefcore(void)
+{
+	int cpu, ret;
+	u64 highest_perf;
+
+	if (!prefcore)
+		return;
+
+	for_each_online_cpu(cpu) {
+		ret = amd_pstate_get_highest_perf(cpu, &highest_perf);
+		if (ret)
+			break;
+
+		sched_set_itmt_core_prio(highest_perf, cpu);
+
+		/* check if CPPC preferred core feature is enabled*/
+		if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) {
+			hw_prefcore = false;
+			prefcore = false;
+			return;
+		}
+	}
+
+	/*
+	 * This code can be run during CPU online under the
+	 * CPU hotplug locks, so sched_set_amd_prefcore_support()
+	 * cannot be called from here.  Queue up a work item
+	 * to invoke it.
+	 */
+	schedule_work(&sched_prefcore_work);
+}

ACPI 6.5 section 8.4.6.1.1.1 specifies that Notify event 0x85 can be emmitted to cause the the OSPM to re-evaluate the highest performance register. Add support for this event.

Signed-off-by Meng Li <[email protected]>

Link https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html?highlight=cppc#cpc-continuous-performance-control

ACPI 6.5 section 8.4.6.1.1.1 specifies that Notify event 0x85 can be emmitted to cause the the OSPM to re-evaluate the highest performance register. Add support for this event.

Signed-off-by Meng Li <[email protected]>

Link https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html?highlight=cppc#cpc-continuous-performance-control

---
 drivers/acpi/processor_driver.c |  6 ++++++
 drivers/cpufreq/cpufreq.c       | 13 +++++++++++++
 include/linux/cpufreq.h         |  5 +++++
 3 files changed, 24 insertions(+)

drivers/acpi/processor_driver.c +1 -0

index 4bd16b3f0781..29b2fb68a35d 100644
@@ -27,6 +27,7 @@
 #define ACPI_PROCESSOR_NOTIFY_PERFORMANCE 0x80
 #define ACPI_PROCESSOR_NOTIFY_POWER	0x81
 #define ACPI_PROCESSOR_NOTIFY_THROTTLING	0x82
+#define ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED	0x85
 
 MODULE_AUTHOR("Paul Diefenbaugh");
 MODULE_DESCRIPTION("ACPI Processor Driver");

@@ -83,6 +84,11 @@ static void acpi_processor_notify(acpi_handle handle, u32 event, void *data)
 		acpi_bus_generate_netlink_event(device->pnp.device_class,

-----Original Message-----
From: Peter Zijlstra <[email protected]>
Sent: Friday, September 8, 2023 9:24 PM
To: Meng, Li (Jassmine) <[email protected]>
Cc: Rafael J . Wysocki <[email protected]>; Huang, Ray <[email protected]>; [email protected]; linux- [email protected]; [email protected]; [email protected]; Shuah Khan <[email protected]>; [email protected]; Fontenot, Nathan <[email protected]>; Sharma, Deepak <[email protected]>; Deucher, Alexander <[email protected]>; Limonciello, Mario <[email protected]>; Huang, Shimmer <[email protected]>; Yuan, Perry <[email protected]>; Du, Xiaojian <[email protected]>; Viresh Kumar <[email protected]>; Borislav Petkov <[email protected]>
Subject: Re: [PATCH V5 4/7] cpufreq: Add a notification message that the highest perf has changed

Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.

Quoted 25 lines · Meng Li

ACPI 6.5 section 8.4.6.1.1.1 specifies that Notify event 0x85 can be emmitted to cause the the OSPM to re-evaluate the highest performance register. Add support for this event.

Signed-off-by Meng Li <[email protected]>

Link:
https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control
.html?highlight=cppc#cpc-continuous-performance-control

---
 drivers/acpi/processor_driver.c |  6 ++++++
 drivers/cpufreq/cpufreq.c       | 13 +++++++++++++
 include/linux/cpufreq.h         |  5 +++++
 3 files changed, 24 insertions(+)

(quoted diff) +0 -0

b/drivers/acpi/processor_driver.c index 4bd16b3f0781..29b2fb68a35d 100644

drivers/acpi/processor_driver.c +0 -0

@@ -27,6 +27,7 @@
 #define ACPI_PROCESSOR_NOTIFY_PERFORMANCE 0x80  #define

ACPI_PROCESSOR_NOTIFY_POWER 0x81
#define ACPI_PROCESSOR_NOTIFY_THROTTLING 0x82
+#define ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED 0x85

Quoted 3 lines

MODULE_AUTHOR("Paul Diefenbaugh"); MODULE_DESCRIPTION("ACPI Processor Driver"); @@ -83,6 +84,11 @@
static void acpi_processor_notify(acpi_handle handle, u32 event, void

*data)

drivers/acpi/processor_driver.c static void acpi_processor_notify(acpi_handle handle, u32 event, void *data) · line 94

Quoted 11 lines

              acpi_bus_generate_netlink_event(device->pnp.device_class,
                                                dev_name(&device->dev), event, 0);
              break;

drivers/acpi/processor_driver.c +5 -0

+     case ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED:
+             cpufreq_update_highest_perf(pr->id);
+             acpi_bus_generate_netlink_event(device->pnp.device_class,
+                                               dev_name(&device->dev), event, 0);
+             break;
      default:
              acpi_handle_debug(handle, "Unsupported event [0x%x]\n", event);
              break;

I've obviously not read the link, but the above seems to suggest that every CPU that has its limits changed gets the 'interrupt' ?

Preferred core rankings can be changed dynamically by the platform based on the workload and platform conditions and accounting for thermals and aging.
When this occurs, cpu priority need to be set.

Signed-off-by Meng Li <[email protected]>

Reviewed-by Wyes Karny <[email protected]>

---
 drivers/cpufreq/amd-pstate.c | 36 ++++++++++++++++++++++++++++++++++--
 include/linux/amd-pstate.h   | 11 +++++++++++
 2 files changed, 45 insertions(+), 2 deletions(-)

drivers/cpufreq/amd-pstate.c +34 -2

index 454eb6e789e7..8c19e1d50d29 100644
@@ -318,6 +318,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)
 	WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));
 	WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1));
+	WRITE_ONCE(cpudata->cppc_highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
 
 	return 0;
 }

@@ -339,6 +340,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata)
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf,
 		   cppc_perf.lowest_nonlinear_perf);
 	WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf);
+	WRITE_ONCE(cpudata->cppc_highest_perf, cppc_perf.highest_perf);
 
 	if (cppc_state == AMD_PSTATE_ACTIVE)
 		return 0;

@@ -545,7 +547,7 @@ static void amd_pstate_adjust_perf(unsigned int cpu,
 	if (target_perf < capacity)
 		des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity);
 
-	min_perf = READ_ONCE(cpudata->highest_perf);
+	min_perf = READ_ONCE(cpudata->lowest_perf);
 	if (_min_perf < capacity)
 		min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity);
 

@@ -748,6 +750,34 @@ static void amd_pstate_init_prefcore(void)
 	schedule_work(&sched_prefcore_work);
 }
 
+static void amd_pstate_update_highest_perf(unsigned int cpu)
+{
+	struct cpufreq_policy *policy;
+	struct amd_cpudata *cpudata;
+	u32 prev_high = 0, cur_high = 0;
+	u64 highest_perf;
+	int ret;
+
+	if (!prefcore)
+		return;
+
+	ret = amd_pstate_get_highest_perf(cpu, &highest_perf);
+	if (ret)
+		return;
+
+	policy = cpufreq_cpu_get(cpu);
+	cpudata = policy->driver_data;
+	cur_high = highest_perf;
+	prev_high = READ_ONCE(cpudata->cppc_highest_perf);
+
+	if (prev_high != cur_high) {
+		WRITE_ONCE(cpudata->cppc_highest_perf, cur_high);
+		sched_set_itmt_core_prio(cur_high, cpu);
+	}
+
+	cpufreq_cpu_put(policy);
+}
+
 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
 {
 	int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;

@@ -912,7 +942,7 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy,
 	u32 perf;
 	struct amd_cpudata *cpudata = policy->driver_data;
 
-	perf = READ_ONCE(cpudata->highest_perf);
+	perf = READ_ONCE(cpudata->cppc_highest_perf);
 
 	return sysfs_emit(buf, "%u\n", perf);
 }

@@ -1479,6 +1509,7 @@ static struct cpufreq_driver amd_pstate_driver = {
 	.suspend	= amd_pstate_cpu_suspend,
 	.resume		= amd_pstate_cpu_resume,
 	.set_boost	= amd_pstate_set_boost,
+	.update_highest_perf	= amd_pstate_update_highest_perf,
 	.name		= "amd-pstate",
 	.attr		= amd_pstate_attr,
 };

@@ -1493,6 +1524,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = {
 	.online		= amd_pstate_epp_cpu_online,
 	.suspend	= amd_pstate_epp_suspend,
 	.resume		= amd_pstate_epp_resume,
+	.update_highest_perf	= amd_pstate_update_highest_perf,
 	.name		= "amd-pstate-epp",
 	.attr		= amd_pstate_epp_attr,
 };

include/linux/amd-pstate.h +0 -0

index 446394f84606..2159fd5693fe 100644

include/linux/amd-pstate.h +6 -0

 /**
  * struct amd_cpudata - private CPU data for AMD P-State

@@ -39,11 +44,16 @@ struct amd_aperf_mperf {
  * @cppc_req_cached: cached performance request hints
  * @highest_perf: the maximum performance an individual processor may reach,
  *		  assuming ideal conditions
+ *		  For platforms that do not support the preferred core feature, the
+ *		  highest_pef may be configured with 166 or 255, to avoid max frequency
+ *		  calculated wrongly. we take the fixed value as the highest_perf.
  * @nominal_perf: the maximum sustained performance level of the processor,
  *		  assuming ideal operating conditions
  * @lowest_nonlinear_perf: the lowest performance level at which nonlinear power
  *			   savings are achieved
  * @lowest_perf: the absolute lowest performance level of the processor
+ * @cppc_highest_perf: the maximum performance an individual processor may reach,
+ *		  assuming ideal conditions
  * @max_freq: the frequency that mapped to highest_perf
  * @min_freq: the frequency that mapped to lowest_perf
  * @nominal_freq: the frequency that mapped to nominal_perf

@@ -70,6 +80,7 @@ struct amd_cpudata {
 	u32	nominal_perf;
 	u32	lowest_nonlinear_perf;
 	u32	lowest_perf;
+	u32     cppc_highest_perf;
 
 	u32	max_freq;
 	u32	min_freq;

Signature · 1 line

2.34.1

Preferred core rankings can be changed dynamically by the platform based on the workload and platform conditions and accounting for thermals and aging.
When this occurs, cpu priority need to be set.

Signed-off-by Meng Li <[email protected]>

Reviewed-by Wyes Karny <[email protected]>

---
 drivers/cpufreq/amd-pstate.c | 36 ++++++++++++++++++++++++++++++++++--
 include/linux/amd-pstate.h   | 11 +++++++++++
 2 files changed, 45 insertions(+), 2 deletions(-)

drivers/cpufreq/amd-pstate.c +0 -0

index 454eb6e789e7..8c19e1d50d29 100644

drivers/cpufreq/amd-pstate.c +33 -2

 	return 0;
 }

@@ -339,6 +340,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata)
 	WRITE_ONCE(cpudata->lowest_nonlinear_perf,
 		   cppc_perf.lowest_nonlinear_perf);
 	WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf);
+	WRITE_ONCE(cpudata->cppc_highest_perf, cppc_perf.highest_perf);
 
 	if (cppc_state == AMD_PSTATE_ACTIVE)
 		return 0;

@@ -545,7 +547,7 @@ static void amd_pstate_adjust_perf(unsigned int cpu,
 	if (target_perf < capacity)
 		des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity);
 
-	min_perf = READ_ONCE(cpudata->highest_perf);
+	min_perf = READ_ONCE(cpudata->lowest_perf);
 	if (_min_perf < capacity)
 		min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity);
 

@@ -748,6 +750,34 @@ static void amd_pstate_init_prefcore(void)
 	schedule_work(&sched_prefcore_work);
 }
 
+static void amd_pstate_update_highest_perf(unsigned int cpu)
+{
+	struct cpufreq_policy *policy;
+	struct amd_cpudata *cpudata;
+	u32 prev_high = 0, cur_high = 0;
+	u64 highest_perf;
+	int ret;
+
+	if (!prefcore)
+		return;
+
+	ret = amd_pstate_get_highest_perf(cpu, &highest_perf);
+	if (ret)
+		return;
+
+	policy = cpufreq_cpu_get(cpu);
+	cpudata = policy->driver_data;
+	cur_high = highest_perf;
+	prev_high = READ_ONCE(cpudata->cppc_highest_perf);
+
+	if (prev_high != cur_high) {
+		WRITE_ONCE(cpudata->cppc_highest_perf, cur_high);
+		sched_set_itmt_core_prio(cur_high, cpu);
+	}
+
+	cpufreq_cpu_put(policy);
+}
+
 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
 {
 	int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;

@@ -912,7 +942,7 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy,
 	u32 perf;
 	struct amd_cpudata *cpudata = policy->driver_data;
 
-	perf = READ_ONCE(cpudata->highest_perf);
+	perf = READ_ONCE(cpudata->cppc_highest_perf);
 
 	return sysfs_emit(buf, "%u\n", perf);
 }

@@ -1479,6 +1509,7 @@ static struct cpufreq_driver amd_pstate_driver = {
 	.suspend	= amd_pstate_cpu_suspend,
 	.resume		= amd_pstate_cpu_resume,
 	.set_boost	= amd_pstate_set_boost,
+	.update_highest_perf	= amd_pstate_update_highest_perf,
 	.name		= "amd-pstate",
 	.attr		= amd_pstate_attr,
 };

@@ -1493,6 +1524,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = {
 	.online		= amd_pstate_epp_cpu_online,
 	.suspend	= amd_pstate_epp_suspend,
 	.resume		= amd_pstate_epp_resume,
+	.update_highest_perf	= amd_pstate_update_highest_perf,
 	.name		= "amd-pstate-epp",
 	.attr		= amd_pstate_epp_attr,
 };

include/linux/amd-pstate.h +11 -0

index 446394f84606..2159fd5693fe 100644
@@ -31,6 +31,11 @@ struct amd_aperf_mperf {
 	u64 mperf;
 	u64 tsc;
 };
+	/* For platforms that do not support the preferred core feature, the
+	 * highest_pef may be configured with 166 or 255, to avoid max frequency
+	 * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as
+	 * the default max perf.
+	 */
 
 /**
  * struct amd_cpudata - private CPU data for AMD P-State

@@ -39,11 +44,16 @@ struct amd_aperf_mperf {
  * @cppc_req_cached: cached performance request hints
  * @highest_perf: the maximum performance an individual processor may reach,
  *		  assuming ideal conditions
+ *		  For platforms that do not support the preferred core feature, the
+ *		  highest_pef may be configured with 166 or 255, to avoid max frequency
+ *		  calculated wrongly. we take the fixed value as the highest_perf.
  * @nominal_perf: the maximum sustained performance level of the processor,
  *		  assuming ideal operating conditions
  * @lowest_nonlinear_perf: the lowest performance level at which nonlinear power
  *			   savings are achieved
  * @lowest_perf: the absolute lowest performance level of the processor
+ * @cppc_highest_perf: the maximum performance an individual processor may reach,
+ *		  assuming ideal conditions
  * @max_freq: the frequency that mapped to highest_perf
  * @min_freq: the frequency that mapped to lowest_perf
  * @nominal_freq: the frequency that mapped to nominal_perf

@@ -70,6 +80,7 @@ struct amd_cpudata {
 	u32	nominal_perf;
 	u32	lowest_nonlinear_perf;
 	u32	lowest_perf;
+	u32     cppc_highest_perf;
 
 	u32	max_freq;
 	u32	min_freq;

Signature · 1 line

2.34.1

drivers/cpufreq/amd-pstate.c +13 -0

+static void amd_pstate_update_highest_perf(unsigned int cpu)
+{
+	struct cpufreq_policy *policy;
+	struct amd_cpudata *cpudata;
+	u32 prev_high = 0, cur_high = 0;
+	u64 highest_perf;
+	int ret;
+
+	if (!prefcore)
+		return;
+
+	ret = amd_pstate_get_highest_perf(cpu, &highest_perf);
+	if (ret)

drivers/cpufreq/amd-pstate.c +4 -0

+	}
+
+	cpufreq_cpu_put(policy);
+}