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riscv: errata: fix T-Head dcache.cva encoding

PATCH Applied Jisheng Zhang 3 participants 3 messages Sep 12, 2023 – Sep 13, 2023 RISC-V

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Jisheng Zhang

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#0 lore raw

PATCH v3 1/1 riscv: errata: fix T-Head dcache.cva encoding

From: Icenowy Zheng <[email protected]>

The dcache.cva encoding shown in the comments are wrong, it's for dcache.cval1 (which is restricted to L1) instead.

Fix this in the comment and in the hardcoded instruction.

Signed-off-by Icenowy Zheng <[email protected]>
Tested-by Sergey Matyukevich <[email protected]>
Reviewed-by Heiko Stuebner <[email protected]>
Reviewed-by Guo Ren <[email protected]>
Tested-by Drew Fustini <[email protected]>

---

This is a renew of Icenowy patch series[1], patch1 is necessary to make T-Head C910 powered SoCs CMO work correctly.

Link https://lore.kernel.org/linux-riscv/[email protected]/ [1] open here

Since v2:
- rebase on linux 6.6-rc1
- collect Tested-by tag
- remove patch2 since I want patch1 to be applied as fix for linux-6.6. patch2 will be sent separately.

Since v1:
- rebase on linux 6.5-rc7
- collect Reviewed-by tag

 arch/riscv/include/asm/errata_list.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/riscv/include/asm/errata_list.h +2 -2
index e2ecd01bfac7..b55b434f0059 100644
@@ -105,7 +105,7 @@ asm volatile(ALTERNATIVE(						\
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000001    01001      rs1       000      00000  0001011
  * dcache.cva rs1 (clean, virtual address)
- *   0000001    00100      rs1       000      00000  0001011
+ *   0000001    00101      rs1       000      00000  0001011
  *
  * dcache.cipa rs1 (clean then invalidate, physical address)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |

@@ -118,7 +118,7 @@ asm volatile(ALTERNATIVE(						\
  *   0000000    11001     00000      000      00000  0001011
  */
 #define THEAD_inval_A0	".long 0x0265000b"
-#define THEAD_clean_A0	".long 0x0245000b"
+#define THEAD_clean_A0	".long 0x0255000b"
 #define THEAD_flush_A0	".long 0x0275000b"
 #define THEAD_SYNC_S	".long 0x0190000b"
Signature · 1 line
2.40.1
Applied
#1 lore raw
Quoted 6 lines · Jisheng Zhang

The dcache.cva encoding shown in the comments are wrong, it's for dcache.cval1 (which is restricted to L1) instead.

Fix this in the comment and in the hardcoded instruction.

Applied, thanks!

[1/1] riscv: errata: fix T-Head dcache.cva encoding

      https://git.kernel.org/palmer/c/8eb8fe67e2c8

Best regards,

Signature · 1 line
Palmer Dabbelt <[email protected]>
CI Applied
#2 lore raw
In reply to Jisheng Zhang
This patch was applied to riscv/linux.git (fixes) by Palmer Dabbelt <[email protected]>:

Hello:

This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <[email protected]>:

Quoted 8 lines · On Tue, 12 Sep 2023 15:24:10 +0800 you wrote:

From: Icenowy Zheng <[email protected]>

The dcache.cva encoding shown in the comments are wrong, it's for dcache.cval1 (which is restricted to L1) instead.

Fix this in the comment and in the hardcoded instruction.

[...]

Here is the summary with links:
- [v3] riscv: errata: fix T-Head dcache.cva encoding

    https://git.kernel.org/riscv/c/8eb8fe67e2c8

You are awesome, thank you!

Signature · 2 lines
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