RISC-V: Enable cbo.zero in usermode

When Zicboz is present, enable its instruction (cbo.zero) in usermode by setting its respective senvcfg bit. We don't bother trying to set this bit per-task, which would also require an interface for tasks to request enabling and/or disabling. Instead, permanently set the bit for each hart which has the extension when bringing it online.

This patch also introduces riscv_cpu_has_extension_[un]likely() functions to check a specific hart's ISA bitmap for extensions. Prior to checking the specific hart's bitmap in these functions we try the bitmap which represents the LCD of extensions, but only when we know it will use its optimized, alternatives path by gating its call on CONFIG_RISCV_ALTERNATIVE. When alternatives are used, the compiler ensures that the invocation of the LCD search becomes a constant true or false. When it's true, even the new functions will completely vanish from their callsites. OTOH, when the LCD check is false, we need to do a search of the hart's ISA bitmap. Had we also checked the LCD bitmap without the use of alternatives, then we would have ended up with two bitmap searches instead of one.

Signed-off-by Andrew Jones <[email protected]>

Reviewed-by Conor Dooley <[email protected]>

---
 arch/riscv/include/asm/cpufeature.h |  1 +
 arch/riscv/include/asm/csr.h        |  1 +
 arch/riscv/include/asm/hwcap.h      | 16 ++++++++++++++++
 arch/riscv/kernel/cpufeature.c      |  6 ++++++
 arch/riscv/kernel/setup.c           |  4 ++++
 arch/riscv/kernel/smpboot.c         |  4 ++++
 6 files changed, 32 insertions(+)

arch/riscv/include/asm/cpufeature.h +1 -0

index d0345bd659c9..13b7d35648a9 100644
@@ -31,5 +31,6 @@ DECLARE_PER_CPU(long, misaligned_access_speed);
 extern struct riscv_isainfo hart_isa[NR_CPUS];
 
 void check_unaligned_access(int cpu);
+void riscv_user_isa_enable(void);
 
 #endif

arch/riscv/include/asm/csr.h +1 -0

index 777cb8299551..5fba25db82d2 100644
@@ -275,6 +275,7 @@
 #define CSR_SIE			0x104
 #define CSR_STVEC		0x105
 #define CSR_SCOUNTEREN		0x106
+#define CSR_SENVCFG		0x10a
 #define CSR_SSCRATCH		0x140
 #define CSR_SEPC		0x141
 #define CSR_SCAUSE		0x142

arch/riscv/include/asm/hwcap.h +16 -0

index b7b58258f6c7..31774bcdf1c6 100644
@@ -70,6 +70,7 @@
 #ifndef __ASSEMBLY__
 
 #include <linux/jump_label.h>
+#include <asm/cpufeature.h>
 
 unsigned long riscv_get_elf_hwcap(void);
 

@@ -137,6 +138,21 @@ riscv_has_extension_unlikely(const unsigned long ext)
 	return true;
 }
 
+static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
+{
+	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))
+		return true;
+
+	return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
+}
+
+static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)
+{
+	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))
+		return true;
+
+	return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
+}
 #endif
 
 #endif /* _ASM_RISCV_HWCAP_H */

arch/riscv/kernel/cpufeature.c +0 -0

index f9ac2717bc7d..8ad6da03ee34 100644

arch/riscv/kernel/cpufeature.c +2 -0

+}
+
 #ifdef CONFIG_RISCV_ALTERNATIVE
 /*
  * Alternative patch sites consider 48 bits when determining when to patch

arch/riscv/kernel/setup.c +4 -0

index e600aab116a4..8fd6c02353d4 100644
@@ -26,6 +26,7 @@
 #include <asm/acpi.h>
 #include <asm/alternative.h>
 #include <asm/cacheflush.h>
+#include <asm/cpufeature.h>
 #include <asm/cpu_ops.h>
 #include <asm/early_ioremap.h>
 #include <asm/pgtable.h>

@@ -314,10 +315,13 @@ void __init setup_arch(char **cmdline_p)
 	riscv_fill_hwcap();
 	init_rt_signal_env();
 	apply_boot_alternatives();
+
 	if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
 	    riscv_isa_extension_available(NULL, ZICBOM))
 		riscv_noncoherent_supported();
 	riscv_set_dma_cache_alignment();
+
+	riscv_user_isa_enable();
 }
 
 static int __init topology_init(void)

arch/riscv/kernel/smpboot.c +2 -0

index 1b8da4e40a4d..d1b0a6fc3adf 100644
@@ -25,6 +25,8 @@
 #include <linux/of.h>
 #include <linux/sched/task_stack.h>
 #include <linux/sched/mm.h>
+
+#include <asm/cpufeature.h>
 #include <asm/cpu_ops.h>
 #include <asm/cpufeature.h>
 #include <asm/irq.h>

Quoted 93 lines · On Mon, 18 Sep 2023 06:15:21 PDT (-0700), [email protected] wrote:

When Zicboz is present, enable its instruction (cbo.zero) in usermode by setting its respective senvcfg bit. We don't bother trying to set this bit per-task, which would also require an interface for tasks to request enabling and/or disabling. Instead, permanently set the bit for each hart which has the extension when bringing it online.

This patch also introduces riscv_cpu_has_extension_[un]likely() functions to check a specific hart's ISA bitmap for extensions. Prior to checking the specific hart's bitmap in these functions we try the bitmap which represents the LCD of extensions, but only when we know it will use its optimized, alternatives path by gating its call on CONFIG_RISCV_ALTERNATIVE. When alternatives are used, the compiler ensures that the invocation of the LCD search becomes a constant true or false. When it's true, even the new functions will completely vanish from their callsites. OTOH, when the LCD check is false, we need to do a search of the hart's ISA bitmap. Had we also checked the LCD bitmap without the use of alternatives, then we would have ended up with two bitmap searches instead of one.

Signed-off-by Andrew Jones <[email protected]>

Reviewed-by Conor Dooley <[email protected]>

---
 arch/riscv/include/asm/cpufeature.h |  1 +
 arch/riscv/include/asm/csr.h        |  1 +
 arch/riscv/include/asm/hwcap.h      | 16 ++++++++++++++++
 arch/riscv/kernel/cpufeature.c      |  6 ++++++
 arch/riscv/kernel/setup.c           |  4 ++++
 arch/riscv/kernel/smpboot.c         |  4 ++++
 6 files changed, 32 insertions(+)

arch/riscv/include/asm/cpufeature.h +1 -0

index d0345bd659c9..13b7d35648a9 100644
@@ -31,5 +31,6 @@ DECLARE_PER_CPU(long, misaligned_access_speed);
 extern struct riscv_isainfo hart_isa[NR_CPUS];
 
 void check_unaligned_access(int cpu);
+void riscv_user_isa_enable(void);
 
 #endif

arch/riscv/include/asm/csr.h +1 -0

index 777cb8299551..5fba25db82d2 100644
@@ -275,6 +275,7 @@
 #define CSR_SIE                      0x104
 #define CSR_STVEC            0x105
 #define CSR_SCOUNTEREN               0x106
+#define CSR_SENVCFG          0x10a
 #define CSR_SSCRATCH         0x140
 #define CSR_SEPC             0x141
 #define CSR_SCAUSE           0x142

arch/riscv/include/asm/hwcap.h +16 -0

index b7b58258f6c7..31774bcdf1c6 100644
@@ -70,6 +70,7 @@
 #ifndef __ASSEMBLY__
 
 #include <linux/jump_label.h>
+#include <asm/cpufeature.h>
 
 unsigned long riscv_get_elf_hwcap(void);
 

@@ -137,6 +138,21 @@ riscv_has_extension_unlikely(const unsigned long ext)
      return true;
 }
 
+static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
+{
+     if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))
+             return true;
+
+     return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
+}
+
+static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)
+{
+     if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))
+             return true;
+
+     return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
+}
 #endif
 
 #endif /* _ASM_RISCV_HWCAP_H */

arch/riscv/kernel/cpufeature.c +0 -0

index f9ac2717bc7d..8ad6da03ee34 100644

arch/riscv/kernel/cpufeature.c static int check_unaligned_access_boot_cpu(void) · line 659

Quoted 7 lines

arch/riscv/kernel/cpufeature.c +4 -0

@@ -653,6 +653,12 @@ static int check_unaligned_access_boot_cpu(void)
 
 arch_initcall(check_unaligned_access_boot_cpu);
 
+void riscv_user_isa_enable(void)
+{
+     if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ))
+             csr_set(CSR_SENVCFG, ENVCFG_CBZE);

It looks like CBZE didn't actually get ratified? The CMO extension says

_The CMO extensions rely on state in {csrname} CSRs that will be defined in a future update to the privileged architecture. If this CSR update is not ratified, the CMO extension will define its own CSRs._

but the privileged spec says

The definition of the CBZE field will be furnished by the forthcoming Zicboz extension. Its allocation within senvcfg may change prior to the ratification of that extension.

Is there some ratified spec that actually defines this?

Quoted 49 lines

arch/riscv/kernel/cpufeature.c +2 -0

+}
+
 #ifdef CONFIG_RISCV_ALTERNATIVE
 /*
  * Alternative patch sites consider 48 bits when determining when to patch

arch/riscv/kernel/setup.c +4 -0

index e600aab116a4..8fd6c02353d4 100644
@@ -26,6 +26,7 @@
 #include <asm/acpi.h>
 #include <asm/alternative.h>
 #include <asm/cacheflush.h>
+#include <asm/cpufeature.h>
 #include <asm/cpu_ops.h>
 #include <asm/early_ioremap.h>
 #include <asm/pgtable.h>

@@ -314,10 +315,13 @@ void __init setup_arch(char **cmdline_p)
      riscv_fill_hwcap();
      init_rt_signal_env();
      apply_boot_alternatives();
+
      if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
          riscv_isa_extension_available(NULL, ZICBOM))
              riscv_noncoherent_supported();
      riscv_set_dma_cache_alignment();
+
+     riscv_user_isa_enable();
 }
 
 static int __init topology_init(void)

arch/riscv/kernel/smpboot.c +2 -0

index 1b8da4e40a4d..d1b0a6fc3adf 100644
@@ -25,6 +25,8 @@
 #include <linux/of.h>
 #include <linux/sched/task_stack.h>
 #include <linux/sched/mm.h>
+
+#include <asm/cpufeature.h>
 #include <asm/cpu_ops.h>
 #include <asm/cpufeature.h>
 #include <asm/irq.h>

@@ -253,6 +255,8 @@ asmlinkage __visible void smp_callin(void)
                      elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
      }
 

arch/riscv/kernel/smpboot.c asmlinkage __visible void smp_callin(void) · line 262

Quoted 5 lines

arch/riscv/kernel/smpboot.c +2 -0

+     riscv_user_isa_enable();
+
      /*
       * Remote TLB flushes are ignored while the CPU is offline, so emit
       * a local TLB flush right now just in case.

Quoted 93 lines · On Mon, 18 Sep 2023 06:15:21 PDT (-0700), [email protected] wrote:

When Zicboz is present, enable its instruction (cbo.zero) in usermode by setting its respective senvcfg bit. We don't bother trying to set this bit per-task, which would also require an interface for tasks to request enabling and/or disabling. Instead, permanently set the bit for each hart which has the extension when bringing it online.

This patch also introduces riscv_cpu_has_extension_[un]likely() functions to check a specific hart's ISA bitmap for extensions. Prior to checking the specific hart's bitmap in these functions we try the bitmap which represents the LCD of extensions, but only when we know it will use its optimized, alternatives path by gating its call on CONFIG_RISCV_ALTERNATIVE. When alternatives are used, the compiler ensures that the invocation of the LCD search becomes a constant true or false. When it's true, even the new functions will completely vanish from their callsites. OTOH, when the LCD check is false, we need to do a search of the hart's ISA bitmap. Had we also checked the LCD bitmap without the use of alternatives, then we would have ended up with two bitmap searches instead of one.

Signed-off-by Andrew Jones <[email protected]>

Reviewed-by Conor Dooley <[email protected]>

---
 arch/riscv/include/asm/cpufeature.h |  1 +
 arch/riscv/include/asm/csr.h        |  1 +
 arch/riscv/include/asm/hwcap.h      | 16 ++++++++++++++++
 arch/riscv/kernel/cpufeature.c      |  6 ++++++
 arch/riscv/kernel/setup.c           |  4 ++++
 arch/riscv/kernel/smpboot.c         |  4 ++++
 6 files changed, 32 insertions(+)

arch/riscv/include/asm/cpufeature.h +1 -0

index d0345bd659c9..13b7d35648a9 100644
@@ -31,5 +31,6 @@ DECLARE_PER_CPU(long, misaligned_access_speed);
 extern struct riscv_isainfo hart_isa[NR_CPUS];
 
 void check_unaligned_access(int cpu);
+void riscv_user_isa_enable(void);
 
 #endif

arch/riscv/include/asm/csr.h +1 -0

index 777cb8299551..5fba25db82d2 100644
@@ -275,6 +275,7 @@
 #define CSR_SIE                      0x104
 #define CSR_STVEC            0x105
 #define CSR_SCOUNTEREN               0x106
+#define CSR_SENVCFG          0x10a
 #define CSR_SSCRATCH         0x140
 #define CSR_SEPC             0x141
 #define CSR_SCAUSE           0x142

arch/riscv/include/asm/hwcap.h +16 -0

index b7b58258f6c7..31774bcdf1c6 100644
@@ -70,6 +70,7 @@
 #ifndef __ASSEMBLY__
 
 #include <linux/jump_label.h>
+#include <asm/cpufeature.h>
 
 unsigned long riscv_get_elf_hwcap(void);
 

@@ -137,6 +138,21 @@ riscv_has_extension_unlikely(const unsigned long ext)
      return true;
 }
 
+static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
+{
+     if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))
+             return true;
+
+     return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
+}
+
+static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)
+{
+     if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))
+             return true;
+
+     return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
+}
 #endif
 
 #endif /* _ASM_RISCV_HWCAP_H */

arch/riscv/kernel/cpufeature.c +0 -0

index f9ac2717bc7d..8ad6da03ee34 100644

arch/riscv/kernel/cpufeature.c static int check_unaligned_access_boot_cpu(void) · line 659

Quoted 7 lines

arch/riscv/kernel/cpufeature.c +4 -0

@@ -653,6 +653,12 @@ static int check_unaligned_access_boot_cpu(void)
 
 arch_initcall(check_unaligned_access_boot_cpu);
 
+void riscv_user_isa_enable(void)
+{
+     if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ))
+             csr_set(CSR_SENVCFG, ENVCFG_CBZE);

It looks like CBZE didn't actually get ratified? The CMO extension says

_The CMO extensions rely on state in {csrname} CSRs that will be defined in a future update to the privileged architecture. If this CSR update is not ratified, the CMO extension will define its own CSRs._

but the privileged spec says

The definition of the CBZE field will be furnished by the forthcoming Zicboz extension. Its allocation within senvcfg may change prior to the ratification of that extension.

Is there some ratified spec that actually defines this?

Quoted 49 lines

arch/riscv/kernel/cpufeature.c +2 -0

+}
+
 #ifdef CONFIG_RISCV_ALTERNATIVE
 /*
  * Alternative patch sites consider 48 bits when determining when to patch

arch/riscv/kernel/setup.c +4 -0

index e600aab116a4..8fd6c02353d4 100644
@@ -26,6 +26,7 @@
 #include <asm/acpi.h>
 #include <asm/alternative.h>
 #include <asm/cacheflush.h>
+#include <asm/cpufeature.h>
 #include <asm/cpu_ops.h>
 #include <asm/early_ioremap.h>
 #include <asm/pgtable.h>

@@ -314,10 +315,13 @@ void __init setup_arch(char **cmdline_p)
      riscv_fill_hwcap();
      init_rt_signal_env();
      apply_boot_alternatives();
+
      if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
          riscv_isa_extension_available(NULL, ZICBOM))
              riscv_noncoherent_supported();
      riscv_set_dma_cache_alignment();
+
+     riscv_user_isa_enable();
 }
 
 static int __init topology_init(void)

arch/riscv/kernel/smpboot.c +2 -0

index 1b8da4e40a4d..d1b0a6fc3adf 100644
@@ -25,6 +25,8 @@
 #include <linux/of.h>
 #include <linux/sched/task_stack.h>
 #include <linux/sched/mm.h>
+
+#include <asm/cpufeature.h>
 #include <asm/cpu_ops.h>
 #include <asm/cpufeature.h>
 #include <asm/irq.h>

@@ -253,6 +255,8 @@ asmlinkage __visible void smp_callin(void)
                      elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
      }
 

arch/riscv/kernel/smpboot.c asmlinkage __visible void smp_callin(void) · line 262

Quoted 5 lines

arch/riscv/kernel/smpboot.c +2 -0

+     riscv_user_isa_enable();
+
      /*
       * Remote TLB flushes are ignored while the CPU is offline, so emit
       * a local TLB flush right now just in case.

Quoted 2 lines · Palmer Dabbelt

On Mon, 18 Sep 2023 06:15:21 PDT (-0700), [email protected] wrote:

Quoted 17 lines

arch/riscv/kernel/cpufeature.c static int check_unaligned_access_boot_cpu(void) · line 659

Quoted 4 lines

arch/riscv/kernel/cpufeature.c +4 -0

+void riscv_user_isa_enable(void)
+{
+     if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ))
+             csr_set(CSR_SENVCFG, ENVCFG_CBZE);

It looks like CBZE didn't actually get ratified? The CMO extension says

_The CMO extensions rely on state in {csrname} CSRs that will be defined in a future update to the privileged architecture. If this CSR update is not ratified, the CMO extension will define its own CSRs._

but the privileged spec says

The definition of the CBZE field will be furnished by the forthcoming Zicboz extension. Its allocation within senvcfg may change prior to the ratification of that extension.

Quoted 1 line

Is there some ratified spec that actually defines this?

I see what you mean. The integration of these bits into the RISC-V priv spec has not happened hence we have the non-normative text in the CMO specification. The bit positions in xenvcfg CSRs can't change because it's already part of ratified CMO specification and there are organizations (like Ventana) who have implemented these bits.

-----Original Message-----
From: linux-riscv <[email protected]> On Behalf Of Andrew Jones
Sent: Monday, September 18, 2023 9:15 PM
To: [email protected]
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Wang, Xiao W <[email protected]>
Subject: [PATCH v4 6/6] RISC-V: selftests: Add CBO tests

Add hwprobe test for Zicboz and its block size. Also, when Zicboz is present, test that cbo.zero may be issued and works. Additionally provide a command line option that enables testing that the Zicbom instructions cause SIGILL and also that cbo.zero causes SIGILL when Zicboz it's not present. The SIGILL tests require "opt-in" with a command line option because the RISC-V ISA does not require unimplemented standard opcodes to issue illegal-instruction exceptions (but hopefully most platforms do).

Pinning the test to a subset of cpus with taskset will also restrict the hwprobe calls to that set.

Signed-off-by Andrew Jones <[email protected]>

---
 .../testing/selftests/riscv/hwprobe/Makefile  |   7 +-
 tools/testing/selftests/riscv/hwprobe/cbo.c   | 228 ++++++++++++++++++
 .../testing/selftests/riscv/hwprobe/hwprobe.c |  12 +-
 .../testing/selftests/riscv/hwprobe/hwprobe.h |  15 ++
 4 files changed, 250 insertions(+), 12 deletions(-)
 create mode 100644 tools/testing/selftests/riscv/hwprobe/cbo.c
 create mode 100644 tools/testing/selftests/riscv/hwprobe/hwprobe.h

tools/testing/selftests/riscv/hwprobe/Makefile +6 -1

index 5f614c3ba598..f224b84591fb 100644
@@ -2,9 +2,14 @@
 # Copyright (C) 2021 ARM Limited
 # Originally tools/testing/arm64/abi/Makefile
 
-TEST_GEN_PROGS := hwprobe
+CFLAGS += -I$(top_srcdir)/tools/include
+
+TEST_GEN_PROGS := hwprobe cbo
 
 include ../../lib.mk
 
 $(OUTPUT)/hwprobe: hwprobe.c sys_hwprobe.S
 	$(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^
+
+$(OUTPUT)/cbo: cbo.c sys_hwprobe.S
+	$(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^

tools/testing/selftests/riscv/hwprobe/cbo.c new file +22 -0

new file mode 100644
index 000000000000..50a2cc8aef38
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023 Ventana Micro Systems Inc.
+ *
+ * Run with 'taskset -c <cpu-list> cbo' to only execute hwprobe on a
+ * subset of cpus, as well as only executing the tests on those cpus.
+ */
+#define _GNU_SOURCE
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <sched.h>
+#include <signal.h>
+#include <assert.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <asm/ucontext.h>
+
+#include "hwprobe.h"
+#include "../../kselftest.h"
+
+#define MK_CBO(fn) cpu_to_le32((fn) << 20 | 10 << 15 | 2 << 12 | 0 << 7 |

15)

tools/testing/selftests/riscv/hwprobe/cbo.c new file +8 -0

+
+static char mem[4096] __aligned(4096) = { [0 ... 4095] = 0xa5 };
+
+static bool illegal_insn;
+
+static void sigill_handler(int sig, siginfo_t *info, void *context)
+{
+	unsigned long *regs = (unsigned long *)&((ucontext_t *)context)-

Quoted 1 line

uc_mcontext;

tools/testing/selftests/riscv/hwprobe/cbo.c new file +66 -0

+	uint32_t insn = *(uint32_t *)regs[0];
+
+	assert(insn == MK_CBO(regs[11]));
+
+	illegal_insn = true;
+	regs[0] += 4;
+}
+
+static void cbo_insn(char *base, int fn)
+{
+	uint32_t insn = MK_CBO(fn);
+
+	asm volatile(
+	"mv	a0, %0\n"
+	"li	a1, %1\n"
+	".4byte	%2\n"
+	: : "r" (base), "i" (fn), "i" (insn) : "a0", "a1", "memory");
+}
+
+static void cbo_inval(char *base) { cbo_insn(base, 0); }
+static void cbo_clean(char *base) { cbo_insn(base, 1); }
+static void cbo_flush(char *base) { cbo_insn(base, 2); }
+static void cbo_zero(char *base)  { cbo_insn(base, 4); }
+
+static void test_no_zicbom(void *arg)
+{
+	ksft_print_msg("Testing Zicbom instructions remain privileged\n");
+
+	illegal_insn = false;
+	cbo_clean(&mem[0]);
+	ksft_test_result(illegal_insn, "No cbo.clean\n");
+
+	illegal_insn = false;
+	cbo_flush(&mem[0]);
+	ksft_test_result(illegal_insn, "No cbo.flush\n");
+
+	illegal_insn = false;
+	cbo_inval(&mem[0]);
+	ksft_test_result(illegal_insn, "No cbo.inval\n");
+}
+
+static void test_no_zicboz(void *arg)
+{
+	ksft_print_msg("No Zicboz, testing cbo.zero remains privileged\n");
+
+	illegal_insn = false;
+	cbo_zero(&mem[0]);
+	ksft_test_result(illegal_insn, "No cbo.zero\n");
+}
+
+static bool is_power_of_2(__u64 n)
+{
+	return n != 0 && (n & (n - 1)) == 0;
+}
+
+static void test_zicboz(void *arg)
+{
+	struct riscv_hwprobe pair = {
+		.key = RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE,
+	};
+	cpu_set_t *cpus = (cpu_set_t *)arg;
+	__u64 block_size;
+	int i, j;
+	long rc;
+
+	rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)cpus,

0);

tools/testing/selftests/riscv/hwprobe/cbo.c new file +2 -0

+	block_size = pair.value;
+	ksft_test_result(rc == 0 && pair.key ==

RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE &&

tools/testing/selftests/riscv/hwprobe/cbo.c new file +26 -0

+			 is_power_of_2(block_size), "Zicboz block size\n");
+	ksft_print_msg("Zicboz block size: %ld\n", block_size);
+
+	illegal_insn = false;
+	cbo_zero(&mem[block_size]);
+	ksft_test_result(!illegal_insn, "cbo.zero\n");
+
+	if (illegal_insn || !is_power_of_2(block_size)) {
+		ksft_test_result_skip("cbo.zero check\n");
+		return;
+	}
+
+	assert(block_size <= 1024);
+
+	for (i = 0; i < 4096 / block_size; ++i) {
+		if (i % 2)
+			cbo_zero(&mem[i * block_size]);
+	}
+
+	for (i = 0; i < 4096 / block_size; ++i) {
+		char expected = i % 2 ? 0x0 : 0xa5;
+
+		for (j = 0; j < block_size; ++j) {
+			if (mem[i * block_size + j] != expected) {
+				ksft_test_result_fail("cbo.zero check\n");
+				ksft_print_msg("cbo.zero check: mem[%d] !=

0x%x\n",

tools/testing/selftests/riscv/hwprobe/cbo.c new file +26 -0

+					       i * block_size + j, expected);
+				return;
+			}
+		}
+	}
+
+	ksft_test_result_pass("cbo.zero check\n");
+}
+
+static void check_no_zicboz_cpus(cpu_set_t *cpus)
+{
+	struct riscv_hwprobe pair = {
+		.key = RISCV_HWPROBE_KEY_IMA_EXT_0,
+	};
+	cpu_set_t one_cpu;
+	int i = 0, c = 0;
+	long rc;
+
+	while (i++ < CPU_COUNT(cpus)) {
+		while (!CPU_ISSET(c, cpus))
+			++c;
+
+		CPU_ZERO(&one_cpu);
+		CPU_SET(c, &one_cpu);
+
+		rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long

*)&one_cpu, 0);

tools/testing/selftests/riscv/hwprobe/cbo.c new file +1 -0

+		assert(rc == 0 && pair.key ==

RISCV_HWPROBE_KEY_IMA_EXT_0);

tools/testing/selftests/riscv/hwprobe/cbo.c new file +3 -0

+
+		if (pair.value & RISCV_HWPROBE_EXT_ZICBOZ)
+			ksft_exit_fail_msg("Zicboz is only present on a subset

of harts.\n"

tools/testing/selftests/riscv/hwprobe/cbo.c new file +1 -0

+					   "Use taskset to select a set of harts

where Zicboz\n"

tools/testing/selftests/riscv/hwprobe/cbo.c new file +1 -0

+					   "presence (present or not) is

consistent for each hart\n");

tools/testing/selftests/riscv/hwprobe/cbo.c new file +46 -0

+		++c;
+	}
+}
+
+enum {
+	TEST_ZICBOZ,
+	TEST_NO_ZICBOZ,
+	TEST_NO_ZICBOM,
+};
+
+static struct test_info {
+	bool enabled;
+	unsigned int nr_tests;
+	void (*test_fn)(void *arg);
+} tests[] = {
+	[TEST_ZICBOZ]		= { .nr_tests = 3, test_zicboz },
+	[TEST_NO_ZICBOZ]	= { .nr_tests = 1, test_no_zicboz },
+	[TEST_NO_ZICBOM]	= { .nr_tests = 3, test_no_zicbom },
+};
+
+int main(int argc, char **argv)
+{
+	struct sigaction act = {
+		.sa_sigaction = &sigill_handler,
+		.sa_flags = SA_SIGINFO,
+	};
+	struct riscv_hwprobe pair;
+	unsigned int plan = 0;
+	cpu_set_t cpus;
+	long rc;
+	int i;
+
+	if (argc > 1 && !strcmp(argv[1], "--sigill")) {
+		rc = sigaction(SIGILL, &act, NULL);
+		assert(rc == 0);
+		tests[TEST_NO_ZICBOZ].enabled = true;
+		tests[TEST_NO_ZICBOM].enabled = true;
+	}
+
+	rc = sched_getaffinity(0, sizeof(cpu_set_t), &cpus);
+	assert(rc == 0);
+
+	ksft_print_header();
+
+	pair.key = RISCV_HWPROBE_KEY_IMA_EXT_0;
+	rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long

*)&cpus, 0);

tools/testing/selftests/riscv/hwprobe/cbo.c new file +26 -0

+	if (rc < 0)
+		ksft_exit_fail_msg("hwprobe() failed with %d\n", rc);
+	assert(rc == 0 && pair.key == RISCV_HWPROBE_KEY_IMA_EXT_0);
+
+	if (pair.value & RISCV_HWPROBE_EXT_ZICBOZ) {
+		tests[TEST_ZICBOZ].enabled = true;
+		tests[TEST_NO_ZICBOZ].enabled = false;
+	} else {
+		check_no_zicboz_cpus(&cpus);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(tests); ++i)
+		plan += tests[i].enabled ? tests[i].nr_tests : 0;
+
+	if (plan == 0)
+		ksft_print_msg("No tests enabled.\n");
+	else
+		ksft_set_plan(plan);
+
+	for (i = 0; i < ARRAY_SIZE(tests); ++i) {
+		if (tests[i].enabled)
+			tests[i].test_fn(&cpus);
+	}
+
+	ksft_finished();
+}

tools/testing/selftests/riscv/hwprobe/hwprobe.c +1 -11

index 4f15f1f3b4c3..c474891df307 100644
@@ -1,17 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
-#include <stddef.h>
-#include <asm/hwprobe.h>
-
+#include "hwprobe.h"
 #include "../../kselftest.h"
 
-/*
- * Rather than relying on having a new enough libc to define this, just do it
- * ourselves.  This way we don't need to be coupled to a new-enough libc to
- * contain the call.
- */
-long riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count,
-		   size_t cpu_count, unsigned long *cpus, unsigned int flags);
-
 int main(int argc, char **argv)
 {
 	struct riscv_hwprobe pairs[8];

tools/testing/selftests/riscv/hwprobe/hwprobe.h new file +15 -1

new file mode 100644
index 000000000000..721b0ce73a56
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef SELFTEST_RISCV_HWPROBE_H
+#define SELFTEST_RISCV_HWPROBE_H
+#include <stddef.h>
+#include <asm/hwprobe.h>
+
+/*
+ * Rather than relying on having a new enough libc to define this, just do it
+ * ourselves.  This way we don't need to be coupled to a new-enough libc to
+ * contain the call.
+ */
+long riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count,
+		   size_t cpu_count, unsigned long *cpus, unsigned int flags);
+
+#endif
--

2.41.0

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