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drm/amdgpu: correct gpu clock counter query on cyan skilfish

PATCH New Lang Yu 2 participants 4 messages Sep 21, 2023

Subsystems (3)
Stable branch DRM drivers Radeon and amdgpu DRM drivers
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Lang Yu

author
#0 lore raw

PATCH 1/1 drm/amdgpu: correct gpu clock counter query on cyan skilfish

Cayn skilfish uses SMUIO v11.0.8 offset.

Signed-off-by Lang Yu <[email protected]>
Cc <[email protected]> # v5.15+
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +21 -0
index 1d671c330475..c16ca611886b 100644
@@ -102,6 +102,11 @@
 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580
 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0
 
+#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
+#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
+#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
+#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1
+
 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026

@@ -7313,6 +7318,22 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
 	uint64_t clock, clock_lo, clock_hi, hi_check;
 
 	switch (adev->ip_versions[GC_HWIP][0]) {
+	case IP_VERSION(10, 1, 3):
+	case IP_VERSION(10, 1, 4):
+		preempt_disable();
+		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
+		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
+		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
+		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
+		 * roughly every 42 seconds.
+		 */
+		if (hi_check != clock_hi) {
+			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
+			clock_hi = hi_check;
+		}
+		preempt_enable();
+		clock = clock_lo | (clock_hi << 32ULL);
+		break;
 	case IP_VERSION(10, 3, 1):
 	case IP_VERSION(10, 3, 3):
 	case IP_VERSION(10, 3, 7):
Signature · 1 line
2.25.1
author
#1 lore raw

PATCH 1/1 drm/amdgpu: correct gpu clock counter query on cyan skilfish

Cayn skilfish uses SMUIO v11.0.8 offset.

Signed-off-by Lang Yu <[email protected]>
Cc <[email protected]> # v5.15+
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +21 -0
index 1d671c330475..c16ca611886b 100644
@@ -102,6 +102,11 @@
 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580
 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0
 
+#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
+#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
+#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
+#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1
+
 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026

@@ -7313,6 +7318,22 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
 	uint64_t clock, clock_lo, clock_hi, hi_check;
 
 	switch (adev->ip_versions[GC_HWIP][0]) {
+	case IP_VERSION(10, 1, 3):
+	case IP_VERSION(10, 1, 4):
+		preempt_disable();
+		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
+		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
+		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
+		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
+		 * roughly every 42 seconds.
+		 */
+		if (hi_check != clock_hi) {
+			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
+			clock_hi = hi_check;
+		}
+		preempt_enable();
+		clock = clock_lo | (clock_hi << 32ULL);
+		break;
 	case IP_VERSION(10, 3, 1):
 	case IP_VERSION(10, 3, 3):
 	case IP_VERSION(10, 3, 7):
Signature · 1 line
2.25.1
author
#2 lore raw

O 09/21/ , Lang Yu wrote:

Sorry for sending this patch twice. Please ignore this one.

Regards,
Lang

Quoted 50 lines

Cayn skilfish uses SMUIO v11.0.8 offset.

Signed-off-by Lang Yu <[email protected]>
Cc <[email protected]> # v5.15+
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +21 -0
index 1d671c330475..c16ca611886b 100644
@@ -102,6 +102,11 @@
 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580
 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0
 
+#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
+#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
+#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
+#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1
+
 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026

@@ -7313,6 +7318,22 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
 	uint64_t clock, clock_lo, clock_hi, hi_check;
 
 	switch (adev->ip_versions[GC_HWIP][0]) {
+	case IP_VERSION(10, 1, 3):
+	case IP_VERSION(10, 1, 4):
+		preempt_disable();
+		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
+		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
+		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
+		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
+		 * roughly every 42 seconds.
+		 */
+		if (hi_check != clock_hi) {
+			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
+			clock_hi = hi_check;
+		}
+		preempt_enable();
+		clock = clock_lo | (clock_hi << 32ULL);
+		break;
 	case IP_VERSION(10, 3, 1):
 	case IP_VERSION(10, 3, 3):
 	case IP_VERSION(10, 3, 7):
Signature · 1 line
2.25.1
Reviewed-by
#3 lore raw

[AMD Official Use Only - General]

Reviewed-by Aaron Liu <[email protected]>
Quoted 75 lines

-----Original Message-----
From: Yu, Lang <[email protected]>
Sent: Thursday, September 21, 2023 2:06 PM
To: [email protected]
Cc: Deucher, Alexander <[email protected]>; Liu, Aaron <[email protected]>; Zhang, Yifan <[email protected]>; [email protected]
Subject: Re: [PATCH] drm/amdgpu: correct gpu clock counter query on cyan skilfish

O 09/21/ , Lang Yu wrote:

Sorry for sending this patch twice. Please ignore this one.

Regards,
Lang

Review

Quoted 9 lines

Cayn skilfish uses SMUIO v11.0.8 offset.

Signed-off-by Lang Yu <[email protected]>
Cc <[email protected]> # v5.15+
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
(quoted diff) +0 -0

b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c line 102

Quoted 5 lines

index 1d671c330475..c16ca611886b 100644

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +0 -0
@@ -102,6 +102,11 @@
 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid

      0x1580

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static uint64_t

Quoted 11 lines
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +5 -0
 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
 
+#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
+#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
+#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
+#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1
+
 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026

@@ -7313,6 +7318,22 @@ static uint64_t

gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)

Quoted 7 lines
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +4 -0
    uint64_t clock, clock_lo, clock_hi, hi_check;
 
    switch (adev->ip_versions[GC_HWIP][0]) {
+   case IP_VERSION(10, 1, 3):
+   case IP_VERSION(10, 1, 4):
+           preempt_disable();
+           clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0,

mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static uint64_t · line 7325

Quoted 1 line
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +1 -0
+           clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0,

mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static uint64_t · line 7326

Quoted 1 line
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +1 -0
+           hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0,

mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static uint64_t · line 7327

Quoted 1 line
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +1 -0
+           /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit

carry over

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)

Quoted 4 lines
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +4 -0
+            * roughly every 42 seconds.
+            */
+           if (hi_check != clock_hi) {
+                   clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0,

mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);

Quoted 11 lines
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +5 -1
+                   clock_hi = hi_check;
+           }
+           preempt_enable();
+           clock = clock_lo | (clock_hi << 32ULL);
+           break;
    case IP_VERSION(10, 3, 1):
    case IP_VERSION(10, 3, 3):
    case IP_VERSION(10, 3, 7):
--

2.25.1