riscv,isa-extensions additions

RFC Superseded Conor Dooley 2 participants 9 messages Sep 21, 2023 – Sep 22, 2023

Subsystems (9)

Device tree bindings RISC-V Arm/RISC-V/Renesas architecture Arm/Allwinner sunXi SoC support +5 more subsystems

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Conor Dooley

author maintainer

2023-09-21 09:57 UTC #0 lore raw

cover riscv,isa-extensions additions

From: Conor Dooley <[email protected]>

I'm suffering from a hw failure on my main dev machine & relegated to a recently acquired & not really configured laptop for a bit, so hopefully nothing with this series goes awry.

I've had two (or more, dunnno) people ask me where the patches for the DTs were swapping them over, so here's what I had before the hw failure. I've marked this RFC as a result & I'd like to come back and revisit these patches once I'm out of this limited environment.

The canaan stuff is absent here, mostly because I don't actually know what to do with it. They don't actually implement the same versions of the F stuff as everyone else (Stefan O'Rear pointed that out to me somewhere recently).

Cheers,
Conor.

CC Rob Herring <[email protected]>

CC Krzysztof Kozlowski <[email protected]>

CC Conor Dooley <[email protected]>

CC Paul Walmsley <[email protected]>

CC Palmer Dabbelt <[email protected]>

CC Albert Ou <[email protected]>

CC Chen-Yu Tsai <[email protected]>

CC Jernej Skrabec <[email protected]>

CC Samuel Holland <[email protected]>

CC Daire McNamara <[email protected]>

CC Geert Uytterhoeven <[email protected]>

CC Magnus Damm <[email protected]>

CC Emil Renner Berthing <[email protected]>

CC Jisheng Zhang <[email protected]>

CC Guo Ren <[email protected]>

CC Fu Wei <[email protected]>

CC [email protected]

Conor Dooley (6):
riscv: dts: microchip: convert isa detection to new properties
riscv: dts: sifive: convert isa detection to new properties
riscv: dts: starfive: convert isa detection to new properties
riscv: dts: renesas: convert isa detection to new properties
riscv: dts: allwinner: convert isa detection to new properties
riscv: dts: thead: convert isa detection to new properties

 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi |  3 +++
 arch/riscv/boot/dts/microchip/mpfs.dtsi       | 15 +++++++++++++++
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi   |  3 +++
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi    | 15 +++++++++++++++
 arch/riscv/boot/dts/sifive/fu740-c000.dtsi    | 15 +++++++++++++++
 arch/riscv/boot/dts/starfive/jh7100.dtsi      |  6 ++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 15 +++++++++++++++
 arch/riscv/boot/dts/thead/th1520.dtsi         | 12 ++++++++++++
 8 files changed, 84 insertions(+)

Signature · 1 line

2.41.0

Conor Dooley

author maintainer

2023-09-21 09:57 UTC #1 lore raw

RFC 1/6 riscv: dts: microchip: convert isa detection to new properties

From: Conor Dooley <[email protected]>

Convert the PolarFire SoC devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

arch/riscv/boot/dts/microchip/mpfs.dtsi +15 -0

index 104504352e99..b1f873d9246c 100644
@@ -22,6 +22,9 @@ cpu0: cpu@0 {
 			i-cache-size = <16384>;
 			reg = <0>;
 			riscv,isa = "rv64imac";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+					       "zihpm";
 			clocks = <&clkcfg CLK_CPU>;
 			status = "disabled";

@@ -48,6 +51,9 @@ cpu1: cpu@1 {
 			mmu-type = "riscv,sv39";
 			reg = <1>;
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;

@@ -76,6 +82,9 @@ cpu2: cpu@2 {
 			mmu-type = "riscv,sv39";
 			reg = <2>;
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;

@@ -104,6 +113,9 @@ cpu3: cpu@3 {
 			mmu-type = "riscv,sv39";
 			reg = <3>;
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;

@@ -132,6 +144,9 @@ cpu4: cpu@4 {
 			mmu-type = "riscv,sv39";
 			reg = <4>;
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;

Signature · 1 line

2.41.0

Chen Wang

2023-09-22 07:33 UTC #2 lore raw

Re: [RFC v1 1/6] riscv: dts: microchip: convert isa detection to new properties

Quoted 16 lines · Conor Dooley

From: Conor Dooley <[email protected]>
Convert the PolarFire SoC devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by Conor Dooley <[email protected]>
---
  arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 +++++++++++++++
  1 file changed, 15 insertions(+)
arch/riscv/boot/dts/microchip/mpfs.dtsi +0 -0
index 104504352e99..b1f873d9246c 100644

arch/riscv/boot/dts/microchip/mpfs.dtsi cpu0: cpu@0 { · line 25

Quoted 4 lines

arch/riscv/boot/dts/microchip/mpfs.dtsi +1 -0

@@ -22,6 +22,9 @@ cpu0: cpu@0 {
  			i-cache-size = <16384>;
  			reg = <0>;
  			riscv,isa = "rv64imac";
+			riscv,base-isa = "rv64i";

should be "isa-base". This applies everywhere.

Quoted 45 lines

arch/riscv/boot/dts/microchip/mpfs.dtsi +14 -0

+			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+					       "zihpm";
  			clocks = <&clkcfg CLK_CPU>;
  			status = "disabled";

@@ -48,6 +51,9 @@ cpu1: cpu@1 {
  			mmu-type = "riscv,sv39";
  			reg = <1>;
  			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
  			clocks = <&clkcfg CLK_CPU>;
  			tlb-split;
  			next-level-cache = <&cctrllr>;

@@ -76,6 +82,9 @@ cpu2: cpu@2 {
  			mmu-type = "riscv,sv39";
  			reg = <2>;
  			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
  			clocks = <&clkcfg CLK_CPU>;
  			tlb-split;
  			next-level-cache = <&cctrllr>;

@@ -104,6 +113,9 @@ cpu3: cpu@3 {
  			mmu-type = "riscv,sv39";
  			reg = <3>;
  			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
  			clocks = <&clkcfg CLK_CPU>;
  			tlb-split;
  			next-level-cache = <&cctrllr>;

@@ -132,6 +144,9 @@ cpu4: cpu@4 {
  			mmu-type = "riscv,sv39";
  			reg = <4>;
  			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
  			clocks = <&clkcfg CLK_CPU>;
  			tlb-split;
  			next-level-cache = <&cctrllr>;

Conor Dooley

author maintainer

2023-09-22 07:38 UTC #3 lore raw

Re: [RFC v1 1/6] riscv: dts: microchip: convert isa detection to new properties

Quoted 5 lines · Chen Wang

Review
Quoted 1 line · Conor Dooley
(quoted diff) +1 -0
+			riscv,base-isa = "rv64i";
should be "isa-base". This applies everywhere.

Yeah, I was expecting exactly something like this to go wrong given the limited environment! Thanks for pointing that out, I'll fix it up when I am back up and running.

Cheers,
Conor.

Conor Dooley

author maintainer

2023-09-21 09:57 UTC #4 lore raw

RFC 2/6 riscv: dts: sifive: convert isa detection to new properties

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

Convert the fu540 and fu740 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++++++++++++++
 arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 15 +++++++++++++++
 2 files changed, 30 insertions(+)

arch/riscv/boot/dts/sifive/fu540-c000.dtsi +15 -0

index 24bba83bec77..a7bd703206b3 100644
@@ -30,6 +30,9 @@ cpu0: cpu@0 {
 			i-cache-size = <16384>;
 			reg = <0>;
 			riscv,isa = "rv64imac";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+					       "zihpm";
 			status = "disabled";
 			cpu0_intc: interrupt-controller {
 				#interrupt-cells = <1>;

@@ -53,6 +56,9 @@ cpu1: cpu@1 {
 			mmu-type = "riscv,sv39";
 			reg = <1>;
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			next-level-cache = <&l2cache>;
 			cpu1_intc: interrupt-controller {

@@ -77,6 +83,9 @@ cpu2: cpu@2 {
 			mmu-type = "riscv,sv39";
 			reg = <2>;
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			next-level-cache = <&l2cache>;
 			cpu2_intc: interrupt-controller {

@@ -101,6 +110,9 @@ cpu3: cpu@3 {
 			mmu-type = "riscv,sv39";
 			reg = <3>;
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			next-level-cache = <&l2cache>;
 			cpu3_intc: interrupt-controller {

@@ -125,6 +137,9 @@ cpu4: cpu@4 {
 			mmu-type = "riscv,sv39";
 			reg = <4>;
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			next-level-cache = <&l2cache>;
 			cpu4_intc: interrupt-controller {

arch/riscv/boot/dts/sifive/fu740-c000.dtsi +15 -0

index 5235fd1c9cb6..06f9c86a6664 100644
@@ -31,6 +31,9 @@ cpu0: cpu@0 {
 			next-level-cache = <&ccache>;
 			reg = <0x0>;
 			riscv,isa = "rv64imac";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+					       "zihpm";
 			status = "disabled";
 			cpu0_intc: interrupt-controller {
 				#interrupt-cells = <1>;

@@ -55,6 +58,9 @@ cpu1: cpu@1 {
 			next-level-cache = <&ccache>;
 			reg = <0x1>;
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			cpu1_intc: interrupt-controller {
 				#interrupt-cells = <1>;

@@ -79,6 +85,9 @@ cpu2: cpu@2 {
 			next-level-cache = <&ccache>;
 			reg = <0x2>;
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			cpu2_intc: interrupt-controller {
 				#interrupt-cells = <1>;

@@ -103,6 +112,9 @@ cpu3: cpu@3 {
 			next-level-cache = <&ccache>;
 			reg = <0x3>;
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			cpu3_intc: interrupt-controller {
 				#interrupt-cells = <1>;

@@ -127,6 +139,9 @@ cpu4: cpu@4 {
 			next-level-cache = <&ccache>;
 			reg = <0x4>;
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			cpu4_intc: interrupt-controller {
 				#interrupt-cells = <1>;

Signature · 1 line

2.41.0

Conor Dooley

author maintainer

2023-09-21 09:57 UTC #5 lore raw

RFC 3/6 riscv: dts: starfive: convert isa detection to new properties

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

Convert the jh7100 and jh7110 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/starfive/jh7100.dtsi |  6 ++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++
 2 files changed, 21 insertions(+)

arch/riscv/boot/dts/starfive/jh7100.dtsi +6 -0

index 35ab54fb235f..d2276357faf7 100644
@@ -33,6 +33,9 @@ U74_0: cpu@0 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 
 			cpu0_intc: interrupt-controller {

@@ -58,6 +61,9 @@ U74_1: cpu@1 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 
 			cpu1_intc: interrupt-controller {

arch/riscv/boot/dts/starfive/jh7110.dtsi +15 -0

index e85464c328d0..991090136bcb 100644
@@ -28,6 +28,9 @@ S7_0: cpu@0 {
 			i-cache-size = <16384>;
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imac_zba_zbb";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			status = "disabled";
 
 			cpu0_intc: interrupt-controller {

@@ -54,6 +57,9 @@ U74_1: cpu@1 {
 			mmu-type = "riscv,sv39";
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+					       "zicsr", "zifencei", "zihpm";
 			tlb-split;
 			operating-points-v2 = <&cpu_opp>;
 			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;

@@ -84,6 +90,9 @@ U74_2: cpu@2 {
 			mmu-type = "riscv,sv39";
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+					       "zicsr", "zifencei", "zihpm";
 			tlb-split;
 			operating-points-v2 = <&cpu_opp>;
 			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;

@@ -114,6 +123,9 @@ U74_3: cpu@3 {
 			mmu-type = "riscv,sv39";
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+					       "zicsr", "zifencei", "zihpm";
 			tlb-split;
 			operating-points-v2 = <&cpu_opp>;
 			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;

@@ -144,6 +156,9 @@ U74_4: cpu@4 {
 			mmu-type = "riscv,sv39";
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+					       "zicsr", "zifencei", "zihpm";
 			tlb-split;
 			operating-points-v2 = <&cpu_opp>;
 			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;

Signature · 1 line

2.41.0

Conor Dooley

author maintainer

2023-09-21 09:57 UTC #6 lore raw

RFC 4/6 riscv: dts: renesas: convert isa detection to new properties

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

Convert the RZ/Five devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 +++
 1 file changed, 3 insertions(+)

arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +3 -0

index 6ec1c6f9a403..10399246dbac 100644
@@ -24,6 +24,9 @@ cpu0: cpu@0 {
 			reg = <0x0>;
 			status = "okay";
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			mmu-type = "riscv,sv39";
 			i-cache-size = <0x8000>;
 			i-cache-line-size = <0x40>;

Signature · 1 line

2.41.0

Conor Dooley

author maintainer

2023-09-21 09:57 UTC #7 lore raw

RFC 5/6 riscv: dts: allwinner: convert isa detection to new properties

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

Convert the D1 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 +++
 1 file changed, 3 insertions(+)

arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +3 -0

index 8275630af977..6b721172390b 100644
@@ -25,6 +25,9 @@ cpu0: cpu@0 {
 			mmu-type = "riscv,sv39";
 			operating-points-v2 = <&opp_table_cpu>;
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			#cooling-cells = <2>;
 
 			cpu0_intc: interrupt-controller {

Signature · 1 line

2.41.0

Conor Dooley

author maintainer

2023-09-21 09:57 UTC #8 lore raw

RFC 6/6 riscv: dts: thead: convert isa detection to new properties

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/riscv/boot/dts/thead/th1520.dtsi +12 -0

index ce708183b6f6..5deac796d1a1 100644
@@ -20,6 +20,9 @@ c910_0: cpu@0 {
 			compatible = "thead,c910", "riscv";
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			reg = <0>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -41,6 +44,9 @@ c910_1: cpu@1 {
 			compatible = "thead,c910", "riscv";
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			reg = <1>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -62,6 +68,9 @@ c910_2: cpu@2 {
 			compatible = "thead,c910", "riscv";
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			reg = <2>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -83,6 +92,9 @@ c910_3: cpu@3 {
 			compatible = "thead,c910", "riscv";
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
+			riscv,base-isa = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			reg = <3>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

Signature · 1 line

2.41.0