Add Anbernic RG-Nano
Subsystems (2)
v6 cover Add Anbernic RG-Nano
From: Chris Morgan <[email protected]>
Add support for the Anbernic RG-Nano handheld gaming device
Changes since V5:
- Removed references to "driver" in comments in device tree.
Changes since V4:
- Rebased off main branch as some patches had been pulled into main.
- Re-enabled the internal RTC based on advice from maintainers.
- Removed "clocks" property from internal RTC based on advice from
- maintainers.
- Gave external RTC alias of rtc0 and internal RTC alias of rtc1 so priority would be given to the external RTC. The external RTC keeps accurate time, while the internal RTC lost 8 hours for me in a 24 hour period.
Changes since V3:
- Added PHY to the OHCI and EHCI nodes. Note that the PHY driver currently forces the PHY to host mode always; a correction to the PHY driver or removal of the phy values from the OHCI and EHCI nodes are necessary to get otg mode working properly.
- Disabled SoC RTC in favor of external clock. The SoC RTC is not set up correctly in hardware and runs fast, whereas the external RTC keeps accurate time. This matches the BSP.
- Added labels to GPIO pins to aid in readability.
Changes since V2:
- Add display support.
- Add USB host support.
- Removed CPU frequency and voltage parameters, as CPU regulator may be tied into additional areas that need further testing.
- Added regulator names back, as they appear to have been accidentally dropped in v2.
- Updated notes to denote all hardware tested and working.
Changes since V1:
- Added additional pwm pin configs to sun8i-v3s.dtsi and removed default config for pwm0 in lieu of defining it for each board.
- Noted in patch notes that additional hardware of UART debug port, USB port (in gadget mode) also work, and that USB host mode does not work.
- Identified GPIO responsible for enabling external speaker amplifier and defined it, allowing onboard audio to work.
- Removed ac_power_supply node.
- Set regulator min and max values to the same value as defined in the schematics.
- Removed definition for reg_ldo1. This regulator is hardware configured so the value did not affect anything, however the driver must be updated to support the correct value of 3.3v in this case.
- Removed usb0_id_det-gpios as I cannot confirm these are correct.
Chris Morgan (4):
arm: dts: sun8i: V3s: Add pinctrl for pwm
ARM: dts: sun8i: v3s: add EHCI and OHCI to v3s dts
dt-bindings: arm: sunxi: add Anbernic RG-Nano
ARM: dts: sunxi: add support for Anbernic RG-Nano
.../devicetree/bindings/arm/sunxi.yaml | 5 + arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 276 ++++++++++++++++++ arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 35 +++ 4 files changed, 317 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Signature · 1 line
2.34.1
PATCH v6 1/4 arm: dts: sun8i: V3s: Add pinctrl for pwm
From: Chris Morgan <[email protected]>
Add pinctrl nodes for pwm0 and pwm1.
--- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +12 -0
@@ -414,6 +414,18 @@ mmc1_pins: mmc1-pins { bias-pull-up; }; + /omit-if-no-ref/ + pwm0_pin: pwm0-pin { + pins = "PB4"; + function = "pwm0"; + }; + + /omit-if-no-ref/ + pwm1_pin: pwm1-pin { + pins = "PB5"; + function = "pwm1"; + }; + spi0_pins: spi0-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0";
Signature · 1 line
2.34.1
PATCH v6 2/4 ARM: dts: sun8i: v3s: add EHCI and OHCI to v3s dts
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
Add the EHCI and OHCI controller to the Allwinner v3s to support using USB in host mode.
--- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+)
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +23 -0
@@ -319,6 +319,29 @@ usbphy: phy@1c19400 { #phy-cells = <1>; }; + ehci: usb@1c1a000 { + compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci: usb@1c1a400 { + compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>;
Signature · 1 line
2.34.1
PATCH v6 3/4 dt-bindings: arm: sunxi: add Anbernic RG-Nano
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a portable handheld console from Anbernic which uses the Allwinner V3s SoC.
--- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+)
Documentation/devicetree/bindings/arm/sunxi.yaml +5 -0
@@ -51,6 +51,11 @@ properties: - const: allwinner,parrot - const: allwinner,sun8i-a33 + - description: Anbernic RG-Nano + items: + - const: anbernic,rg-nano + - const: allwinner,sun8i-v3s + - description: Amarula A64 Relic items: - const: amarula,a64-relic
Signature · 1 line
2.34.1
PATCH v6 4/4 ARM: dts: sunxi: add support for Anbernic RG-Nano
In reply to Chris MorganFrom: Chris Morgan <[email protected]>
The Anbernic RG-Nano is a small portable game device based on the Allwinner V3s SoC. It has GPIO buttons on the face and side for input, a single mono speaker, a 240x240 SPI controlled display, a USB-C OTG port, an SD card slot for booting, and 64MB of RAM included in the SoC. There does not appear to be a crystal feeding the internal RTC so it does not keep proper time (for me it ran 8 hours slow in a 24 hour period). External RTC works just fine.
Working/Tested:
- SDMMC
- UART (for debugging)
- Buttons
- Charging/battery/PMIC
- Speaker
- RTC (external RTC)
- USB
- Display
--- arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 276 ++++++++++++++++++ 2 files changed, 277 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
arch/arm/boot/dts/allwinner/Makefile +1 -0
@@ -256,6 +256,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-anbernic-rg-nano.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtb
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file +276 -0
276 lines not on this page · raw message
Signature · 1 line
2.34.1
Dne petek, 29. september 2023 ob 16:44:37 CEST je Chris Morgan napisal(a):
Quoted 58 lines
From: Chris Morgan <[email protected]>
Add support for the Anbernic RG-Nano handheld gaming device
Changes since V5:
- Removed references to "driver" in comments in device tree.Changes since V4:
- Rebased off main branch as some patches had been pulled into main.
- Re-enabled the internal RTC based on advice from maintainers.
- Removed "clocks" property from internal RTC based on advice from
- maintainers.
- Gave external RTC alias of rtc0 and internal RTC alias of rtc1 so priority would be given to the external RTC. The external RTC keeps accurate time, while the internal RTC lost 8 hours for me in a 24 hour period.Changes since V3:
- Added PHY to the OHCI and EHCI nodes. Note that the PHY driver currently forces the PHY to host mode always; a correction to the PHY driver or removal of the phy values from the OHCI and EHCI nodes are necessary to get otg mode working properly.
- Disabled SoC RTC in favor of external clock. The SoC RTC is not set up correctly in hardware and runs fast, whereas the external RTC keeps accurate time. This matches the BSP.
- Added labels to GPIO pins to aid in readability.Changes since V2:
- Add display support.
- Add USB host support.
- Removed CPU frequency and voltage parameters, as CPU regulator may be tied into additional areas that need further testing.
- Added regulator names back, as they appear to have been accidentally dropped in v2.
- Updated notes to denote all hardware tested and working.Changes since V1:
- Added additional pwm pin configs tosun8i-v3s.dtsiand removed default config for pwm0 in lieu of defining it for each board.
- Noted in patch notes that additional hardware of UART debug port, USB port (in gadget mode) also work, and that USB host mode does not work.
- Identified GPIO responsible for enabling external speaker amplifier and defined it, allowing onboard audio to work.
- Removedac_power_supplynode.
- Set regulator min and max values to the same value as defined in the schematics.
- Removed definition forreg_ldo1. This regulator is hardware configured so the value did not affect anything, however the driver must be updated to support the correct value of 3.3v in this case.
- Removed usb0_id_det-gpios as I cannot confirm these are correct.Chris Morgan (4):
arm: dts: sun8i: V3s: Add pinctrl for pwm
ARM: dts: sun8i: v3s: add EHCI and OHCI to v3s dts
dt-bindings: arm: sunxi: add Anbernic RG-Nano
ARM: dts: sunxi: add support for Anbernic RG-Nano
Quoted 7 lines
.../devicetree/bindings/arm/sunxi.yaml | 5 + arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-v3s-anbernic-rg-nano.dts | 276 ++++++++++++++++++ arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 35 +++ 4 files changed, 317 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts
Applied, thanks!
Best regards,
Jernej