arm64: dts: qcom: ipq5018: add QUP1 SPI controller

PATCH In review Robert Marko 3 participants 5 messages Oct 4, 2023 – Oct 16, 2023

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Robert Marko

author

2023-10-04 19:13 UTC #0 lore raw

PATCH 1/1 arm64: dts: qcom: ipq5018: add QUP1 SPI controller

Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018.

Signed-off-by Robert Marko <[email protected]>

---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

arch/arm64/boot/dts/qcom/ipq5018.dtsi +24 -0

index 38ffdc3cbdcd..484034e65f4f 100644
@@ -146,6 +146,16 @@ sdhc_1: mmc@7804000 {
 			status = "disabled";
 		};
 
+		blsp_dma: dma-controller@7884000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07884000 0x1d000>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+		};
+
 		blsp1_uart1: serial@78af000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x078af000 0x200>;

@@ -156,6 +166,20 @@ blsp1_uart1: serial@78af000 {
 			status = "disabled";
 		};
 
+		blsp1_spi1: spi@78b5000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x78b5000 0x600>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
 		intc: interrupt-controller@b000000 {
 			compatible = "qcom,msm-qgic2";
 			reg = <0x0b000000 0x1000>,  /* GICD */

Signature · 1 line

2.41.0

Kathiravan Thirumoorthy

Reviewed-by on v1 1/1

2023-10-05 13:49 UTC #1 lore raw

Quoted 29 lines · Robert Marko

Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018.

Signed-off-by Robert Marko <[email protected]>

---
  arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++
  1 file changed, 24 insertions(+)

arch/arm64/boot/dts/qcom/ipq5018.dtsi +10 -0

index 38ffdc3cbdcd..484034e65f4f 100644
@@ -146,6 +146,16 @@ sdhc_1: mmc@7804000 {
  			status = "disabled";
  		};
 
+		blsp_dma: dma-controller@7884000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07884000 0x1d000>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+		};
+
  		blsp1_uart1: serial@78af000 {
  			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  			reg = <0x078af000 0x200>;

arch/arm64/boot/dts/qcom/ipq5018.dtsi blsp1_uart1: serial@78af000 { · line 173

Quoted 8 lines

arch/arm64/boot/dts/qcom/ipq5018.dtsi +5 -0

@@ -156,6 +166,20 @@ blsp1_uart1: serial@78af000 {
  			status = "disabled";
  		};
 
+		blsp1_spi1: spi@78b5000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x78b5000 0x600>;

Please pad the address part to 8 hex digits with leading zeroes. With that,

Reviewed-by Kathiravan T <[email protected]>

Quoted 12 lines

arch/arm64/boot/dts/qcom/ipq5018.dtsi +9 -0

+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
  		intc: interrupt-controller@b000000 {
  			compatible = "qcom,msm-qgic2";
  			reg = <0x0b000000 0x1000>,  /* GICD */

Kathiravan Thirumoorthy

Reviewed-by

2023-10-05 13:56 UTC #2 lore raw

Quoted 41 lines · Kathiravan Thirumoorthy

Quoted 28 lines · Robert Marko

Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018.

Signed-off-by Robert Marko <[email protected]>

---
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++

  1 file changed, 24 insertions(+)

arch/arm64/boot/dts/qcom/ipq5018.dtsi +9 -0

index 38ffdc3cbdcd..484034e65f4f 100644
@@ -146,6 +146,16 @@ sdhc_1: mmc@7804000 {
               status = "disabled";
           };
   +        blsp_dma: dma-controller@7884000 {
+            compatible = "qcom,bam-v1.7.0";
+            reg = <0x07884000 0x1d000>;
+            interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+            clock-names = "bam_clk";
+            #dma-cells = <1>;
+            qcom,ee = <0>;
+        };
+
           blsp1_uart1: serial@78af000 {
               compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
               reg = <0x078af000 0x200>;

arch/arm64/boot/dts/qcom/ipq5018.dtsi blsp1_uart1: serial@78af000 { · line 172

Quoted 7 lines

arch/arm64/boot/dts/qcom/ipq5018.dtsi +4 -0

@@ -156,6 +166,20 @@ blsp1_uart1: serial@78af000 {
               status = "disabled";
           };
   +        blsp1_spi1: spi@78b5000 {
+            compatible = "qcom,spi-qup-v2.2.1";
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <0x78b5000 0x600>;

Please pad the address part to 8 hex digits with leading zeroes. With that,

Quoted 1 line

Reviewed-by Kathiravan T <[email protected]>

Once again, missed to spell out last name...

Reviewed-by Kathiravan Thirumoorthy <[email protected]>

Quoted 14 lines

arch/arm64/boot/dts/qcom/ipq5018.dtsi +9 -0

+            interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+                 <&gcc GCC_BLSP1_AHB_CLK>;
+            clock-names = "core", "iface";
+            dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+            dma-names = "tx", "rx";
+            status = "disabled";
+        };
+
           intc: interrupt-controller@b000000 {
               compatible = "qcom,msm-qgic2";

reg = <0x0b000000 0x1000>, /* GICD */

Bjorn Andersson

maintainer

2023-10-16 18:54 UTC #3 lore raw

In reply to Robert Marko

Quoted 3 lines · Robert Marko

Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018.
Signed-off-by Robert Marko <[email protected]>

I padded the spi node to 8 digits, and applied the patch.

Thanks,
Bjorn

Quoted 49 lines

---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

arch/arm64/boot/dts/qcom/ipq5018.dtsi +24 -0

index 38ffdc3cbdcd..484034e65f4f 100644
@@ -146,6 +146,16 @@ sdhc_1: mmc@7804000 {
 			status = "disabled";
 		};
 
+		blsp_dma: dma-controller@7884000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07884000 0x1d000>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+		};
+
 		blsp1_uart1: serial@78af000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x078af000 0x200>;

@@ -156,6 +166,20 @@ blsp1_uart1: serial@78af000 {
 			status = "disabled";
 		};
 
+		blsp1_spi1: spi@78b5000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x78b5000 0x600>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
 		intc: interrupt-controller@b000000 {
 			compatible = "qcom,msm-qgic2";
 			reg = <0x0b000000 0x1000>,  /* GICD */

Signature · 1 line

2.41.0

Robert Marko

author

2023-10-16 19:53 UTC #4 lore raw

Quoted 7 lines · Bjorn Andersson

Quoted 3 lines · Robert Marko
Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018.
Signed-off-by Robert Marko <[email protected]>
I padded the spi node to 8 digits, and applied the patch.

Thank you for this, it was in my TODO but that is quite long.

Regards,
Robert

Quoted 53 lines

Thanks,
Bjorn

Quoted 49 lines

---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

arch/arm64/boot/dts/qcom/ipq5018.dtsi +24 -1

index 38ffdc3cbdcd..484034e65f4f 100644
@@ -146,6 +146,16 @@ sdhc_1: mmc@7804000 {
                      status = "disabled";
              };
 
+             blsp_dma: dma-controller@7884000 {
+                     compatible = "qcom,bam-v1.7.0";
+                     reg = <0x07884000 0x1d000>;
+                     interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+                     clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+                     clock-names = "bam_clk";
+                     #dma-cells = <1>;
+                     qcom,ee = <0>;
+             };
+
              blsp1_uart1: serial@78af000 {
                      compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
                      reg = <0x078af000 0x200>;

@@ -156,6 +166,20 @@ blsp1_uart1: serial@78af000 {
                      status = "disabled";
              };
 
+             blsp1_spi1: spi@78b5000 {
+                     compatible = "qcom,spi-qup-v2.2.1";
+                     #address-cells = <1>;
+                     #size-cells = <0>;
+                     reg = <0x78b5000 0x600>;
+                     interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                     clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+                              <&gcc GCC_BLSP1_AHB_CLK>;
+                     clock-names = "core", "iface";
+                     dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+                     dma-names = "tx", "rx";
+                     status = "disabled";
+             };
+
              intc: interrupt-controller@b000000 {
                      compatible = "qcom,msm-qgic2";
                      reg = <0x0b000000 0x1000>,  /* GICD */
--

2.41.0