dt-bindings: clock: qcom: ipq6018: add USB GDSCs

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

---

Quoted 6 lines · Robert Marko

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

---

Applying patches 1 and 3 without this one breaks usb, no?

Quoted 10 lines · Konrad Dybcio

Quoted 6 lines · Robert Marko

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

---

Applying patches 1 and 3 without this one breaks usb, no?

Sorry, my hands don't keep up with my brain - that's almost another speculative execution vulnerability!

What I meant to say is:

applying patches 1 and 2 breaks USB

but

the solution here would be to apply patch 1 and patch 3, followed by patch 2 (unless it will make the USB defer, IDK, it's probably easier to just test than to dive deep into the code)

with Bjorn taking both subsystems, we can make that work I think

Konrad

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

---
 drivers/clk/qcom/Kconfig       |  1 +
 drivers/clk/qcom/gcc-ipq6018.c | 33 ++++++++++++++++++++++++---------
 2 files changed, 25 insertions(+), 9 deletions(-)

drivers/clk/qcom/Kconfig +1 -0

index ad1acd9b7426b..2aefa2231b51b 100644
@@ -164,6 +164,7 @@ config IPQ_GCC_5332
 
 config IPQ_GCC_6018
        tristate "IPQ6018 Global Clock Controller"
+       select QCOM_GDSC
        help
          Support for global clock controller on ipq6018 devices.
          Say Y if you want to use peripheral devices such as UART, SPI,

drivers/clk/qcom/gcc-ipq6018.c +24 -10

index cc20a16d8973c..9d5ee2ac012a1 100644
@@ -23,6 +23,7 @@
 #include "clk-alpha-pll.h"
 #include "clk-regmap-divider.h"
 #include "clk-regmap-mux.h"
+#include "gdsc.h"
 #include "reset.h"
 
 enum {

@@ -4691,6 +4692,22 @@ static struct clk_branch gcc_dcc_clk = {
        },
 };
 
+static struct gdsc usb0_gdsc = {
+       .gdscr = 0x3e078,
+       .pd = {
+               .name = "usb0_gdsc",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc usb1_gdsc = {
+       .gdscr = 0x3f078,
+       .pd = {
+               .name = "usb1_gdsc",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+};
+
 static const struct alpha_pll_config ubi32_pll_config = {
        .l = 0x3e,
        .alpha = 0x6667,

@@ -5138,6 +5155,11 @@ static const struct qcom_reset_map gcc_ipq6018_resets[] = {
        [GCC_Q6_AXIM_ARES] = {0x59110, 4},
 };
 
+static struct gdsc *gcc_ipq6018_gdscs[] = {
+       [USB0_GDSC] = &usb0_gdsc,
+       [USB1_GDSC] = &usb1_gdsc,
+};
+
 static const struct of_device_id gcc_ipq6018_match_table[] = {
        { .compatible = "qcom,gcc-ipq6018" },
        { }

@@ -5160,6 +5182,8 @@ static const struct qcom_cc_desc gcc_ipq6018_desc = {
        .num_resets = ARRAY_SIZE(gcc_ipq6018_resets),
        .clk_hws = gcc_ipq6018_hws,
        .num_clk_hws = ARRAY_SIZE(gcc_ipq6018_hws),
+       .gdscs = gcc_ipq6018_gdscs,
+       .num_gdscs = ARRAY_SIZE(gcc_ipq6018_gdscs),
 };
 
 static int gcc_ipq6018_probe(struct platform_device *pdev)

@@ -5170,15 +5194,6 @@ static int gcc_ipq6018_probe(struct platform_device *pdev)
        if (IS_ERR(regmap))
                return PTR_ERR(regmap);
 
-       /* Disable SW_COLLAPSE for USB0 GDSCR */
-       regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
-       /* Enable SW_OVERRIDE for USB0 GDSCR */
-       regmap_update_bits(regmap, 0x3e078, BIT(2), BIT(2));
-       /* Disable SW_COLLAPSE for USB1 GDSCR */
-       regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
-       /* Enable SW_OVERRIDE for USB1 GDSCR */
-       regmap_update_bits(regmap, 0x3f078, BIT(2), BIT(2));
-
        /* SW Workaround for UBI Huyara PLL */
        regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
 
--

2.41.0

Quoted 6 lines · Robert Marko

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

Unfortunately, after testing on multiple devices I hit the same GDSC issue I had a long time ago
that was the reason I did not send this upstream.
It seems that USB3 port GDSC (USB0 GDSC in code) works just fine, however the USB2 one
(USB1 GDSC in code) it is stuck off and USB2 port will fail due to this:

    1.607531] ------------[ cut here ]------------
[    1.607559] usb1_gdsc status stuck at 'off'
[    1.607592] WARNING: CPU: 0 PID: 35 at gdsc_toggle_logic+0x16c/0x174
[    1.615120] Modules linked in:

Quoted 14 lines · Robert Marko

Quoted 6 lines · Robert Marko

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

Unfortunately, after testing on multiple devices I hit the same GDSC issue I had a long time ago
that was the reason I did not send this upstream.
It seems that USB3 port GDSC (USB0 GDSC in code) works just fine, however the USB2 one
(USB1 GDSC in code) it is stuck off and USB2 port will fail due to this:

Quoted 4 lines

    1.607531] ------------[ cut here ]------------
[    1.607559] usb1_gdsc status stuck at 'off'
[    1.607592] WARNING: CPU: 0 PID: 35 at gdsc_toggle_logic+0x16c/0x174
[    1.615120] Modules linked in:

Can you dump GDSCR (the entire 32-bit register) at boot and when toggling?

Konrad

Quoted 20 lines · Konrad Dybcio

Quoted 14 lines · Robert Marko

Quoted 6 lines · Robert Marko

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

Unfortunately, after testing on multiple devices I hit the same GDSC issue I had a long time ago
that was the reason I did not send this upstream.
It seems that USB3 port GDSC (USB0 GDSC in code) works just fine, however the USB2 one
(USB1 GDSC in code) it is stuck off and USB2 port will fail due to this:

Quoted 4 lines

    1.607531] ------------[ cut here ]------------
[    1.607559] usb1_gdsc status stuck at 'off'
[    1.607592] WARNING: CPU: 0 PID: 35 at gdsc_toggle_logic+0x16c/0x174
[    1.615120] Modules linked in:

Quoted 1 line

Can you dump GDSCR (the entire 32-bit register) at boot and when toggling?

Sure, here it is:

[    0.023760] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val: 0x8222004 init
[    0.023782] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val: 0x8222004 init
[    0.988626] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 before toggle
[    1.202506] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 after toggle
[    1.207208] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val:

0xa0282000 before toggle

Quoted 24 lines · Robert Marko

Quoted 20 lines · Konrad Dybcio

Quoted 14 lines · Robert Marko

Quoted 6 lines · Robert Marko

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

Unfortunately, after testing on multiple devices I hit the same GDSC issue I had a long time ago
that was the reason I did not send this upstream.
It seems that USB3 port GDSC (USB0 GDSC in code) works just fine, however the USB2 one
(USB1 GDSC in code) it is stuck off and USB2 port will fail due to this:

Quoted 4 lines

    1.607531] ------------[ cut here ]------------
[    1.607559] usb1_gdsc status stuck at 'off'
[    1.607592] WARNING: CPU: 0 PID: 35 at gdsc_toggle_logic+0x16c/0x174
[    1.615120] Modules linked in:

Quoted 1 line

Can you dump GDSCR (the entire 32-bit register) at boot and when toggling?

Sure, here it is:

Quoted 8 lines

[    0.023760] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val: 0x8222004 init
[    0.023782] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val: 0x8222004 init
[    0.988626] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 before toggle
[    1.202506] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 after toggle
[    1.207208] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val:

0xa0282000 before toggle

Any chance

.en_few_wait_val = 0x2

(turning BIT(19) into BIT(17))

will make a difference?

Konrad

Quoted 36 lines · Konrad Dybcio

Quoted 24 lines · Robert Marko

Quoted 20 lines · Konrad Dybcio

Quoted 14 lines · Robert Marko

Quoted 6 lines · Robert Marko

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

Unfortunately, after testing on multiple devices I hit the same GDSC issue I had a long time ago
that was the reason I did not send this upstream.
It seems that USB3 port GDSC (USB0 GDSC in code) works just fine, however the USB2 one
(USB1 GDSC in code) it is stuck off and USB2 port will fail due to this:

Quoted 4 lines

     1.607531] ------------[ cut here ]------------
[    1.607559] usb1_gdsc status stuck at 'off'
[    1.607592] WARNING: CPU: 0 PID: 35 at gdsc_toggle_logic+0x16c/0x174
[    1.615120] Modules linked in:

Quoted 1 line

Can you dump GDSCR (the entire 32-bit register) at boot and when toggling?

Sure, here it is:

Quoted 8 lines

[    0.023760] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val: 0x8222004 init
[    0.023782] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val: 0x8222004 init
[    0.988626] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 before toggle
[    1.202506] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 after toggle
[    1.207208] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val:

0xa0282000 before toggle

Any chance

Quoted 5 lines

.en_few_wait_val = 0x2

(turning BIT(19) into BIT(17))

will make a difference?

Sadly, it makes no difference and GDSC status bit newer comes up which is rather weird as USB0 one seems to work just fine.

Quoted 39 lines · Robert Marko

Quoted 38 lines · Konrad Dybcio

Quoted 24 lines · Robert Marko

Quoted 20 lines · Konrad Dybcio

Quoted 14 lines · Robert Marko

Quoted 6 lines · Robert Marko

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

Unfortunately, after testing on multiple devices I hit the same GDSC issue I had a long time ago
that was the reason I did not send this upstream.
It seems that USB3 port GDSC (USB0 GDSC in code) works just fine, however the USB2 one
(USB1 GDSC in code) it is stuck off and USB2 port will fail due to this:

Quoted 4 lines

     1.607531] ------------[ cut here ]------------
[    1.607559] usb1_gdsc status stuck at 'off'
[    1.607592] WARNING: CPU: 0 PID: 35 at gdsc_toggle_logic+0x16c/0x174
[    1.615120] Modules linked in:

Quoted 1 line

Can you dump GDSCR (the entire 32-bit register) at boot and when toggling?

Sure, here it is:

Quoted 8 lines

[    0.023760] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val: 0x8222004 init
[    0.023782] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val: 0x8222004 init
[    0.988626] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 before toggle
[    1.202506] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 after toggle
[    1.207208] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val:

0xa0282000 before toggle

Any chance

.en_few_wait_val = 0x2

Quoted 6 lines

Quoted 3 lines

(turning BIT(19) into BIT(17))

will make a difference?

Sadly, it makes no difference and GDSC status bit newer comes up which is rather weird as USB0 one seems to work just fine.

What if you add clk_ignore_unused?

Konrad

Quoted 45 lines · Konrad Dybcio

Quoted 41 lines · Robert Marko

Quoted 40 lines · Konrad Dybcio

Quoted 24 lines · Robert Marko

Quoted 20 lines · Konrad Dybcio

Quoted 14 lines · Robert Marko

Quoted 6 lines · Robert Marko

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

Unfortunately, after testing on multiple devices I hit the same GDSC issue I had a long time ago
that was the reason I did not send this upstream.
It seems that USB3 port GDSC (USB0 GDSC in code) works just fine, however the USB2 one
(USB1 GDSC in code) it is stuck off and USB2 port will fail due to this:

Quoted 4 lines

     1.607531] ------------[ cut here ]------------
[    1.607559] usb1_gdsc status stuck at 'off'
[    1.607592] WARNING: CPU: 0 PID: 35 at gdsc_toggle_logic+0x16c/0x174
[    1.615120] Modules linked in:

Quoted 1 line

Can you dump GDSCR (the entire 32-bit register) at boot and when toggling?

Sure, here it is:

Quoted 8 lines

[    0.023760] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val: 0x8222004 init
[    0.023782] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val: 0x8222004 init
[    0.988626] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 before toggle
[    1.202506] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 after toggle
[    1.207208] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val:

0xa0282000 before toggle

Any chance

.en_few_wait_val = 0x2

(turning BIT(19) into BIT(17))

Quoted 5 lines

Quoted 4 lines

Quoted 1 line

will make a difference?

Sadly, it makes no difference and GDSC status bit newer comes up which is rather weird as USB0 one seems to work just fine.

What if you add clk_ignore_unused?

To the USB1 master clock or?

There is definitively something broken regarding the GDSC as GDSC_STATE bits (30-27)
change from 0 to something on the USB0 GDSC but on GDSC1 they are 0 even after SW_OVERRIDE BIT(2) is set to 1, and the POWER BIT(31) newer changes to 1.

However, if you manually set BIT(2) to 1 then the USB1 master clock can come up so
GDSC seems to work.
USB1 (The USB2.0 HS) port is still broken after this if USB mass storage is used but that was present before the GDSC changes as well and I still need to figure out
which quirk is missing for this.

Quoted 46 lines · Robert Marko

Quoted 45 lines · Konrad Dybcio

Quoted 41 lines · Robert Marko

Quoted 40 lines · Konrad Dybcio

Quoted 24 lines · Robert Marko

Quoted 20 lines · Konrad Dybcio

Quoted 14 lines · Robert Marko

Quoted 6 lines · Robert Marko

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

Unfortunately, after testing on multiple devices I hit the same GDSC issue I had a long time ago
that was the reason I did not send this upstream.
It seems that USB3 port GDSC (USB0 GDSC in code) works just fine, however the USB2 one
(USB1 GDSC in code) it is stuck off and USB2 port will fail due to this:

Quoted 4 lines

     1.607531] ------------[ cut here ]------------
[    1.607559] usb1_gdsc status stuck at 'off'
[    1.607592] WARNING: CPU: 0 PID: 35 at gdsc_toggle_logic+0x16c/0x174
[    1.615120] Modules linked in:

Quoted 1 line

Can you dump GDSCR (the entire 32-bit register) at boot and when toggling?

Sure, here it is:

Quoted 8 lines

[    0.023760] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val: 0x8222004 init
[    0.023782] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val: 0x8222004 init
[    0.988626] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 before toggle
[    1.202506] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 after toggle
[    1.207208] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val:

0xa0282000 before toggle

Any chance

.en_few_wait_val = 0x2

(turning BIT(19) into BIT(17))

Quoted 7 lines

Quoted 5 lines

Quoted 4 lines

Quoted 1 line

will make a difference?

Sadly, it makes no difference and GDSC status bit newer comes up which is rather weird as USB0 one seems to work just fine.

What if you add clk_ignore_unused?

To the USB1 master clock or?

That's a command line parameter, effectively setting it on all clks.

Quoted 7 lines

There is definitively something broken regarding the GDSC as GDSC_STATE bits (30-27)
change from 0 to something on the USB0 GDSC but on GDSC1 they are 0 even after SW_OVERRIDE BIT(2) is set to 1, and the POWER BIT(31) newer changes to 1.

Quoted 7 lines

However, if you manually set BIT(2) to 1 then the USB1 master clock can come up so
GDSC seems to work.
USB1 (The USB2.0 HS) port is still broken after this if USB mass storage is used but that was present before the GDSC changes as well and I still need to figure out
which quirk is missing for this.

Please try clk_ignore_unused and see if toggling the GDSC is still broken.

Konrad

Quoted 48 lines · Konrad Dybcio

Quoted 46 lines · Robert Marko

Quoted 45 lines · Konrad Dybcio

Quoted 41 lines · Robert Marko

Quoted 40 lines · Konrad Dybcio

Quoted 24 lines · Robert Marko

Quoted 20 lines · Konrad Dybcio

Quoted 14 lines · Robert Marko

Quoted 6 lines · Robert Marko

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

Unfortunately, after testing on multiple devices I hit the same GDSC issue I had a long time ago
that was the reason I did not send this upstream.
It seems that USB3 port GDSC (USB0 GDSC in code) works just fine, however the USB2 one
(USB1 GDSC in code) it is stuck off and USB2 port will fail due to this:

Quoted 4 lines

      1.607531] ------------[ cut here ]------------
[    1.607559] usb1_gdsc status stuck at 'off'
[    1.607592] WARNING: CPU: 0 PID: 35 at gdsc_toggle_logic+0x16c/0x174
[    1.615120] Modules linked in:

Quoted 1 line

Can you dump GDSCR (the entire 32-bit register) at boot and when toggling?

Sure, here it is:

Quoted 8 lines

[    0.023760] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val: 0x8222004 init
[    0.023782] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val: 0x8222004 init
[    0.988626] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 before toggle
[    1.202506] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 after toggle
[    1.207208] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val:

0xa0282000 before toggle

Any chance

.en_few_wait_val = 0x2

(turning BIT(19) into BIT(17))

Quoted 8 lines

Quoted 7 lines

Quoted 5 lines

Quoted 4 lines

Quoted 1 line

will make a difference?

Sadly, it makes no difference and GDSC status bit newer comes up which is rather weird as USB0 one seems to work just fine.

What if you add clk_ignore_unused?

To the USB1 master clock or?

That's a command line parameter, effectively setting it on all clks.

Oh that, I understand now.

Quoted 14 lines

Quoted 14 lines

There is definitively something broken regarding the GDSC as GDSC_STATE bits (30-27)
change from 0 to something on the USB0 GDSC but on GDSC1 they are 0 even after SW_OVERRIDE BIT(2) is set to 1, and the POWER BIT(31) newer changes to 1.

However, if you manually set BIT(2) to 1 then the USB1 master clock can come up so
GDSC seems to work.
USB1 (The USB2.0 HS) port is still broken after this if USB mass storage is used but that was present before the GDSC changes as well and I still need to figure out
which quirk is missing for this.

Quoted 1 line

Please try clk_ignore_unused and see if toggling the GDSC is still broken.

Sadly, passing clk_ignore_unused in the bootargs doesn't help, GDSC is still stuck off.

Quoted 76 lines · Robert Marko

Quoted 48 lines · Konrad Dybcio

Quoted 46 lines · Robert Marko

Quoted 45 lines · Konrad Dybcio

Quoted 41 lines · Robert Marko

Quoted 40 lines · Konrad Dybcio

Quoted 24 lines · Robert Marko

Quoted 20 lines · Konrad Dybcio

Quoted 14 lines · Robert Marko

Quoted 6 lines · Robert Marko

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

Unfortunately, after testing on multiple devices I hit the same GDSC issue I had a long time ago
that was the reason I did not send this upstream.
It seems that USB3 port GDSC (USB0 GDSC in code) works just fine, however the USB2 one
(USB1 GDSC in code) it is stuck off and USB2 port will fail due to this:

Quoted 4 lines

      1.607531] ------------[ cut here ]------------
[    1.607559] usb1_gdsc status stuck at 'off'
[    1.607592] WARNING: CPU: 0 PID: 35 at gdsc_toggle_logic+0x16c/0x174
[    1.615120] Modules linked in:

Quoted 1 line

Can you dump GDSCR (the entire 32-bit register) at boot and when toggling?

Sure, here it is:

Quoted 8 lines

[    0.023760] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val: 0x8222004 init
[    0.023782] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val: 0x8222004 init
[    0.988626] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 before toggle
[    1.202506] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val:
0x8282000 after toggle
[    1.207208] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val:

0xa0282000 before toggle

Any chance

.en_few_wait_val = 0x2

(turning BIT(19) into BIT(17))

Quoted 8 lines

Quoted 7 lines

Quoted 5 lines

Quoted 4 lines

Quoted 1 line

will make a difference?

Sadly, it makes no difference and GDSC status bit newer comes up which is rather weird as USB0 one seems to work just fine.

What if you add clk_ignore_unused?

To the USB1 master clock or?

That's a command line parameter, effectively setting it on all clks.

Oh that, I understand now.

Quoted 15 lines

Quoted 7 lines

There is definitively something broken regarding the GDSC as GDSC_STATE bits (30-27)
change from 0 to something on the USB0 GDSC but on GDSC1 they are 0 even after SW_OVERRIDE BIT(2) is set to 1, and the POWER BIT(31) newer changes to 1.

Quoted 7 lines

However, if you manually set BIT(2) to 1 then the USB1 master clock can come up so
GDSC seems to work.
USB1 (The USB2.0 HS) port is still broken after this if USB mass storage is used but that was present before the GDSC changes as well and I still need to figure out
which quirk is missing for this.

Please try clk_ignore_unused and see if toggling the GDSC is still broken.

Quoted 2 lines

Sadly, passing clk_ignore_unused in the bootargs doesn't help, GDSC is still stuck off.

Hm, so it looks like there's no clock dependency for this GDSC..

Maybe some regulator needs to be turned on?

Can you try to add regulator-always-on to all vregs and retry? (and keep clk_ignore_unused to be sure)

Konrad

Quoted 6 lines · Robert Marko

IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such and drop the curent code that is de-asserting the USB GDSC-s as part of the GCC probe.

Signed-off-by Robert Marko <[email protected]>

Unfortunately, after testing on multiple devices I hit the same GDSC issue I had a long time ago
that was the reason I did not send this upstream.
It seems that USB3 port GDSC (USB0 GDSC in code) works just fine, however the USB2 one
(USB1 GDSC in code) it is stuck off and USB2 port will fail due to this:

     1.607531] ------------[ cut here ]------------
[    1.607559] usb1_gdsc status stuck at 'off'
[    1.607592] WARNING: CPU: 0 PID: 35 at gdsc_toggle_logic+0x16c/0x174
[    1.615120] Modules linked in:
[    1.621712] CPU: 0 PID: 35 Comm: kworker/u8:1 Tainted: G        W
        6.6.0-rc7-next-20231026 #5
[    1.624586] Hardware name: Wallys DR6018 v4 (DT)
[    1.633867] Workqueue: events_unbound deferred_probe_work_func
[    1.638556] pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[    1.644200] pc : gdsc_toggle_logic+0x16c/0x174
[    1.651052] lr : gdsc_toggle_logic+0x16c/0x174
[    1.655566] sp : ffffffc081a03a40
[    1.659990] x29: ffffffc081a03a40 x28: 0000000000000000 x27: 0000000000000000
[    1.663384] x26: ffffff8000156ac0 x25: 0000000000000000 x24: ffffffc081824c90
[    1.670502] x23: ffffffc081824840 x22: 0000000000000000 x21: 0000000000000001
[    1.677620] x20: 00000000ffffff92 x19: ffffffc081824840 x18: ffffffffffffffff
[    1.684738] x17: 00000000cdb32eee x16: 00000000d648a142 x15: fffffffffffc38ff
[    1.691855] x14: ffffffc0817994c0 x13: 00000000000000e0 x12: 00000000000000e0
[    1.698974] x11: 00000000ffffffea x10: ffffffc0817f14c0 x9 : 0000000000000001
[    1.706094] x8 : 0000000000000001 x7 : 0000000000017fe8 x6 : c0000000ffffefff
[    1.713211] x5 : 0000000000057fa8 x4 : 0000000000000000 x3 : ffffffc081a03840
[    1.720328] x2 : ffffffc081799400 x1 : ffffffc081799400 x0 : 000000000000001f
[    1.727448] Call trace:
[    1.734556]  gdsc_toggle_logic+0x16c/0x174
[    1.736815]  gdsc_enable+0x60/0x27c
[    1.740980]  genpd_power_on+0x180/0x22c
[    1.744367]  __genpd_dev_pm_attach+0x140/0x238
[    1.748188]  genpd_dev_pm_attach+0x60/0x70
[    1.752701]  dev_pm_domain_attach+0x20/0x34
[    1.756780]  platform_probe+0x50/0xc0
[    1.760859]  really_probe+0x148/0x2b8
[    1.764679]  __driver_probe_device+0x78/0x12c
[    1.768327]  driver_probe_device+0xdc/0x160
[    1.772667]  __device_attach_driver+0xb8/0x134
[    1.776660]  bus_for_each_drv+0x70/0xb8
[    1.781173]  __device_attach+0xa0/0x184
[    1.784905]  device_initial_probe+0x14/0x20
[    1.788725]  bus_probe_device+0xac/0xb0
[    1.792891]  deferred_probe_work_func+0x88/0xc0
[    1.796712]  process_one_work+0x158/0x2bc
[    1.801226]  worker_thread+0x2a0/0x4bc
[    1.805391]  kthread+0xe4/0xf0
[    1.809035]  ret_from_fork+0x10/0x20
[    1.812075] ---[ end trace 0000000000000000 ]---

Kathiravan, do you happen to have any docs or info if the USB1 GDSC is special and its status bits are broken or?

Maybe the offset is even wrong as I based it on the current driver.

Regards,
Robert

Quoted 92 lines

---
  drivers/clk/qcom/Kconfig       |  1 +
  drivers/clk/qcom/gcc-ipq6018.c | 33 ++++++++++++++++++++++++---------
  2 files changed, 25 insertions(+), 9 deletions(-)

drivers/clk/qcom/Kconfig +1 -0

index ad1acd9b7426b..2aefa2231b51b 100644
@@ -164,6 +164,7 @@ config IPQ_GCC_5332
 
  config IPQ_GCC_6018
         tristate "IPQ6018 Global Clock Controller"
+       select QCOM_GDSC
         help
           Support for global clock controller on ipq6018 devices.
           Say Y if you want to use peripheral devices such as UART, SPI,

drivers/clk/qcom/gcc-ipq6018.c +24 -10

index cc20a16d8973c..9d5ee2ac012a1 100644
@@ -23,6 +23,7 @@
  #include "clk-alpha-pll.h"
  #include "clk-regmap-divider.h"
  #include "clk-regmap-mux.h"
+#include "gdsc.h"
  #include "reset.h"
 
  enum {

@@ -4691,6 +4692,22 @@ static struct clk_branch gcc_dcc_clk = {
         },
  };
 
+static struct gdsc usb0_gdsc = {
+       .gdscr = 0x3e078,
+       .pd = {
+               .name = "usb0_gdsc",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc usb1_gdsc = {
+       .gdscr = 0x3f078,
+       .pd = {
+               .name = "usb1_gdsc",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+};
+
  static const struct alpha_pll_config ubi32_pll_config = {
         .l = 0x3e,
         .alpha = 0x6667,

@@ -5138,6 +5155,11 @@ static const struct qcom_reset_map gcc_ipq6018_resets[] = {
         [GCC_Q6_AXIM_ARES] = {0x59110, 4},
  };
 
+static struct gdsc *gcc_ipq6018_gdscs[] = {
+       [USB0_GDSC] = &usb0_gdsc,
+       [USB1_GDSC] = &usb1_gdsc,
+};
+
  static const struct of_device_id gcc_ipq6018_match_table[] = {
         { .compatible = "qcom,gcc-ipq6018" },
         { }

@@ -5160,6 +5182,8 @@ static const struct qcom_cc_desc gcc_ipq6018_desc = {
         .num_resets = ARRAY_SIZE(gcc_ipq6018_resets),
         .clk_hws = gcc_ipq6018_hws,
         .num_clk_hws = ARRAY_SIZE(gcc_ipq6018_hws),
+       .gdscs = gcc_ipq6018_gdscs,
+       .num_gdscs = ARRAY_SIZE(gcc_ipq6018_gdscs),
  };
 
  static int gcc_ipq6018_probe(struct platform_device *pdev)

@@ -5170,15 +5194,6 @@ static int gcc_ipq6018_probe(struct platform_device *pdev)
         if (IS_ERR(regmap))
                 return PTR_ERR(regmap);
 
-       /* Disable SW_COLLAPSE for USB0 GDSCR */
-       regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
-       /* Enable SW_OVERRIDE for USB0 GDSCR */
-       regmap_update_bits(regmap, 0x3e078, BIT(2), BIT(2));
-       /* Disable SW_COLLAPSE for USB1 GDSCR */
-       regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
-       /* Enable SW_OVERRIDE for USB1 GDSCR */
-       regmap_update_bits(regmap, 0x3f078, BIT(2), BIT(2));
-
         /* SW Workaround for UBI Huyara PLL */
         regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
 
--

2.41.0

Add bindings for the USB GDSCs found in IPQ6018 GCC.

Signed-off-by Robert Marko <[email protected]>

---