x86/CPU/AMD: Rework Zen family detection and other fun

PATCH Applied Borislav Petkov 5 participants 39 messages Nov 20, 2023 – Dec 12, 2023 x86

lore

Share & tools

lore

Borislav Petkov

author maintainer

2023-11-20 10:42 UTC #0 lore raw

cover x86/CPU/AMD: Rework Zen family detection and other fun

From: "Borislav Petkov (AMD)" <[email protected]>

Add Zen generation flags which will be used to check on what type of Zen the kernel runs. Distribute the per-generation init work into the respective functions and cleanup amd.c properly.

As a result, drop the errata checking gunk which is not needed anymore.

There should be no functionality change resulting from these changes.

Borislav Petkov (AMD) (13):
x86/CPU/AMD: Add ZenX generations flags
x86/CPU/AMD: Carve out the erratum 1386 fix
x86/CPU/AMD: Move the Zen3 BTC_NO detection to the Zen3 init function x86/CPU/AMD: Move erratum 1076 fix into the Zen1 init function x86/CPU/AMD: Call the spectral chicken in the Zen2 init function x86/CPU/AMD: Rename init_amd_zn() to init_amd_zen_common() x86/CPU/AMD: Move Zenbleed check to the Zen2 init function x86/CPU/AMD: Move the DIV0 bug detection to the Zen1 init function x86/CPU/AMD: Get rid of amd_erratum_1054[]
x86/CPU/AMD: Get rid of amd_erratum_383[]
x86/CPU/AMD: Get rid of amd_erratum_400[]
x86/CPU/AMD: Get rid of amd_erratum_1485[]
x86/CPU/AMD: Drop now unused CPU erratum checking function

 arch/x86/include/asm/cpufeatures.h |   6 +-
 arch/x86/kernel/cpu/amd.c          | 266 ++++++++++++++---------------
 2 files changed, 135 insertions(+), 137 deletions(-)

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

Borislav Petkov

author maintainer

2023-11-20 10:42 UTC #1 lore raw

PATCH 1/13 x86/CPU/AMD: Add ZenX generations flags

From: "Borislav Petkov (AMD)" <[email protected]>

Add X86_FEATURE flags for each Zen generation. They should be used from now on instead of checking f/m/s.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
 arch/x86/include/asm/cpufeatures.h |  6 ++-
 arch/x86/kernel/cpu/amd.c          | 70 +++++++++++++++++++++++++++++-
 2 files changed, 72 insertions(+), 4 deletions(-)

arch/x86/include/asm/cpufeatures.h +4 -2

index 4af140cf5719..6f6cf49e9891 100644
@@ -218,7 +218,7 @@
 #define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */
 #define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */
 #define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_ZEN			(7*32+28) /* "" CPU based on Zen microarchitecture */
+#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU based on Zen microarchitecture */
 #define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */
 #define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */
 #define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */

@@ -308,10 +308,12 @@
 #define X86_FEATURE_SMBA		(11*32+21) /* "" Slow Memory Bandwidth Allocation */
 #define X86_FEATURE_BMEC		(11*32+22) /* "" Bandwidth Monitoring Event Configuration */
 #define X86_FEATURE_USER_SHSTK		(11*32+23) /* Shadow stack support for user mode applications */
-
 #define X86_FEATURE_SRSO		(11*32+24) /* "" AMD BTB untrain RETs */
 #define X86_FEATURE_SRSO_ALIAS		(11*32+25) /* "" AMD BTB untrain RETs through aliasing */
 #define X86_FEATURE_IBPB_ON_VMEXIT	(11*32+26) /* "" Issue an IBPB only on VMEXIT */
+#define X86_FEATURE_ZEN2		(11*32+27) /* "" CPU based on Zen2 microarchitecture */
+#define X86_FEATURE_ZEN3		(11*32+28) /* "" CPU based on Zen3 microarchitecture */
+#define X86_FEATURE_ZEN4		(11*32+29) /* "" CPU based on Zen4 microarchitecture */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

arch/x86/kernel/cpu/amd.c +68 -2

94 lines not on this page · raw message

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-11-29 11:23 UTC #2 lore raw

[tip: x86/cpu] x86/CPU/AMD: Add ZenX generations flags

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     30fa92832f405d5ac9f263e99f62445fa3084008
Gitweb:        https://git.kernel.org/tip/30fa92832f405d5ac9f263e99f62445fa3084008
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Tue, 31 Oct 2023 23:30:59 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Wed, 29 Nov 2023 12:11:01 +01:00

x86/CPU/AMD: Add ZenX generations flags

Add X86_FEATURE flags for each Zen generation. They should be used from now on instead of checking f/m/s.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Reviewed-by Nikolay Borisov <[email protected]>

Acked-by Thomas Gleixner <[email protected]>

Link http://lore.kernel.org/r/[email protected] open here

---
 arch/x86/include/asm/cpufeatures.h |  5 +-
 arch/x86/kernel/cpu/amd.c          | 70 ++++++++++++++++++++++++++++-
 2 files changed, 72 insertions(+), 3 deletions(-)

arch/x86/include/asm/cpufeatures.h +4 -1

index 3e973ff..149cc5d 100644
@@ -218,7 +218,7 @@
 #define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */
 #define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */
 #define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_ZEN			(7*32+28) /* "" CPU based on Zen microarchitecture */
+#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU based on Zen microarchitecture */
 #define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */
 #define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */
 #define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */

@@ -312,6 +312,9 @@
 #define X86_FEATURE_SRSO_ALIAS		(11*32+25) /* "" AMD BTB untrain RETs through aliasing */
 #define X86_FEATURE_IBPB_ON_VMEXIT	(11*32+26) /* "" Issue an IBPB only on VMEXIT */
 #define X86_FEATURE_APIC_MSRS_FENCE	(11*32+27) /* "" IA32_TSC_DEADLINE and X2APIC MSRs need fencing */
+#define X86_FEATURE_ZEN2		(11*32+28) /* "" CPU based on Zen2 microarchitecture */
+#define X86_FEATURE_ZEN3		(11*32+29) /* "" CPU based on Zen3 microarchitecture */
+#define X86_FEATURE_ZEN4		(11*32+30) /* "" CPU based on Zen4 microarchitecture */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

arch/x86/kernel/cpu/amd.c +68 -2

94 lines not on this page · raw message

Tom Lendacky

2023-11-30 17:05 UTC #3 lore raw

Re: [PATCH 01/13] x86/CPU/AMD: Add ZenX generations flags

In reply to Borislav Petkov

Quoted 53 lines · Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

Add X86_FEATURE flags for each Zen generation. They should be used from now on instead of checking f/m/s.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
  arch/x86/include/asm/cpufeatures.h |  6 ++-
  arch/x86/kernel/cpu/amd.c          | 70 +++++++++++++++++++++++++++++-
  2 files changed, 72 insertions(+), 4 deletions(-)

arch/x86/include/asm/cpufeatures.h +4 -2

index 4af140cf5719..6f6cf49e9891 100644
@@ -218,7 +218,7 @@
  #define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */
  #define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */
  #define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_ZEN			(7*32+28) /* "" CPU based on Zen microarchitecture */
+#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU based on Zen microarchitecture */
  #define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */
  #define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */
  #define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */

@@ -308,10 +308,12 @@
  #define X86_FEATURE_SMBA		(11*32+21) /* "" Slow Memory Bandwidth Allocation */
  #define X86_FEATURE_BMEC		(11*32+22) /* "" Bandwidth Monitoring Event Configuration */
  #define X86_FEATURE_USER_SHSTK		(11*32+23) /* Shadow stack support for user mode applications */
-
  #define X86_FEATURE_SRSO		(11*32+24) /* "" AMD BTB untrain RETs */
  #define X86_FEATURE_SRSO_ALIAS		(11*32+25) /* "" AMD BTB untrain RETs through aliasing */
  #define X86_FEATURE_IBPB_ON_VMEXIT	(11*32+26) /* "" Issue an IBPB only on VMEXIT */
+#define X86_FEATURE_ZEN2		(11*32+27) /* "" CPU based on Zen2 microarchitecture */
+#define X86_FEATURE_ZEN3		(11*32+28) /* "" CPU based on Zen3 microarchitecture */
+#define X86_FEATURE_ZEN4		(11*32+29) /* "" CPU based on Zen4 microarchitecture */
 
  /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
  #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

arch/x86/kernel/cpu/amd.c +7 -0

index a7eab05e5f29..fa6ba63ca7e2 100644
@@ -616,6 +616,49 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
  	}
 
  	resctrl_cpu_detect(c);
+
+	/* Figure out Zen generations: */
+	switch (c->x86) {
+	case 0x17: {
+		switch (c->x86_model) {
+		case 0x00 ... 0x2f:
+		case 0x50 ... 0x5f:

arch/x86/kernel/cpu/amd.c static void bsp_init_amd(struct cpuinfo_x86 *c) · line 635

Quoted 10 lines

arch/x86/kernel/cpu/amd.c +10 -0

+			setup_force_cpu_cap(X86_FEATURE_ZEN);
+			break;
+		case 0x30 ... 0x4f:
+		case 0x60 ... 0x7f:
+		case 0x90 ... 0x91:
+		case 0xa0 ... 0xaf:
+			setup_force_cpu_cap(X86_FEATURE_ZEN2);
+			break;
+		default:
+			goto warn;

Previously just being family 17h or 19h would get X86_FEATURE_ZEN set. With this, if the model check doesn't match, you won't get any X86_FEATURE_ZEN* set. Should you do set X86_FEATURE_ZEN here, e.g. lowest common denominator for the family?

Quoted 4 lines

arch/x86/kernel/cpu/amd.c +4 -0
+		}
+		break;
+	}
+	case 0x19: {

arch/x86/kernel/cpu/amd.c static void bsp_init_amd(struct cpuinfo_x86 *c) · line 649

Quoted 10 lines

arch/x86/kernel/cpu/amd.c +10 -0

+		switch (c->x86_model) {
+		case 0x00 ... 0x0f:
+		case 0x20 ... 0x5f:
+			setup_force_cpu_cap(X86_FEATURE_ZEN3);
+			break;
+		case 0x10 ... 0x1f:
+		case 0x60 ... 0xaf:
+			setup_force_cpu_cap(X86_FEATURE_ZEN4);
+			break;
+		default:

Ditto here to set X86_FEATURE_ZEN3?

Thanks,
Tom

Quoted 63 lines

arch/x86/kernel/cpu/amd.c +37 -2

+			goto warn;
+		}
+		break;
+	}
+	default:
+		break;
+	}
+
+	return;
+
+warn:
+	WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model);
  }
 
  static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)

@@ -974,8 +1017,6 @@ void init_spectral_chicken(struct cpuinfo_x86 *c)
 
  static void init_amd_zn(struct cpuinfo_x86 *c)
  {
-	set_cpu_cap(c, X86_FEATURE_ZEN);
-
  #ifdef CONFIG_NUMA
  	node_reclaim_distance = 32;
  #endif

@@ -997,6 +1038,22 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
  	}
  }
 
+static void init_amd_zen(struct cpuinfo_x86 *c)
+{
+}
+
+static void init_amd_zen2(struct cpuinfo_x86 *c)
+{
+}
+
+static void init_amd_zen3(struct cpuinfo_x86 *c)
+{
+}
+
+static void init_amd_zen4(struct cpuinfo_x86 *c)
+{
+}
+
  static bool cpu_has_zenbleed_microcode(void)
  {
  	u32 good_rev = 0;

@@ -1077,6 +1134,15 @@ static void init_amd(struct cpuinfo_x86 *c)
  	case 0x19: init_amd_zn(c); break;
  	}
 
+	if (boot_cpu_has(X86_FEATURE_ZEN))
+		init_amd_zen(c);
+	else if (boot_cpu_has(X86_FEATURE_ZEN2))
+		init_amd_zen2(c);
+	else if (boot_cpu_has(X86_FEATURE_ZEN3))
+		init_amd_zen3(c);
+	else if (boot_cpu_has(X86_FEATURE_ZEN4))
+		init_amd_zen4(c);
+
  	/*
  	 * Enable workaround for FXSAVE leak on CPUs
  	 * without a XSaveErPtr feature

Borislav Petkov

author maintainer

2023-11-30 17:14 UTC #4 lore raw

Re: [PATCH 01/13] x86/CPU/AMD: Add ZenX generations flags

Quoted 4 lines · Tom Lendacky

Previously just being family 17h or 19h would get X86_FEATURE_ZEN set. With this, if the model check doesn't match, you won't get any X86_FEATURE_ZEN* set. Should you do set X86_FEATURE_ZEN here, e.g. lowest common denominator for the family?

My assumption/expectation is that those WARNs should never happen because they will be caught early enough in enablement and I will get patches.

Besides, X86_FEATURE_ZEN means only Zen1 now.

Signature · 4 lines

Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Brian Gerst

2023-11-30 18:05 UTC #5 lore raw

Re: [PATCH 01/13] x86/CPU/AMD: Add ZenX generations flags

Quoted 7 lines · Borislav Petkov

Quoted 4 lines · Tom Lendacky
Previously just being family 17h or 19h would get X86_FEATURE_ZEN set. With this, if the model check doesn't match, you won't get any X86_FEATURE_ZEN* set. Should you do set X86_FEATURE_ZEN here, e.g. lowest common denominator for the family?

Quoted 5 lines

My assumption/expectation is that those WARNs should never happen because they will be caught early enough in enablement and I will get patches.
Besides, X86_FEATURE_ZEN means only Zen1 now.

It should be renamed to X86_FEATURE_ZEN1 for clarity.

Brian Gerst

Tom Lendacky

2023-11-30 18:17 UTC #6 lore raw

Re: [PATCH 01/13] x86/CPU/AMD: Add ZenX generations flags

In reply to Borislav Petkov

Quoted 11 lines · Borislav Petkov

Quoted 4 lines · Tom Lendacky
Previously just being family 17h or 19h would get X86_FEATURE_ZEN set. With this, if the model check doesn't match, you won't get any X86_FEATURE_ZEN* set. Should you do set X86_FEATURE_ZEN here, e.g. lowest common denominator for the family?
My assumption/expectation is that those WARNs should never happen because they will be caught early enough in enablement and I will get patches.
Besides, X86_FEATURE_ZEN means only Zen1 now.

There are references to X86_FEATURE_ZEN in arch/x86/kernel/process.c and drivers/acpi/resource.c that should probably be vetted.

Maybe having X86_FEATURE_ZEN mean all ZEN (and set for anything family 17h or higher) and a separate per generation, e.g. X86_FEATURE_ZEN1, when you need to be specific, would work.

Thanks,
Tom

Quoted 1 line

Borislav Petkov

author maintainer

2023-11-30 18:51 UTC #7 lore raw

Re: [PATCH 01/13] x86/CPU/AMD: Add ZenX generations flags

Quoted 6 lines · Tom Lendacky

There are references to X86_FEATURE_ZEN in arch/x86/kernel/process.c and drivers/acpi/resource.c that should probably be vetted.
Maybe having X86_FEATURE_ZEN mean all ZEN (and set for anything family 17h or higher) and a separate per generation, e.g. X86_FEATURE_ZEN1, when you need to be specific, would work.

Yap, looks like it. Those process.c and resource.c things mean all Zen
- and perhaps that really should mean that - Zen and newer. This all falls nicely into place anyway since Zen stopped using a family number per generation so that's a natural cutoff point where we're going to start using those synthetic feature flags for the generations and one for all Zens.

And yap, the Zen1 stuff should probably be behind X86_FEATURE_ZEN1.

Yap, sounds good. Lemme cook up a patch tomorrow.

Thx to you and Brian for the suggestions.

Signature · 4 lines

Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Borislav Petkov

author maintainer

2023-12-02 12:49 UTC #8 lore raw

PATCH 1/1 x86/CPU/AMD: Add X86_FEATURE_ZEN1

From: "Borislav Petkov (AMD)" <[email protected]>
Date: Sat, 2 Dec 2023 12:50:23 +0100

Add a synthetic feature flag specifically for first generation Zen machines. There's need to have a generic flag for all Zen generations so make X86_FEATURE_ZEN be that flag.

Fixes 30fa92832f40 ("x86/CPU/AMD: Add ZenX generations flags")

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Link https://lore.kernel.org/r/[email protected] open here

---
 arch/x86/include/asm/cpufeatures.h       | 3 ++-
 arch/x86/kernel/cpu/amd.c                | 7 ++++---
 tools/arch/x86/include/asm/cpufeatures.h | 2 +-
 3 files changed, 7 insertions(+), 5 deletions(-)

arch/x86/include/asm/cpufeatures.h +2 -1

index 149cc5d5c2ae..632c26cdeeda 100644
@@ -218,7 +218,7 @@
 #define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */
 #define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */
 #define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU based on Zen microarchitecture */
+#define X86_FEATURE_ZEN			( 7*32+28) /* "" Generic flag for all Zen and newer */
 #define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */
 #define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */
 #define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */

@@ -315,6 +315,7 @@
 #define X86_FEATURE_ZEN2		(11*32+28) /* "" CPU based on Zen2 microarchitecture */
 #define X86_FEATURE_ZEN3		(11*32+29) /* "" CPU based on Zen3 microarchitecture */
 #define X86_FEATURE_ZEN4		(11*32+30) /* "" CPU based on Zen4 microarchitecture */
+#define X86_FEATURE_ZEN1		(11*32+31) /* "" CPU based on Zen1 microarchitecture */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

arch/x86/kernel/cpu/amd.c +4 -3

index 9a2e0ec8d0f9..68669158faa4 100644
@@ -542,7 +542,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
 		switch (c->x86_model) {
 		case 0x00 ... 0x2f:
 		case 0x50 ... 0x5f:
-			setup_force_cpu_cap(X86_FEATURE_ZEN);
+			setup_force_cpu_cap(X86_FEATURE_ZEN1);
 			break;
 		case 0x30 ... 0x4f:
 		case 0x60 ... 0x7f:

@@ -948,6 +948,7 @@ void init_spectral_chicken(struct cpuinfo_x86 *c)
 
 static void init_amd_zen_common(void)
 {
+	setup_force_cpu_cap(X86_FEATURE_ZEN);
 #ifdef CONFIG_NUMA
 	node_reclaim_distance = 32;
 #endif

@@ -1075,7 +1076,7 @@ static void init_amd(struct cpuinfo_x86 *c)
 	case 0x16: init_amd_jg(c); break;
 	}
 
-	if (boot_cpu_has(X86_FEATURE_ZEN))
+	if (boot_cpu_has(X86_FEATURE_ZEN1))
 		init_amd_zen(c);
 	else if (boot_cpu_has(X86_FEATURE_ZEN2))
 		init_amd_zen2(c);

@@ -1143,7 +1144,7 @@ static void init_amd(struct cpuinfo_x86 *c)
 	 * Counter May Be Inaccurate".
 	 */
 	if (cpu_has(c, X86_FEATURE_IRPERF) &&
-	    (boot_cpu_has(X86_FEATURE_ZEN) && c->x86_model > 0x2f))
+	    (boot_cpu_has(X86_FEATURE_ZEN1) && c->x86_model > 0x2f))
 		msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
 
 	check_null_seg_clears_base(c);

tools/arch/x86/include/asm/cpufeatures.h +1 -1

index 4af140cf5719..f4542d2718f4 100644
@@ -218,7 +218,7 @@
 #define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */
 #define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */
 #define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_ZEN			(7*32+28) /* "" CPU based on Zen microarchitecture */
+#define X86_FEATURE_ZEN			( 7*32+28) /* "" Generic flag for all Zen and newer */
 #define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */
 #define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */
 #define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */

Signature · 8 lines

2.42.0.rc0.25.ga82fb66fed25


-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Tom Lendacky

2023-12-04 14:36 UTC #9 lore raw

Re: [PATCH] x86/CPU/AMD: Add X86_FEATURE_ZEN1

Quoted 15 lines · Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>
Date: Sat, 2 Dec 2023 12:50:23 +0100
Add a synthetic feature flag specifically for first generation Zen machines. There's need to have a generic flag for all Zen generations so make X86_FEATURE_ZEN be that flag.
Fixes 30fa92832f40 ("x86/CPU/AMD: Add ZenX generations flags")
Suggested-by Brian Gerst <[email protected]>
Suggested-by Tom Lendacky <[email protected]>
Signed-off-by Borislav Petkov (AMD) <[email protected]>
Link https://lore.kernel.org/r/[email protected] open here
---

arch/x86/kernel/cpu/amd.c static void init_amd(struct cpuinfo_x86 *c) · line 1080

Quoted 3 lines

arch/x86/kernel/cpu/amd.c +1 -1

-	if (boot_cpu_has(X86_FEATURE_ZEN))
+	if (boot_cpu_has(X86_FEATURE_ZEN1))
  		init_amd_zen(c);

Should this be renamed to init_amd_zen1(), just to avoid confusion?

Thanks,
Tom

Quoted 2 lines

  	else if (boot_cpu_has(X86_FEATURE_ZEN2))
  		init_amd_zen2(c);

Borislav Petkov

author maintainer

2023-12-04 15:32 UTC #10 lore raw

Re: [PATCH] x86/CPU/AMD: Add X86_FEATURE_ZEN1

Quoted 1 line · Tom Lendacky

Should this be renamed to init_amd_zen1(), just to avoid confusion?

Done.

Thx.

Signature · 4 lines

Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-12-12 10:33 UTC #11 lore raw

[tip: x86/cpu] x86/CPU/AMD: Add X86_FEATURE_ZEN1

In reply to Tom Lendacky

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     232afb557835d6f6859c73bf610bad308c96b131
Gitweb:        https://git.kernel.org/tip/232afb557835d6f6859c73bf610bad308c96b131
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Sat, 02 Dec 2023 12:50:23 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Tue, 12 Dec 2023 11:17:37 +01:00

x86/CPU/AMD: Add X86_FEATURE_ZEN1

Add a synthetic feature flag specifically for first generation Zen machines. There's need to have a generic flag for all Zen generations so make X86_FEATURE_ZEN be that flag.

Fixes 30fa92832f40 ("x86/CPU/AMD: Add ZenX generations flags")

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Link https://lore.kernel.org/r/[email protected] open here

---
 arch/x86/include/asm/cpufeatures.h       |  3 ++-
 arch/x86/kernel/cpu/amd.c                | 11 ++++++-----
 tools/arch/x86/include/asm/cpufeatures.h |  2 +-
 3 files changed, 9 insertions(+), 7 deletions(-)

arch/x86/include/asm/cpufeatures.h +2 -1

index 149cc5d..632c26c 100644
@@ -218,7 +218,7 @@
 #define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */
 #define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */
 #define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU based on Zen microarchitecture */
+#define X86_FEATURE_ZEN			( 7*32+28) /* "" Generic flag for all Zen and newer */
 #define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */
 #define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */
 #define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */

@@ -315,6 +315,7 @@
 #define X86_FEATURE_ZEN2		(11*32+28) /* "" CPU based on Zen2 microarchitecture */
 #define X86_FEATURE_ZEN3		(11*32+29) /* "" CPU based on Zen3 microarchitecture */
 #define X86_FEATURE_ZEN4		(11*32+30) /* "" CPU based on Zen4 microarchitecture */
+#define X86_FEATURE_ZEN1		(11*32+31) /* "" CPU based on Zen1 microarchitecture */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

arch/x86/kernel/cpu/amd.c +6 -5

index 89bbb1a..3395863 100644
@@ -542,7 +542,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
 		switch (c->x86_model) {
 		case 0x00 ... 0x2f:
 		case 0x50 ... 0x5f:
-			setup_force_cpu_cap(X86_FEATURE_ZEN);
+			setup_force_cpu_cap(X86_FEATURE_ZEN1);
 			break;
 		case 0x30 ... 0x4f:
 		case 0x60 ... 0x7f:

@@ -948,12 +948,13 @@ void init_spectral_chicken(struct cpuinfo_x86 *c)
 
 static void init_amd_zen_common(void)
 {
+	setup_force_cpu_cap(X86_FEATURE_ZEN);
 #ifdef CONFIG_NUMA
 	node_reclaim_distance = 32;
 #endif
 }
 
-static void init_amd_zen(struct cpuinfo_x86 *c)
+static void init_amd_zen1(struct cpuinfo_x86 *c)
 {
 	init_amd_zen_common();
 	fix_erratum_1386(c);

@@ -1075,8 +1076,8 @@ static void init_amd(struct cpuinfo_x86 *c)
 	case 0x16: init_amd_jg(c); break;
 	}
 
-	if (boot_cpu_has(X86_FEATURE_ZEN))
-		init_amd_zen(c);
+	if (boot_cpu_has(X86_FEATURE_ZEN1))
+		init_amd_zen1(c);
 	else if (boot_cpu_has(X86_FEATURE_ZEN2))
 		init_amd_zen2(c);
 	else if (boot_cpu_has(X86_FEATURE_ZEN3))

@@ -1143,7 +1144,7 @@ static void init_amd(struct cpuinfo_x86 *c)
 	 * Counter May Be Inaccurate".
 	 */
 	if (cpu_has(c, X86_FEATURE_IRPERF) &&
-	    (boot_cpu_has(X86_FEATURE_ZEN) && c->x86_model > 0x2f))
+	    (boot_cpu_has(X86_FEATURE_ZEN1) && c->x86_model > 0x2f))
 		msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
 
 	check_null_seg_clears_base(c);

tools/arch/x86/include/asm/cpufeatures.h +1 -1

index 798e60b..845a402 100644
@@ -219,7 +219,7 @@
 #define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */
 #define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */
 #define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_ZEN			(7*32+28) /* "" CPU based on Zen microarchitecture */
+#define X86_FEATURE_ZEN			( 7*32+28) /* "" Generic flag for all Zen and newer */
 #define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */
 #define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */
 #define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */

Borislav Petkov

author maintainer

2023-11-20 10:42 UTC #12 lore raw

PATCH 2/13 x86/CPU/AMD: Carve out the erratum 1386 fix

In reply to Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

Call it on the affected CPU generations.

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
 arch/x86/kernel/cpu/amd.c | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

arch/x86/kernel/cpu/amd.c +15 -9

index fa6ba63ca7e2..b3f939101368 100644
@@ -984,6 +984,19 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
 	clear_rdrand_cpuid_bit(c);
 }
 
+static void fix_erratum_1386(struct cpuinfo_x86 *c)
+{
+	/*
+	 * Work around Erratum 1386.  The XSAVES instruction malfunctions in
+	 * certain circumstances on Zen1/2 uarch, and not all parts have had
+	 * updated microcode at the time of writing (March 2023).
+	 *
+	 * Affected parts all have no supervisor XSAVE states, meaning that
+	 * the XSAVEC instruction (which works fine) is equivalent.
+	 */
+	clear_cpu_cap(c, X86_FEATURE_XSAVES);
+}
+
 void init_spectral_chicken(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_CPU_UNRET_ENTRY

@@ -1004,15 +1017,6 @@ void init_spectral_chicken(struct cpuinfo_x86 *c)
 		}
 	}
 #endif
-	/*
-	 * Work around Erratum 1386.  The XSAVES instruction malfunctions in
-	 * certain circumstances on Zen1/2 uarch, and not all parts have had
-	 * updated microcode at the time of writing (March 2023).
-	 *
-	 * Affected parts all have no supervisor XSAVE states, meaning that
-	 * the XSAVEC instruction (which works fine) is equivalent.
-	 */
-	clear_cpu_cap(c, X86_FEATURE_XSAVES);
 }
 
 static void init_amd_zn(struct cpuinfo_x86 *c)

@@ -1040,10 +1044,12 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
 
 static void init_amd_zen(struct cpuinfo_x86 *c)
 {
+	fix_erratum_1386(c);
 }
 
 static void init_amd_zen2(struct cpuinfo_x86 *c)
 {
+	fix_erratum_1386(c);
 }
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-11-29 11:23 UTC #13 lore raw

[tip: x86/cpu] x86/CPU/AMD: Carve out the erratum 1386 fix

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     a7c32a1ae9ee43abfe884f5af376877c4301d166
Gitweb:        https://git.kernel.org/tip/a7c32a1ae9ee43abfe884f5af376877c4301d166
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Wed, 01 Nov 2023 11:14:59 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Wed, 29 Nov 2023 12:11:21 +01:00

x86/CPU/AMD: Carve out the erratum 1386 fix

Call it on the affected CPU generations.

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Reviewed-by Nikolay Borisov <[email protected]>

Link http://lore.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/cpu/amd.c | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

arch/x86/kernel/cpu/amd.c +15 -9

index 6aba224..0a499cb 100644
@@ -984,6 +984,19 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
 	clear_rdrand_cpuid_bit(c);
 }
 
+static void fix_erratum_1386(struct cpuinfo_x86 *c)
+{
+	/*
+	 * Work around Erratum 1386.  The XSAVES instruction malfunctions in
+	 * certain circumstances on Zen1/2 uarch, and not all parts have had
+	 * updated microcode at the time of writing (March 2023).
+	 *
+	 * Affected parts all have no supervisor XSAVE states, meaning that
+	 * the XSAVEC instruction (which works fine) is equivalent.
+	 */
+	clear_cpu_cap(c, X86_FEATURE_XSAVES);
+}
+
 void init_spectral_chicken(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_CPU_UNRET_ENTRY

@@ -1004,15 +1017,6 @@ void init_spectral_chicken(struct cpuinfo_x86 *c)
 		}
 	}
 #endif
-	/*
-	 * Work around Erratum 1386.  The XSAVES instruction malfunctions in
-	 * certain circumstances on Zen1/2 uarch, and not all parts have had
-	 * updated microcode at the time of writing (March 2023).
-	 *
-	 * Affected parts all have no supervisor XSAVE states, meaning that
-	 * the XSAVEC instruction (which works fine) is equivalent.
-	 */
-	clear_cpu_cap(c, X86_FEATURE_XSAVES);
 }
 
 static void init_amd_zn(struct cpuinfo_x86 *c)

@@ -1080,10 +1084,12 @@ static void zenbleed_check(struct cpuinfo_x86 *c)
 
 static void init_amd_zen(struct cpuinfo_x86 *c)
 {
+	fix_erratum_1386(c);
 }
 
 static void init_amd_zen2(struct cpuinfo_x86 *c)
 {
+	fix_erratum_1386(c);
 }
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)

Borislav Petkov

author maintainer

2023-11-20 10:42 UTC #14 lore raw

PATCH 3/13 x86/CPU/AMD: Move the Zen3 BTC_NO detection to the Zen3 init function

In reply to Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
 arch/x86/kernel/cpu/amd.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

arch/x86/kernel/cpu/amd.c +9 -8

index b3f939101368..92202bad9bd3 100644
@@ -1031,14 +1031,6 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
 		/* Erratum 1076: CPB feature bit not being set in CPUID. */
 		if (!cpu_has(c, X86_FEATURE_CPB))
 			set_cpu_cap(c, X86_FEATURE_CPB);
-
-		/*
-		 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
-		 * Branch Type Confusion, but predate the allocation of the
-		 * BTC_NO bit.
-		 */
-		if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO))
-			set_cpu_cap(c, X86_FEATURE_BTC_NO);
 	}
 }

@@ -1054,6 +1046,15 @@ static void init_amd_zen2(struct cpuinfo_x86 *c)
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)
 {
+	if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
+		/*
+		 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
+		 * Branch Type Confusion, but predate the allocation of the
+		 * BTC_NO bit.
+		 */
+		if (!cpu_has(c, X86_FEATURE_BTC_NO))
+			set_cpu_cap(c, X86_FEATURE_BTC_NO);
+	}
 }
 
 static void init_amd_zen4(struct cpuinfo_x86 *c)

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-11-29 11:23 UTC #15 lore raw

[tip: x86/cpu] x86/CPU/AMD: Move the Zen3 BTC_NO detection to the Zen3 init function

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     affc66cb96f865b3763a8e18add52e133d864f04
Gitweb:        https://git.kernel.org/tip/affc66cb96f865b3763a8e18add52e133d864f04
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Wed, 01 Nov 2023 11:28:31 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Wed, 29 Nov 2023 12:11:44 +01:00

x86/CPU/AMD: Move the Zen3 BTC_NO detection to the Zen3 init function

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Reviewed-by Nikolay Borisov <[email protected]>

Link http://lore.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/cpu/amd.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

arch/x86/kernel/cpu/amd.c +9 -8

index 0a499cb..3d74347 100644
@@ -1031,14 +1031,6 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
 		/* Erratum 1076: CPB feature bit not being set in CPUID. */
 		if (!cpu_has(c, X86_FEATURE_CPB))
 			set_cpu_cap(c, X86_FEATURE_CPB);
-
-		/*
-		 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
-		 * Branch Type Confusion, but predate the allocation of the
-		 * BTC_NO bit.
-		 */
-		if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO))
-			set_cpu_cap(c, X86_FEATURE_BTC_NO);
 	}
 }

@@ -1094,6 +1086,15 @@ static void init_amd_zen2(struct cpuinfo_x86 *c)
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)
 {
+	if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
+		/*
+		 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
+		 * Branch Type Confusion, but predate the allocation of the
+		 * BTC_NO bit.
+		 */
+		if (!cpu_has(c, X86_FEATURE_BTC_NO))
+			set_cpu_cap(c, X86_FEATURE_BTC_NO);
+	}
 }
 
 static void init_amd_zen4(struct cpuinfo_x86 *c)

Borislav Petkov

author maintainer

2023-11-20 10:42 UTC #16 lore raw

PATCH 4/13 x86/CPU/AMD: Move erratum 1076 fix into the Zen1 init function

In reply to Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
 arch/x86/kernel/cpu/amd.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

arch/x86/kernel/cpu/amd.c +5 -5

index 92202bad9bd3..6d87c43e4ee9 100644
@@ -1024,6 +1024,11 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
 #ifdef CONFIG_NUMA
 	node_reclaim_distance = 32;
 #endif
+}
+
+static void init_amd_zen(struct cpuinfo_x86 *c)
+{
+	fix_erratum_1386(c);
 
 	/* Fix up CPUID bits, but only if not virtualised. */
 	if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {

@@ -1034,11 +1039,6 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
 	}
 }
 
-static void init_amd_zen(struct cpuinfo_x86 *c)
-{
-	fix_erratum_1386(c);
-}
-
 static void init_amd_zen2(struct cpuinfo_x86 *c)
 {
 	fix_erratum_1386(c);

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-11-29 11:22 UTC #17 lore raw

[tip: x86/cpu] x86/CPU/AMD: Move erratum 1076 fix into the Zen1 init function

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     0da91912fc150d6d321b15e648bead202ced1a27
Gitweb:        https://git.kernel.org/tip/0da91912fc150d6d321b15e648bead202ced1a27
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Wed, 01 Nov 2023 12:31:44 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Wed, 29 Nov 2023 12:11:59 +01:00

x86/CPU/AMD: Move erratum 1076 fix into the Zen1 init function

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Reviewed-by Nikolay Borisov <[email protected]>

Link http://lore.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/cpu/amd.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

arch/x86/kernel/cpu/amd.c +5 -5

index 3d74347..ebe6be8 100644
@@ -1024,6 +1024,11 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
 #ifdef CONFIG_NUMA
 	node_reclaim_distance = 32;
 #endif
+}
+
+static void init_amd_zen(struct cpuinfo_x86 *c)
+{
+	fix_erratum_1386(c);
 
 	/* Fix up CPUID bits, but only if not virtualised. */
 	if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {

@@ -1074,11 +1079,6 @@ static void zenbleed_check(struct cpuinfo_x86 *c)
 	}
 }
 
-static void init_amd_zen(struct cpuinfo_x86 *c)
-{
-	fix_erratum_1386(c);
-}
-
 static void init_amd_zen2(struct cpuinfo_x86 *c)
 {
 	fix_erratum_1386(c);

Borislav Petkov

author maintainer

2023-11-20 10:42 UTC #18 lore raw

PATCH 5/13 x86/CPU/AMD: Call the spectral chicken in the Zen2 init function

In reply to Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

No functional change.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
 arch/x86/kernel/cpu/amd.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

arch/x86/kernel/cpu/amd.c +3 -4

index 6d87c43e4ee9..f43a70d495da 100644
@@ -1007,10 +1007,8 @@ void init_spectral_chicken(struct cpuinfo_x86 *c)
 	 *
 	 * This suppresses speculation from the middle of a basic block, i.e. it
 	 * suppresses non-branch predictions.
-	 *
-	 * We use STIBP as a heuristic to filter out Zen2 from the rest of F17H
 	 */
-	if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) {
+	if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
 		if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) {
 			value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT;
 			wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value);

@@ -1041,6 +1039,7 @@ static void init_amd_zen(struct cpuinfo_x86 *c)
 
 static void init_amd_zen2(struct cpuinfo_x86 *c)
 {
+	init_spectral_chicken(c);
 	fix_erratum_1386(c);
 }

@@ -1136,7 +1135,7 @@ static void init_amd(struct cpuinfo_x86 *c)
 	case 0x12: init_amd_ln(c); break;
 	case 0x15: init_amd_bd(c); break;
 	case 0x16: init_amd_jg(c); break;
-	case 0x17: init_spectral_chicken(c);
+	case 0x17:
 		   fallthrough;
 	case 0x19: init_amd_zn(c); break;
 	}

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-11-29 11:23 UTC #19 lore raw

[tip: x86/cpu] x86/CPU/AMD: Call the spectral chicken in the Zen2 init function

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     cfbf4f992bfce1fa9f2f347a79cbbea0368e7971
Gitweb:        https://git.kernel.org/tip/cfbf4f992bfce1fa9f2f347a79cbbea0368e7971
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Wed, 01 Nov 2023 11:20:01 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Wed, 29 Nov 2023 12:12:20 +01:00

x86/CPU/AMD: Call the spectral chicken in the Zen2 init function

No functional change.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Reviewed-by Nikolay Borisov <[email protected]>

Link http://lore.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/cpu/amd.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

arch/x86/kernel/cpu/amd.c +3 -4

index ebe6be8..82747b6 100644
@@ -1007,10 +1007,8 @@ void init_spectral_chicken(struct cpuinfo_x86 *c)
 	 *
 	 * This suppresses speculation from the middle of a basic block, i.e. it
 	 * suppresses non-branch predictions.
-	 *
-	 * We use STIBP as a heuristic to filter out Zen2 from the rest of F17H
 	 */
-	if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) {
+	if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
 		if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) {
 			value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT;
 			wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value);

@@ -1081,6 +1079,7 @@ static void zenbleed_check(struct cpuinfo_x86 *c)
 
 static void init_amd_zen2(struct cpuinfo_x86 *c)
 {
+	init_spectral_chicken(c);
 	fix_erratum_1386(c);
 }

@@ -1136,7 +1135,7 @@ static void init_amd(struct cpuinfo_x86 *c)
 	case 0x12: init_amd_ln(c); break;
 	case 0x15: init_amd_bd(c); break;
 	case 0x16: init_amd_jg(c); break;
-	case 0x17: init_spectral_chicken(c);
+	case 0x17:
 		   fallthrough;
 	case 0x19: init_amd_zn(c); break;
 	}

Borislav Petkov

author maintainer

2023-11-20 10:43 UTC #20 lore raw

PATCH 6/13 x86/CPU/AMD: Rename init_amd_zn() to init_amd_zen_common()

In reply to Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

Call it from all Zen init functions.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
 arch/x86/kernel/cpu/amd.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

arch/x86/kernel/cpu/amd.c +7 -4

index f43a70d495da..8d90f5f6b0d9 100644
@@ -1017,7 +1017,7 @@ void init_spectral_chicken(struct cpuinfo_x86 *c)
 #endif
 }
 
-static void init_amd_zn(struct cpuinfo_x86 *c)
+static void init_amd_zen_common(void)
 {
 #ifdef CONFIG_NUMA
 	node_reclaim_distance = 32;

@@ -1026,6 +1026,7 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
 
 static void init_amd_zen(struct cpuinfo_x86 *c)
 {
+	init_amd_zen_common();
 	fix_erratum_1386(c);
 
 	/* Fix up CPUID bits, but only if not virtualised. */

@@ -1035,16 +1036,20 @@ static void init_amd_zen(struct cpuinfo_x86 *c)
 		if (!cpu_has(c, X86_FEATURE_CPB))
 			set_cpu_cap(c, X86_FEATURE_CPB);
 	}
+
 }
 
 static void init_amd_zen2(struct cpuinfo_x86 *c)
 {
+	init_amd_zen_common();
 	init_spectral_chicken(c);
 	fix_erratum_1386(c);
 }
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)
 {
+	init_amd_zen_common();
+
 	if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
 		/*
 		 * Zen3 (Fam19 model < 0x10) parts are not susceptible to

@@ -1058,6 +1063,7 @@ static void init_amd_zen3(struct cpuinfo_x86 *c)
 
 static void init_amd_zen4(struct cpuinfo_x86 *c)
 {
+	init_amd_zen_common();
 }
 
 static bool cpu_has_zenbleed_microcode(void)

@@ -1135,9 +1141,6 @@ static void init_amd(struct cpuinfo_x86 *c)
 	case 0x12: init_amd_ln(c); break;
 	case 0x15: init_amd_bd(c); break;
 	case 0x16: init_amd_jg(c); break;
-	case 0x17:
-		   fallthrough;
-	case 0x19: init_amd_zn(c); break;
 	}
 
 	if (boot_cpu_has(X86_FEATURE_ZEN))

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-11-29 11:22 UTC #21 lore raw

[tip: x86/cpu] x86/CPU/AMD: Rename init_amd_zn() to init_amd_zen_common()

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     7c81ad8e8bc28a1847e87c5afe1bae6bffb2f73e
Gitweb:        https://git.kernel.org/tip/7c81ad8e8bc28a1847e87c5afe1bae6bffb2f73e
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Wed, 01 Nov 2023 12:34:29 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Wed, 29 Nov 2023 12:12:27 +01:00

x86/CPU/AMD: Rename init_amd_zn() to init_amd_zen_common()

Call it from all Zen init functions.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Reviewed-by Nikolay Borisov <[email protected]>

Link http://lore.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/cpu/amd.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

arch/x86/kernel/cpu/amd.c +7 -4

index 82747b6..f53e0a2 100644
@@ -1017,7 +1017,7 @@ void init_spectral_chicken(struct cpuinfo_x86 *c)
 #endif
 }
 
-static void init_amd_zn(struct cpuinfo_x86 *c)
+static void init_amd_zen_common(void)
 {
 #ifdef CONFIG_NUMA
 	node_reclaim_distance = 32;

@@ -1026,6 +1026,7 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
 
 static void init_amd_zen(struct cpuinfo_x86 *c)
 {
+	init_amd_zen_common();
 	fix_erratum_1386(c);
 
 	/* Fix up CPUID bits, but only if not virtualised. */

@@ -1075,16 +1076,20 @@ static void zenbleed_check(struct cpuinfo_x86 *c)
 	} else {
 		msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
 	}
+
 }
 
 static void init_amd_zen2(struct cpuinfo_x86 *c)
 {
+	init_amd_zen_common();
 	init_spectral_chicken(c);
 	fix_erratum_1386(c);
 }
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)
 {
+	init_amd_zen_common();
+
 	if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
 		/*
 		 * Zen3 (Fam19 model < 0x10) parts are not susceptible to

@@ -1098,6 +1103,7 @@ static void init_amd_zen3(struct cpuinfo_x86 *c)
 
 static void init_amd_zen4(struct cpuinfo_x86 *c)
 {
+	init_amd_zen_common();
 }
 
 static void init_amd(struct cpuinfo_x86 *c)

@@ -1135,9 +1141,6 @@ static void init_amd(struct cpuinfo_x86 *c)
 	case 0x12: init_amd_ln(c); break;
 	case 0x15: init_amd_bd(c); break;
 	case 0x16: init_amd_jg(c); break;
-	case 0x17:
-		   fallthrough;
-	case 0x19: init_amd_zn(c); break;
 	}
 
 	if (boot_cpu_has(X86_FEATURE_ZEN))

Borislav Petkov

author maintainer

2023-11-20 10:43 UTC #22 lore raw

PATCH 7/13 x86/CPU/AMD: Move Zenbleed check to the Zen2 init function

In reply to Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

Prefix it properly so that it is clear which generation it is dealing with.

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
 arch/x86/kernel/cpu/amd.c | 70 +++++++++++++++++----------------------
 1 file changed, 30 insertions(+), 40 deletions(-)

arch/x86/kernel/cpu/amd.c +30 ~~-40~~

index 8d90f5f6b0d9..7cbb108afaf4 100644
@@ -70,12 +70,6 @@ static const int amd_erratum_383[] =
 static const int amd_erratum_1054[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
 
-static const int amd_zenbleed[] =
-	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
-			   AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
-			   AMD_MODEL_RANGE(0x17, 0x90, 0x0, 0x91, 0xf),
-			   AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
-
 static const int amd_div0[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf),
 			   AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf));

@@ -1039,33 +1033,6 @@ static void init_amd_zen(struct cpuinfo_x86 *c)
 
 }
 
-static void init_amd_zen2(struct cpuinfo_x86 *c)
-{
-	init_amd_zen_common();
-	init_spectral_chicken(c);
-	fix_erratum_1386(c);
-}
-
-static void init_amd_zen3(struct cpuinfo_x86 *c)
-{
-	init_amd_zen_common();
-
-	if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
-		/*
-		 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
-		 * Branch Type Confusion, but predate the allocation of the
-		 * BTC_NO bit.
-		 */
-		if (!cpu_has(c, X86_FEATURE_BTC_NO))
-			set_cpu_cap(c, X86_FEATURE_BTC_NO);
-	}
-}
-
-static void init_amd_zen4(struct cpuinfo_x86 *c)
-{
-	init_amd_zen_common();
-}
-
 static bool cpu_has_zenbleed_microcode(void)
 {
 	u32 good_rev = 0;

@@ -1087,11 +1054,8 @@ static bool cpu_has_zenbleed_microcode(void)
 	return true;
 }
 
-static void zenbleed_check(struct cpuinfo_x86 *c)
+static void zen2_zenbleed_check(struct cpuinfo_x86 *c)
 {
-	if (!cpu_has_amd_erratum(c, amd_zenbleed))
-		return;
-
 	if (cpu_has(c, X86_FEATURE_HYPERVISOR))
 		return;

@@ -1106,6 +1070,34 @@ static void zenbleed_check(struct cpuinfo_x86 *c)
 	}
 }
 
+static void init_amd_zen2(struct cpuinfo_x86 *c)
+{
+	init_amd_zen_common();
+	init_spectral_chicken(c);
+	fix_erratum_1386(c);
+	zen2_zenbleed_check(c);
+}
+
+static void init_amd_zen3(struct cpuinfo_x86 *c)
+{
+	init_amd_zen_common();
+
+	if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
+		/*
+		 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
+		 * Branch Type Confusion, but predate the allocation of the
+		 * BTC_NO bit.
+		 */
+		if (!cpu_has(c, X86_FEATURE_BTC_NO))
+			set_cpu_cap(c, X86_FEATURE_BTC_NO);
+	}
+}
+
+static void init_amd_zen4(struct cpuinfo_x86 *c)
+{
+	init_amd_zen_common();
+}
+
 static void init_amd(struct cpuinfo_x86 *c)
 {
 	u64 vm_cr;

@@ -1227,8 +1219,6 @@ static void init_amd(struct cpuinfo_x86 *c)
 	    cpu_has(c, X86_FEATURE_AUTOIBRS))
 		WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
 
-	zenbleed_check(c);
-
 	if (cpu_has_amd_erratum(c, amd_div0)) {
 		pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
 		setup_force_cpu_bug(X86_BUG_DIV0);

@@ -1390,7 +1380,7 @@ static void zenbleed_check_cpu(void *unused)
 {
 	struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
 
-	zenbleed_check(c);
+	zen2_zenbleed_check(c);
 }
 
 void amd_check_microcode(void)

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

Nikolay Borisov

2023-11-20 12:54 UTC #23 lore raw

Re: [PATCH 07/13] x86/CPU/AMD: Move Zenbleed check to the Zen2 init function

Quoted 49 lines · Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

Prefix it properly so that it is clear which generation it is dealing with.

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
  arch/x86/kernel/cpu/amd.c | 70 +++++++++++++++++----------------------
  1 file changed, 30 insertions(+), 40 deletions(-)

arch/x86/kernel/cpu/amd.c +0 ~~-22~~

index 8d90f5f6b0d9..7cbb108afaf4 100644
@@ -70,12 +70,6 @@ static const int amd_erratum_383[] =
  static const int amd_erratum_1054[] =
  	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
 
-static const int amd_zenbleed[] =
-	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
-			   AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
-			   AMD_MODEL_RANGE(0x17, 0x90, 0x0, 0x91, 0xf),
-			   AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
-
  static const int amd_div0[] =
  	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf),
  			   AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf));

@@ -1039,33 +1033,6 @@ static void init_amd_zen(struct cpuinfo_x86 *c)
 
  }
 
-static void init_amd_zen2(struct cpuinfo_x86 *c)
-{
-	init_amd_zen_common();
-	init_spectral_chicken(c);
-	fix_erratum_1386(c);
-}
-
-static void init_amd_zen3(struct cpuinfo_x86 *c)
-{
-	init_amd_zen_common();
-
-	if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
-		/*
-		 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
-		 * Branch Type Confusion, but predate the allocation of the
-		 * BTC_NO bit.

arch/x86/kernel/cpu/amd.c static void init_amd_zen(struct cpuinfo_x86 *c) · line 1067

Quoted 10 lines

arch/x86/kernel/cpu/amd.c +0 ~~-10~~

-		 */
-		if (!cpu_has(c, X86_FEATURE_BTC_NO))
-			set_cpu_cap(c, X86_FEATURE_BTC_NO);
-	}
-}
-
-static void init_amd_zen4(struct cpuinfo_x86 *c)
-{
-	init_amd_zen_common();
-}

nit: If you initially introduced the zen-specific functions right after zenbleed_check you would have avoided the function move in this patch which would have reduced the overall diff.

<snip>

Borislav Petkov

author maintainer

2023-11-21 10:42 UTC #24 lore raw

Re: [PATCH 07/13] x86/CPU/AMD: Move Zenbleed check to the Zen2 init function

Quoted 3 lines · Nikolay Borisov

nit: If you initially introduced the zen-specific functions right after zenbleed_check you would have avoided the function move in this patch which would have reduced the overall diff.

Yap, done, good point.

And thanks for the review.

Signature · 4 lines

Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-11-29 11:22 UTC #25 lore raw

[tip: x86/cpu] x86/CPU/AMD: Move Zenbleed check to the Zen2 init function

In reply to Borislav Petkov

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     f69759be251dce722942594fbc62e53a40822a82
Gitweb:        https://git.kernel.org/tip/f69759be251dce722942594fbc62e53a40822a82
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Wed, 01 Nov 2023 12:38:35 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Wed, 29 Nov 2023 12:12:34 +01:00

x86/CPU/AMD: Move Zenbleed check to the Zen2 init function

Prefix it properly so that it is clear which generation it is dealing with.

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Link http://lore.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/cpu/amd.c | 16 +++-------------
 1 file changed, 3 insertions(+), 13 deletions(-)

arch/x86/kernel/cpu/amd.c +3 ~~-13~~

index f53e0a2..3c3b4c1 100644
@@ -70,12 +70,6 @@ static const int amd_erratum_383[] =
 static const int amd_erratum_1054[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
 
-static const int amd_zenbleed[] =
-	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
-			   AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
-			   AMD_MODEL_RANGE(0x17, 0x90, 0x0, 0x91, 0xf),
-			   AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
-
 static const int amd_div0[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf),
 			   AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf));

@@ -1059,11 +1053,8 @@ static bool cpu_has_zenbleed_microcode(void)
 	return true;
 }
 
-static void zenbleed_check(struct cpuinfo_x86 *c)
+static void zen2_zenbleed_check(struct cpuinfo_x86 *c)
 {
-	if (!cpu_has_amd_erratum(c, amd_zenbleed))
-		return;
-
 	if (cpu_has(c, X86_FEATURE_HYPERVISOR))
 		return;

@@ -1084,6 +1075,7 @@ static void init_amd_zen2(struct cpuinfo_x86 *c)
 	init_amd_zen_common();
 	init_spectral_chicken(c);
 	fix_erratum_1386(c);
+	zen2_zenbleed_check(c);
 }
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)

@@ -1227,8 +1219,6 @@ static void init_amd(struct cpuinfo_x86 *c)
 	    cpu_has(c, X86_FEATURE_AUTOIBRS))
 		WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
 
-	zenbleed_check(c);
-
 	if (cpu_has_amd_erratum(c, amd_div0)) {
 		pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
 		setup_force_cpu_bug(X86_BUG_DIV0);

@@ -1393,7 +1383,7 @@ static void zenbleed_check_cpu(void *unused)
 {
 	struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
 
-	zenbleed_check(c);
+	zen2_zenbleed_check(c);
 }
 
 void amd_check_microcode(void)

Borislav Petkov

author maintainer

2023-11-20 10:43 UTC #26 lore raw

PATCH 8/13 x86/CPU/AMD: Move the DIV0 bug detection to the Zen1 init function

In reply to Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
 arch/x86/kernel/cpu/amd.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

arch/x86/kernel/cpu/amd.c +2 -9

index 7cbb108afaf4..43d6a6da7591 100644
@@ -70,10 +70,6 @@ static const int amd_erratum_383[] =
 static const int amd_erratum_1054[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
 
-static const int amd_div0[] =
-	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf),
-			   AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf));
-
 static const int amd_erratum_1485[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
 			   AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));

@@ -1031,6 +1027,8 @@ static void init_amd_zen(struct cpuinfo_x86 *c)
 			set_cpu_cap(c, X86_FEATURE_CPB);
 	}
 
+	pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
+	setup_force_cpu_bug(X86_BUG_DIV0);
 }
 
 static bool cpu_has_zenbleed_microcode(void)

@@ -1219,11 +1217,6 @@ static void init_amd(struct cpuinfo_x86 *c)
 	    cpu_has(c, X86_FEATURE_AUTOIBRS))
 		WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
 
-	if (cpu_has_amd_erratum(c, amd_div0)) {
-		pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
-		setup_force_cpu_bug(X86_BUG_DIV0);
-	}
-
 	if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
 	     cpu_has_amd_erratum(c, amd_erratum_1485))
 		msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-11-29 11:22 UTC #27 lore raw

[tip: x86/cpu] x86/CPU/AMD: Move the DIV0 bug detection to the Zen1 init function

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     bfff3c6692ce64fa9d86eb829d18229c307a0855
Gitweb:        https://git.kernel.org/tip/bfff3c6692ce64fa9d86eb829d18229c307a0855
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Wed, 01 Nov 2023 12:52:01 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Wed, 29 Nov 2023 12:12:42 +01:00

x86/CPU/AMD: Move the DIV0 bug detection to the Zen1 init function

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Reviewed-by Nikolay Borisov <[email protected]>

Link http://lore.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/cpu/amd.c | 13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

arch/x86/kernel/cpu/amd.c +3 ~~-10~~

index 3c3b4c1..13ad44b 100644
@@ -70,10 +70,6 @@ static const int amd_erratum_383[] =
 static const int amd_erratum_1054[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
 
-static const int amd_div0[] =
-	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf),
-			   AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf));
-
 static const int amd_erratum_1485[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
 			   AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));

@@ -1030,6 +1026,9 @@ static void init_amd_zen(struct cpuinfo_x86 *c)
 		if (!cpu_has(c, X86_FEATURE_CPB))
 			set_cpu_cap(c, X86_FEATURE_CPB);
 	}
+
+	pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
+	setup_force_cpu_bug(X86_BUG_DIV0);
 }
 
 static bool cpu_has_zenbleed_microcode(void)

@@ -1067,7 +1066,6 @@ static void zen2_zenbleed_check(struct cpuinfo_x86 *c)
 	} else {
 		msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
 	}
-
 }
 
 static void init_amd_zen2(struct cpuinfo_x86 *c)

@@ -1219,11 +1217,6 @@ static void init_amd(struct cpuinfo_x86 *c)
 	    cpu_has(c, X86_FEATURE_AUTOIBRS))
 		WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
 
-	if (cpu_has_amd_erratum(c, amd_div0)) {
-		pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
-		setup_force_cpu_bug(X86_BUG_DIV0);
-	}
-
 	if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
 	     cpu_has_amd_erratum(c, amd_erratum_1485))
 		msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);

Borislav Petkov

author maintainer

2023-11-20 10:43 UTC #28 lore raw

PATCH 9/13 x86/CPU/AMD: Get rid of amd_erratum_1054[]

In reply to Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
 arch/x86/kernel/cpu/amd.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

arch/x86/kernel/cpu/amd.c +1 -5

index 43d6a6da7591..62aa99b5d6c8 100644
@@ -66,10 +66,6 @@ static const int amd_erratum_400[] =
 static const int amd_erratum_383[] =
 	AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
 
-/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
-static const int amd_erratum_1054[] =
-	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-
 static const int amd_erratum_1485[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
 			   AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));

@@ -1201,7 +1197,7 @@ static void init_amd(struct cpuinfo_x86 *c)
 	 * Counter May Be Inaccurate".
 	 */
 	if (cpu_has(c, X86_FEATURE_IRPERF) &&
-	    !cpu_has_amd_erratum(c, amd_erratum_1054))
+	    (boot_cpu_has(X86_FEATURE_ZEN) && c->x86_model > 0x2f))
 		msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
 
 	check_null_seg_clears_base(c);

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-11-29 11:22 UTC #29 lore raw

[tip: x86/cpu] x86/CPU/AMD: Get rid of amd_erratum_1054[]

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     54c33e23f75d5c9925495231c57d3319336722ef
Gitweb:        https://git.kernel.org/tip/54c33e23f75d5c9925495231c57d3319336722ef
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Fri, 03 Nov 2023 19:53:49 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Wed, 29 Nov 2023 12:12:55 +01:00

x86/CPU/AMD: Get rid of amd_erratum_1054[]

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Reviewed-by Nikolay Borisov <[email protected]>

Link http://lore.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/cpu/amd.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

arch/x86/kernel/cpu/amd.c +1 -5

index 13ad44b..219ae7e 100644
@@ -66,10 +66,6 @@ static const int amd_erratum_400[] =
 static const int amd_erratum_383[] =
 	AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
 
-/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
-static const int amd_erratum_1054[] =
-	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-
 static const int amd_erratum_1485[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
 			   AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));

@@ -1201,7 +1197,7 @@ static void init_amd(struct cpuinfo_x86 *c)
 	 * Counter May Be Inaccurate".
 	 */
 	if (cpu_has(c, X86_FEATURE_IRPERF) &&
-	    !cpu_has_amd_erratum(c, amd_erratum_1054))
+	    (boot_cpu_has(X86_FEATURE_ZEN) && c->x86_model > 0x2f))
 		msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
 
 	check_null_seg_clears_base(c);

Borislav Petkov

author maintainer

2023-11-20 10:44 UTC #30 lore raw

PATCH 10/13 x86/CPU/AMD: Get rid of amd_erratum_383[]

In reply to Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

Set it in init_amd_gh() unconditionally as that is the F10h init function.

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
 arch/x86/kernel/cpu/amd.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

arch/x86/kernel/cpu/amd.c +1 -5

index 62aa99b5d6c8..3e25fa9c5275 100644
@@ -63,9 +63,6 @@ static const int amd_erratum_400[] =
 	AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
 			    AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
 
-static const int amd_erratum_383[] =
-	AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
-
 static const int amd_erratum_1485[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
 			   AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));

@@ -876,8 +873,7 @@ static void init_amd_gh(struct cpuinfo_x86 *c)
 	 */
 	msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
 
-	if (cpu_has_amd_erratum(c, amd_erratum_383))
-		set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
+	set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
 }
 
 static void init_amd_ln(struct cpuinfo_x86 *c)

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-11-29 11:22 UTC #31 lore raw

[tip: x86/cpu] x86/CPU/AMD: Get rid of amd_erratum_383[]

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     1709528f73d475d3c9ec514bc0dee0b41cadd871
Gitweb:        https://git.kernel.org/tip/1709528f73d475d3c9ec514bc0dee0b41cadd871
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Fri, 03 Nov 2023 19:58:53 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Wed, 29 Nov 2023 12:13:08 +01:00

x86/CPU/AMD: Get rid of amd_erratum_383[]

Set it in init_amd_gh() unconditionally as that is the F10h init function.

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Reviewed-by Nikolay Borisov <[email protected]>

Link http://lore.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/cpu/amd.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

arch/x86/kernel/cpu/amd.c +1 -5

index 219ae7e..7ab7f98 100644
@@ -63,9 +63,6 @@ static const int amd_erratum_400[] =
 	AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
 			    AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
 
-static const int amd_erratum_383[] =
-	AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
-
 static const int amd_erratum_1485[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
 			   AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));

@@ -876,8 +873,7 @@ static void init_amd_gh(struct cpuinfo_x86 *c)
 	 */
 	msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
 
-	if (cpu_has_amd_erratum(c, amd_erratum_383))
-		set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
+	set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
 }
 
 static void init_amd_ln(struct cpuinfo_x86 *c)

Borislav Petkov

author maintainer

2023-11-20 10:44 UTC #32 lore raw

PATCH 11/13 x86/CPU/AMD: Get rid of amd_erratum_400[]

In reply to Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

Setting X86_BUG_AMD_E400 in init_amd() is early enough.

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
 arch/x86/kernel/cpu/amd.c | 33 ++++++++++++++++++++-------------
 1 file changed, 20 insertions(+), 13 deletions(-)

arch/x86/kernel/cpu/amd.c +20 ~~-13~~

index 3e25fa9c5275..f913ca245639 100644
@@ -59,10 +59,6 @@ static u32 nodes_per_socket = 1;
 #define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)
 #define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)
 
-static const int amd_erratum_400[] =
-	AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-			    AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
-
 static const int amd_erratum_1485[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
 			   AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));

@@ -765,15 +761,6 @@ static void early_init_amd(struct cpuinfo_x86 *c)
 	if (c->x86 == 0x16 && c->x86_model <= 0xf)
 		msr_set_bit(MSR_AMD64_LS_CFG, 15);
 
-	/*
-	 * Check whether the machine is affected by erratum 400. This is
-	 * used to select the proper idle routine and to enable the check
-	 * whether the machine is affected in arch_post_acpi_init(), which
-	 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
-	 */
-	if (cpu_has_amd_erratum(c, amd_erratum_400))
-		set_cpu_bug(c, X86_BUG_AMD_E400);
-
 	early_detect_mem_encrypt(c);
 
 	/* Re-enable TopologyExtensions if switched off by BIOS */

@@ -840,6 +827,16 @@ static void init_amd_k8(struct cpuinfo_x86 *c)
 	msr_set_bit(MSR_K7_HWCR, 6);
 #endif
 	set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
+
+	/*
+	 * Check models and steppings affected by erratum 400. This is
+	 * used to select the proper idle routine and to enable the
+	 * check whether the machine is affected in arch_post_acpi_subsys_init()
+	 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
+	 */
+	if (c->x86_model > 0x41 ||
+	    (c->x86_model == 0x41 && c->x86_stepping >= 0x2))
+		setup_force_cpu_bug(X86_BUG_AMD_E400);
 }
 
 static void init_amd_gh(struct cpuinfo_x86 *c)

@@ -874,6 +871,16 @@ static void init_amd_gh(struct cpuinfo_x86 *c)
 	msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
 
 	set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
+
+	/*
+	 * Check models and steppings affected by erratum 400. This is
+	 * used to select the proper idle routine and to enable the
+	 * check whether the machine is affected in arch_post_acpi_subsys_init()
+	 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
+	 */
+	if (c->x86_model > 0x2 ||
+	    (c->x86_model == 0x2 && c->x86_stepping >= 0x1))
+		setup_force_cpu_bug(X86_BUG_AMD_E400);
 }
 
 static void init_amd_ln(struct cpuinfo_x86 *c)

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-11-29 11:22 UTC #33 lore raw

[tip: x86/cpu] x86/CPU/AMD: Get rid of amd_erratum_400[]

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     b3ffbbd282d4eb79f489853a171242c2a06bd8b8
Gitweb:        https://git.kernel.org/tip/b3ffbbd282d4eb79f489853a171242c2a06bd8b8
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Fri, 03 Nov 2023 23:20:11 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Wed, 29 Nov 2023 12:13:23 +01:00

x86/CPU/AMD: Get rid of amd_erratum_400[]

Setting X86_BUG_AMD_E400 in init_amd() is early enough.

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Reviewed-by Nikolay Borisov <[email protected]>

Link http://lore.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/cpu/amd.c | 33 ++++++++++++++++++++-------------
 1 file changed, 20 insertions(+), 13 deletions(-)

arch/x86/kernel/cpu/amd.c +20 ~~-13~~

index 7ab7f98..550ac25 100644
@@ -59,10 +59,6 @@ static u32 nodes_per_socket = 1;
 #define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)
 #define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)
 
-static const int amd_erratum_400[] =
-	AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-			    AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
-
 static const int amd_erratum_1485[] =
 	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
 			   AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));

@@ -765,15 +761,6 @@ static void early_init_amd(struct cpuinfo_x86 *c)
 	if (c->x86 == 0x16 && c->x86_model <= 0xf)
 		msr_set_bit(MSR_AMD64_LS_CFG, 15);
 
-	/*
-	 * Check whether the machine is affected by erratum 400. This is
-	 * used to select the proper idle routine and to enable the check
-	 * whether the machine is affected in arch_post_acpi_init(), which
-	 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
-	 */
-	if (cpu_has_amd_erratum(c, amd_erratum_400))
-		set_cpu_bug(c, X86_BUG_AMD_E400);
-
 	early_detect_mem_encrypt(c);
 
 	/* Re-enable TopologyExtensions if switched off by BIOS */

@@ -840,6 +827,16 @@ static void init_amd_k8(struct cpuinfo_x86 *c)
 	msr_set_bit(MSR_K7_HWCR, 6);
 #endif
 	set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
+
+	/*
+	 * Check models and steppings affected by erratum 400. This is
+	 * used to select the proper idle routine and to enable the
+	 * check whether the machine is affected in arch_post_acpi_subsys_init()
+	 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
+	 */
+	if (c->x86_model > 0x41 ||
+	    (c->x86_model == 0x41 && c->x86_stepping >= 0x2))
+		setup_force_cpu_bug(X86_BUG_AMD_E400);
 }
 
 static void init_amd_gh(struct cpuinfo_x86 *c)

@@ -874,6 +871,16 @@ static void init_amd_gh(struct cpuinfo_x86 *c)
 	msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
 
 	set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
+
+	/*
+	 * Check models and steppings affected by erratum 400. This is
+	 * used to select the proper idle routine and to enable the
+	 * check whether the machine is affected in arch_post_acpi_subsys_init()
+	 * which sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
+	 */
+	if (c->x86_model > 0x2 ||
+	    (c->x86_model == 0x2 && c->x86_stepping >= 0x1))
+		setup_force_cpu_bug(X86_BUG_AMD_E400);
 }
 
 static void init_amd_ln(struct cpuinfo_x86 *c)

Borislav Petkov

author maintainer

2023-11-20 10:44 UTC #34 lore raw

PATCH 12/13 x86/CPU/AMD: Get rid of amd_erratum_1485[]

In reply to Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
 arch/x86/kernel/cpu/amd.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

arch/x86/kernel/cpu/amd.c +3 -8

index f913ca245639..54e07c9b1292 100644
@@ -59,10 +59,6 @@ static u32 nodes_per_socket = 1;
 #define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)
 #define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)
 
-static const int amd_erratum_1485[] =
-	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
-			   AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
-
 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
 {
 	int osvw_id = *erratum++;

@@ -1093,6 +1089,9 @@ static void init_amd_zen3(struct cpuinfo_x86 *c)
 static void init_amd_zen4(struct cpuinfo_x86 *c)
 {
 	init_amd_zen_common();
+
+	if (!cpu_has(c, X86_FEATURE_HYPERVISOR))
+		msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
 }
 
 static void init_amd(struct cpuinfo_x86 *c)

@@ -1215,10 +1214,6 @@ static void init_amd(struct cpuinfo_x86 *c)
 	if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
 	    cpu_has(c, X86_FEATURE_AUTOIBRS))
 		WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
-
-	if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
-	     cpu_has_amd_erratum(c, amd_erratum_1485))
-		msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
 }
 
 #ifdef CONFIG_X86_32

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-11-29 11:22 UTC #35 lore raw

[tip: x86/cpu] x86/CPU/AMD: Get rid of amd_erratum_1485[]

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     794c68b20408bb6899f90314e36e256924cc85a1
Gitweb:        https://git.kernel.org/tip/794c68b20408bb6899f90314e36e256924cc85a1
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Fri, 03 Nov 2023 23:21:56 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Wed, 29 Nov 2023 12:13:31 +01:00

x86/CPU/AMD: Get rid of amd_erratum_1485[]

No functional changes.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Reviewed-by Nikolay Borisov <[email protected]>

Link http://lore.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/cpu/amd.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

arch/x86/kernel/cpu/amd.c +3 -8

index 550ac25..f8be7ac 100644
@@ -59,10 +59,6 @@ static u32 nodes_per_socket = 1;
 #define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)
 #define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)
 
-static const int amd_erratum_1485[] =
-	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
-			   AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
-
 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
 {
 	int osvw_id = *erratum++;

@@ -1093,6 +1089,9 @@ static void init_amd_zen3(struct cpuinfo_x86 *c)
 static void init_amd_zen4(struct cpuinfo_x86 *c)
 {
 	init_amd_zen_common();
+
+	if (!cpu_has(c, X86_FEATURE_HYPERVISOR))
+		msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
 }
 
 static void init_amd(struct cpuinfo_x86 *c)

@@ -1216,10 +1215,6 @@ static void init_amd(struct cpuinfo_x86 *c)
 	    cpu_has(c, X86_FEATURE_AUTOIBRS))
 		WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
 
-	if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
-	     cpu_has_amd_erratum(c, amd_erratum_1485))
-		msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
-
 	/* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */
 	clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
 }

Borislav Petkov

author maintainer

2023-11-20 10:44 UTC #36 lore raw

PATCH 13/13 x86/CPU/AMD: Drop now unused CPU erratum checking function

In reply to Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>

Bye bye.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

---
 arch/x86/kernel/cpu/amd.c | 56 ---------------------------------------
 1 file changed, 56 deletions(-)

arch/x86/kernel/cpu/amd.c +0 ~~-56~~

index 54e07c9b1292..a363de80ce28 100644
@@ -34,62 +34,6 @@
  */
 static u32 nodes_per_socket = 1;
 
-/*
- * AMD errata checking
- *
- * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
- * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
- * have an OSVW id assigned, which it takes as first argument. Both take a
- * variable number of family-specific model-stepping ranges created by
- * AMD_MODEL_RANGE().
- *
- * Example:
- *
- * const int amd_erratum_319[] =
- *	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
- *			   AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
- *			   AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
- */
-
-#define AMD_LEGACY_ERRATUM(...)		{ -1, __VA_ARGS__, 0 }
-#define AMD_OSVW_ERRATUM(osvw_id, ...)	{ osvw_id, __VA_ARGS__, 0 }
-#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-	((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
-#define AMD_MODEL_RANGE_FAMILY(range)	(((range) >> 24) & 0xff)
-#define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)
-#define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)
-
-static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
-{
-	int osvw_id = *erratum++;
-	u32 range;
-	u32 ms;
-
-	if (osvw_id >= 0 && osvw_id < 65536 &&
-	    cpu_has(cpu, X86_FEATURE_OSVW)) {
-		u64 osvw_len;
-
-		rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-		if (osvw_id < osvw_len) {
-			u64 osvw_bits;
-
-			rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-			    osvw_bits);
-			return osvw_bits & (1ULL << (osvw_id & 0x3f));
-		}
-	}
-
-	/* OSVW unavailable or ID unknown, match family-model-stepping range */
-	ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-	while ((range = *erratum++))
-		if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-		    (ms >= AMD_MODEL_RANGE_START(range)) &&
-		    (ms <= AMD_MODEL_RANGE_END(range)))
-			return true;
-
-	return false;
-}
-
 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
 {
 	u32 gprs[8] = { 0 };

Signature · 1 line

2.42.0.rc0.25.ga82fb66fed25

tip-bot2 for Borislav Petkov (AMD)

merge bot Applied

2023-11-29 11:22 UTC #37 lore raw

[tip: x86/cpu] x86/CPU/AMD: Drop now unused CPU erratum checking function

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     05f5f73936fa4c1bc0a852702edf53789398d278
Gitweb:        https://git.kernel.org/tip/05f5f73936fa4c1bc0a852702edf53789398d278
Author:        Borislav Petkov (AMD) <[email protected]>
AuthorDate:    Fri, 03 Nov 2023 23:40:48 +01:00
Committer:     Borislav Petkov (AMD) <[email protected]>
CommitterDate: Wed, 29 Nov 2023 12:13:53 +01:00

x86/CPU/AMD: Drop now unused CPU erratum checking function

Bye bye.

Signed-off-by Borislav Petkov (AMD) <[email protected]>

Reviewed-by Nikolay Borisov <[email protected]>

Link http://lore.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/cpu/amd.c | 56 +--------------------------------------
 1 file changed, 56 deletions(-)

arch/x86/kernel/cpu/amd.c +0 ~~-56~~

index f8be7ac..89bbb1a 100644
@@ -34,62 +34,6 @@
  */
 static u32 nodes_per_socket = 1;
 
-/*
- * AMD errata checking
- *
- * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
- * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
- * have an OSVW id assigned, which it takes as first argument. Both take a
- * variable number of family-specific model-stepping ranges created by
- * AMD_MODEL_RANGE().
- *
- * Example:
- *
- * const int amd_erratum_319[] =
- *	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
- *			   AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
- *			   AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
- */
-
-#define AMD_LEGACY_ERRATUM(...)		{ -1, __VA_ARGS__, 0 }
-#define AMD_OSVW_ERRATUM(osvw_id, ...)	{ osvw_id, __VA_ARGS__, 0 }
-#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-	((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
-#define AMD_MODEL_RANGE_FAMILY(range)	(((range) >> 24) & 0xff)
-#define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)
-#define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)
-
-static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
-{
-	int osvw_id = *erratum++;
-	u32 range;
-	u32 ms;
-
-	if (osvw_id >= 0 && osvw_id < 65536 &&
-	    cpu_has(cpu, X86_FEATURE_OSVW)) {
-		u64 osvw_len;
-
-		rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-		if (osvw_id < osvw_len) {
-			u64 osvw_bits;
-
-			rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-			    osvw_bits);
-			return osvw_bits & (1ULL << (osvw_id & 0x3f));
-		}
-	}
-
-	/* OSVW unavailable or ID unknown, match family-model-stepping range */
-	ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-	while ((range = *erratum++))
-		if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-		    (ms >= AMD_MODEL_RANGE_START(range)) &&
-		    (ms <= AMD_MODEL_RANGE_END(range)))
-			return true;
-
-	return false;
-}
-
 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
 {
 	u32 gprs[8] = { 0 };

Nikolay Borisov

Reviewed-by on the v1 series

2023-11-20 15:08 UTC #38 lore raw

In reply to Borislav Petkov

Quoted 25 lines · Borislav Petkov

From: "Borislav Petkov (AMD)" <[email protected]>
Add Zen generation flags which will be used to check on what type of Zen the kernel runs. Distribute the per-generation init work into the respective functions and cleanup amd.c properly.
As a result, drop the errata checking gunk which is not needed anymore.
There should be no functionality change resulting from these changes.
Borislav Petkov (AMD) (13):
x86/CPU/AMD: Add ZenX generations flags
x86/CPU/AMD: Carve out the erratum 1386 fix
x86/CPU/AMD: Move the Zen3 BTC_NO detection to the Zen3 init function x86/CPU/AMD: Move erratum 1076 fix into the Zen1 init function x86/CPU/AMD: Call the spectral chicken in the Zen2 init function x86/CPU/AMD: Rename init_amd_zn() to init_amd_zen_common() x86/CPU/AMD: Move Zenbleed check to the Zen2 init function x86/CPU/AMD: Move the DIV0 bug detection to the Zen1 init function x86/CPU/AMD: Get rid of amd_erratum_1054[]
x86/CPU/AMD: Get rid of amd_erratum_383[]
x86/CPU/AMD: Get rid of amd_erratum_400[]
x86/CPU/AMD: Get rid of amd_erratum_1485[]
x86/CPU/AMD: Drop now unused CPU erratum checking function

Quoted 4 lines

  arch/x86/include/asm/cpufeatures.h |   6 +-
  arch/x86/kernel/cpu/amd.c          | 266 ++++++++++++++---------------
  2 files changed, 135 insertions(+), 137 deletions(-)

The whole series LGTM:

Reviewed-by Nikolay Borisov <[email protected] >