FAILED: patch "[PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate" failed to apply to 6.6-stable tree
[email protected]
maintainerThe patch below does not apply to the 6.6-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.6.y
git checkout FETCH_HEAD
git cherry-pick -x e6861d8264cd43c5eb20196e53df36fd71ec5698
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2023121841-backspin-troubling-44cf@gregkh' --subject-prefix 'PATCH 6.6.y' HEAD^..
Possible dependencies:
e6861d8264cd ("drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select") 3072a24c778a ("drm/i915: Introduce crtc_state->enhanced_framing") 3dfeb80b3088 ("drm/i915: Fix FEC state dump")
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From e6861d8264cd43c5eb20196e53df36fd71ec5698 Mon Sep 17 00:00:00 2001
From: Jani Nikula <[email protected]>
Date: Tue, 5 Dec 2023 20:05:51 +0200
Subject: [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate
select
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The eDP 1.5 spec adds a clarification for eDP 1.4x:
Quoted 2 lines
For eDP v1.4x, if the Source device chooses the Main-Link rate by way of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as it can cause the panel to ignore the rate set method.
Moreover, 0 is a reserved value for DP_LINK_BW_SET, and should not be used.
v2: Improve the comments (Ville)
drivers/gpu/drm/i915/display/intel_dp_link_training.c +21 -10
@@ -650,19 +650,30 @@ intel_dp_update_link_bw_set(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state, u8 link_bw, u8 rate_select) { - u8 link_config[2]; + u8 lane_count = crtc_state->lane_count; -/* Write the link configuration data */ - link_config[0 ] = link_bw; - link_config[1 ] = crtc_state->lane_count;if (crtc_state->enhanced_framing) - link_config[1 ] |=DP_LANE_COUNT_ENHANCED_FRAME_EN ; -drm_dp_dpcd_write (&intel_dp->aux,DP_LINK_BW_SET , link_config,2 ); + lane_count |=DP_LANE_COUNT_ENHANCED_FRAME_EN ; -/* eDP 1.4 rate select method. */ -if (!link_bw) -drm_dp_dpcd_write (&intel_dp->aux,DP_LINK_RATE_SET , - &rate_select,1 ); +if (link_bw) { +/* DP and eDP v1.3 and earlier link bw set method. */ +u8 link_config[] = { link_bw, lane_count }; + +drm_dp_dpcd_write (&intel_dp->aux,DP_LINK_BW_SET , link_config, +ARRAY_SIZE (link_config)); + }else { +/* +* eDP v1.4 and later link rate set method. +* +* eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if +* DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET. +* +* eDP v1.5 sinks allow choosing either, and the last choice +* shall be active. +*/ +drm_dp_dpcd_writeb (&intel_dp->aux,DP_LANE_COUNT_SET , lane_count); +drm_dp_dpcd_writeb (&intel_dp->aux,DP_LINK_RATE_SET , rate_select); + } }/*