Skip to contentSkip to conversation

Add StarFive JH7110 SoC DSI support

PATCH Superseded Shengyang Chen 3 participants 7 messages Jan 9, 2024 – Jan 16, 2024

Subsystems (4)
Device tree bindings DRM drivers DRM misc DRM drivers for bridge chips

v2 of 4 Superseded Latest is v4 →

lore
Share & tools
lore

Shengyang Chen

author
#0 lore raw

v2 cover Add StarFive JH7110 SoC DSI support

This series is the series that attempts to support the CDNS DSI driver used to converts DPI to DSI. CDNS DSI is embedded in StarFive JH7110 SoC. The series has been tested on the VisionFive 2 board.

changes since v1:
- Rebased on tag v6.7.

patch 1:
- Changed the 'starfive,cdns-dsi' to 'starfve,jh7110-dsi'.
- Changed the compatible enum alphabetical order.
- Restrict other variants.
- Drop 'dsi_' prefix.

patch 2:
- Optimize the calculation process.
- Drop useless definition.

v1: https://patchwork.kernel.org/project/dri-devel/cover/[email protected]/

Keith Zhao (2):
dt-bindings: display: bridge: cdns: Add properties to support StarFive

    JH7110 SoC
  gpu: drm: bridge: cadence: Add a driver and platform ops for StarFive
    JH7110 SoC
 .../bindings/display/bridge/cdns,dsi.yaml     |  44 +++-
 MAINTAINERS                                   |   8 +
 drivers/gpu/drm/bridge/cadence/Kconfig        |   7 +
 drivers/gpu/drm/bridge/cadence/Makefile       |   1 +
 .../gpu/drm/bridge/cadence/cdns-dsi-core.c    |  29 ++-
 .../gpu/drm/bridge/cadence/cdns-dsi-core.h    |  21 ++
 .../gpu/drm/bridge/cadence/cdns-dsi-jh7110.c  | 193 ++++++++++++++++++
 .../gpu/drm/bridge/cadence/cdns-dsi-jh7110.h  |  16 ++
 8 files changed, 316 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.c
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.h
Signature · 1 line
2.17.1
author
#1 lore raw

PATCH v2 1/2 dt-bindings: display: bridge: cdns: Add properties to support StarFive JH7110 SoC

From: Keith Zhao <[email protected]>

Add properties in CDNS DSI yaml file to match with CDNS DSI module in StarFive JH7110 SoC.

Signed-off-by Keith Zhao <[email protected]>
---
 .../bindings/display/bridge/cdns,dsi.yaml     | 44 ++++++++++++++++++-
 1 file changed, 42 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +42 -2
index 23060324d16e..da091e105794 100644
@@ -16,6 +16,7 @@ properties:
   compatible:
     enum:
       - cdns,dsi
+      - starfve,jh7110-dsi
       - ti,j721e-dsi
 
   reg:

@@ -27,14 +28,20 @@ properties:
           Register block for wrapper settings registers in case of TI J7 SoCs.
 
   clocks:
+    minItems: 2
     items:
       - description: PSM clock, used by the IP
       - description: sys clock, used by the IP
+      - description: apb clock, used by the IP
+      - description: txesc clock, used by the IP
 
   clock-names:
+    minItems: 2
     items:
       - const: dsi_p_clk
       - const: dsi_sys_clk
+      - const: apb
+      - const: txesc
 
   phys:
     maxItems: 1

@@ -46,10 +53,21 @@ properties:
     maxItems: 1
 
   resets:
-    maxItems: 1
+    minItems: 1
+    items:
+      - description: dsi sys reset line
+      - description: dsi dpi reset line
+      - description: dsi apb reset line
+      - description: dsi txesc reset line
+      - description: dsi txbytehs reset line
 
   reset-names:
-    const: dsi_p_rst
+    items:
+      - const: dsi_p_rst
+      - const: dpi
+      - const: apb
+      - const: txesc
+      - const: txbytehs
 
   ports:
     $ref: /schemas/graph.yaml#/properties/ports

@@ -90,6 +108,28 @@ allOf:
         reg:
           maxItems: 1
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: starfive,jh7110-dsi
+    then:
+      properties:
+        clocks:
+          minItems: 4
+          maxItems: 4
+        resets:
+          minItems: 5
+          maxItems: 5
+      required:
+        - reset-names
+    else:
+      properties:
+        clocks:
+          maxItems: 2
+        resets:
+          maxItems: 1
+
 required:
   - compatible
   - reg
Signature · 1 line
2.17.1
#2 lore raw

Re: [PATCH v2 1/2] dt-bindings: display: bridge: cdns: Add properties to support StarFive JH7110 SoC

Quoted 4 lines · Shengyang Chen

From: Keith Zhao <[email protected]>

Add properties in CDNS DSI yaml file to match with CDNS DSI module in StarFive JH7110 SoC.

Please wrap commit message according to Linux coding style / submission process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597

Subject: Make it concise, like: "Add StarFive JH7110 SoC display bridge or something".

Quoted 70 lines
Signed-off-by Keith Zhao <[email protected]>
---
 .../bindings/display/bridge/cdns,dsi.yaml     | 44 ++++++++++++++++++-
 1 file changed, 42 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +23 -2
index 23060324d16e..da091e105794 100644
@@ -16,6 +16,7 @@ properties:
   compatible:
     enum:
       - cdns,dsi
+      - starfve,jh7110-dsi
       - ti,j721e-dsi
 
   reg:

@@ -27,14 +28,20 @@ properties:
           Register block for wrapper settings registers in case of TI J7 SoCs.
 
   clocks:
+    minItems: 2
     items:
       - description: PSM clock, used by the IP
       - description: sys clock, used by the IP
+      - description: apb clock, used by the IP
+      - description: txesc clock, used by the IP
 
   clock-names:
+    minItems: 2
     items:
       - const: dsi_p_clk
       - const: dsi_sys_clk
+      - const: apb
+      - const: txesc
 
   phys:
     maxItems: 1

@@ -46,10 +53,21 @@ properties:
     maxItems: 1
 
   resets:
-    maxItems: 1
+    minItems: 1
+    items:
+      - description: dsi sys reset line
+      - description: dsi dpi reset line
+      - description: dsi apb reset line
+      - description: dsi txesc reset line
+      - description: dsi txbytehs reset line
 
   reset-names:
-    const: dsi_p_rst
+    items:
+      - const: dsi_p_rst
+      - const: dpi
+      - const: apb
+      - const: txesc
+      - const: txbytehs
 
   ports:
     $ref: /schemas/graph.yaml#/properties/ports

@@ -90,6 +108,28 @@ allOf:
         reg:
           maxItems: 1
 
+  - if:
+      properties:
+        compatible:

Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml allOf: · line 123

Quoted 10 lines
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +10 -0
+          contains:
+            const: starfive,jh7110-dsi
+    then:
+      properties:
+        clocks:
+          minItems: 4
+          maxItems: 4
+        resets:
+          minItems: 5
+          maxItems: 5

Missing constraints for xxx-names.

Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml allOf: · line 131

Quoted 8 lines
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +8 -0
+      required:
+        - reset-names
+    else:
+      properties:
+        clocks:
+          maxItems: 2
+        resets:
+          maxItems: 1

Same problem.

Best regards,
Krzysztof

author
#3 lore raw

RE: [PATCH v2 1/2] dt-bindings: display: bridge: cdns: Add properties to support StarFive JH7110 SoC

Hi, Krzysztof

Thanks for review and comment.

Quoted 26 lines

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: 2024年1月11日 5:06
To: Shengyang Chen <[email protected]>; [email protected]; [email protected]
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Changhuang Liang <[email protected]>; Keith Zhao <[email protected]>; Jack Zhu <[email protected]>; [email protected]
Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: cdns: Add properties to support StarFive JH7110 SoC

Quoted 4 lines · Shengyang Chen

From: Keith Zhao <[email protected]>

Add properties in CDNS DSI yaml file to match with CDNS DSI module in StarFive JH7110 SoC.

Quoted 8 lines

Please wrap commit message according to Linux coding style / submission process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submi
tting-patches.rst#L597

Subject: Make it concise, like: "Add StarFive JH7110 SoC display bridge or something".

ok, will follow up this issue.
thanks for suggestion.

Quoted 70 lines
Quoted 21 lines
Signed-off-by Keith Zhao <[email protected]>
---
 .../bindings/display/bridge/cdns,dsi.yaml     | 44 ++++++++++++++++++-
 1 file changed, 42 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml index 23060324d16e..da091e105794 100644

Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +1 -0
@@ -16,6 +16,7 @@ properties:
   compatible:
     enum:
       - cdns,dsi
+      - starfve,jh7110-dsi
       - ti,j721e-dsi
 
   reg:

Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml properties: · line 28

Quoted 1 line
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +0 -0
@@ -27,14 +28,20 @@ properties:
           Register block for wrapper settings registers in case of TI J7

SoCs.

Quoted 47 lines
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +19 -2
   clocks:
+    minItems: 2
     items:
       - description: PSM clock, used by the IP
       - description: sys clock, used by the IP
+      - description: apb clock, used by the IP
+      - description: txesc clock, used by the IP
 
   clock-names:
+    minItems: 2
     items:
       - const: dsi_p_clk
       - const: dsi_sys_clk
+      - const: apb
+      - const: txesc
 
   phys:
     maxItems: 1

@@ -46,10 +53,21 @@ properties:
     maxItems: 1
 
   resets:
-    maxItems: 1
+    minItems: 1
+    items:
+      - description: dsi sys reset line
+      - description: dsi dpi reset line
+      - description: dsi apb reset line
+      - description: dsi txesc reset line
+      - description: dsi txbytehs reset line
 
   reset-names:
-    const: dsi_p_rst
+    items:
+      - const: dsi_p_rst
+      - const: dpi
+      - const: apb
+      - const: txesc
+      - const: txbytehs
 
   ports:
     $ref: /schemas/graph.yaml#/properties/ports

@@ -90,6 +108,28 @@ allOf:
         reg:
           maxItems: 1
Quoted 16 lines

Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml allOf: · line 123

Quoted 13 lines
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +13 -0
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: starfive,jh7110-dsi
+    then:
+      properties:
+        clocks:
+          minItems: 4
+          maxItems: 4
+        resets:
+          minItems: 5
+          maxItems: 5

Missing constraints for xxx-names.

ok, will fix it

Quoted 11 lines

Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml allOf: · line 131

Quoted 8 lines
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +8 -0
+      required:
+        - reset-names
+    else:
+      properties:
+        clocks:
+          maxItems: 2
+        resets:
+          maxItems: 1

Same problem.

ok, will fix it

Quoted 2 lines

Best regards,
Krzysztof

thanks.

Best Regards,
Shengyang

author
#4 lore raw

PATCH v2 2/2 gpu: drm: bridge: cadence: Add a driver and platform ops for StarFive JH7110 SoC

In reply to Shengyang Chen

From: Keith Zhao <[email protected]>

In order to fit CDNS DSI module in StarFive JH7110 SoC, The mainly modification is followed:

1.Add driver for StarFive JH7110 SoC to drive its CDNS DSI module. 2.Add platform ops in cdns-dsi.c for StarFive JH7110 SoC probing.

Signed-off-by Keith Zhao <[email protected]>
---
 MAINTAINERS                                   |   8 +
 drivers/gpu/drm/bridge/cadence/Kconfig        |   7 +
 drivers/gpu/drm/bridge/cadence/Makefile       |   1 +
 .../gpu/drm/bridge/cadence/cdns-dsi-core.c    |  29 ++-
 .../gpu/drm/bridge/cadence/cdns-dsi-core.h    |  21 ++
 .../gpu/drm/bridge/cadence/cdns-dsi-jh7110.c  | 193 ++++++++++++++++++
 .../gpu/drm/bridge/cadence/cdns-dsi-jh7110.h  |  16 ++
 7 files changed, 274 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.c
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.h
MAINTAINERS +8 -0
index d32920dd943f..a220ea04f5c4 100644
@@ -6847,6 +6847,14 @@ F:	Documentation/devicetree/bindings/display/solomon,ssd-common.yaml
 F:	Documentation/devicetree/bindings/display/solomon,ssd13*.yaml
 F:	drivers/gpu/drm/solomon/ssd130x*
 
+DRM DRIVERS FOR STARFIVE
+M:	Keith Zhao <[email protected]>
+M:	Shengyang Chen <[email protected]>
+L:	[email protected]
+S:	Maintained
+T:	git git://anongit.freedesktop.org/drm/drm-misc
+F:	drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110*
+
 DRM DRIVER FOR ST-ERICSSON MCDE
 M:	Linus Walleij <[email protected]>
 S:	Maintained
drivers/gpu/drm/bridge/cadence/Kconfig +7 -0
index cced81633ddc..ad9f572f4720 100644
@@ -19,6 +19,13 @@ config DRM_CDNS_DSI_J721E
 	help
 	  Support J721E Cadence DSI wrapper. The wrapper manages
 	  the routing of the DSS DPI signal to the Cadence DSI.
+
+config DRM_CDNS_DSI_JH7110
+	bool "JH7110 SOC Cadence DSI support"
+	default n
+	help
+	  Cadence DPI to DSI bridge which is embedded in the
+	  StarFive JH7110 SoC.
 endif
 
 config DRM_CDNS_MHDP8546
drivers/gpu/drm/bridge/cadence/Makefile +1 -0
index c95fd5b81d13..87f603a9f4ad 100644
@@ -2,6 +2,7 @@
 obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
 cdns-dsi-y := cdns-dsi-core.o
 cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
+cdns-dsi-$(CONFIG_DRM_CDNS_DSI_JH7110) += cdns-dsi-jh7110.o
 obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
 cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
 cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c +28 -1
index 7457d38622b0..a8f976f9eeed 100644
@@ -27,6 +27,10 @@
 #include "cdns-dsi-j721e.h"
 #endif
 
+#ifdef CONFIG_DRM_CDNS_DSI_JH7110
+#include "cdns-dsi-jh7110.h"
+#endif
+
 #define IP_CONF				0x0
 #define SP_HS_FIFO_DEPTH(x)		(((x) & GENMASK(30, 26)) >> 26)
 #define SP_LP_FIFO_DEPTH(x)		(((x) & GENMASK(25, 21)) >> 21)

@@ -552,6 +556,10 @@ static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,
 	/* data rate was in bytes/sec, convert to bits/sec. */
 	phy_cfg->hs_clk_rate = dlane_bps * 8;
 
+	if (dsi->platform_ops && dsi->platform_ops->update)
+		adj_dsi_htotal = dsi->platform_ops->update(dsi, dsi_cfg, phy_cfg,
+							   dpi_hz, dpi_htotal, dsi_htotal);
+
 	dsi_hfp_ext = adj_dsi_htotal - dsi_htotal;
 	dsi_cfg->hfp += dsi_hfp_ext;
 	dsi_cfg->htotal = dsi_htotal + dsi_hfp_ext;

@@ -683,7 +691,7 @@ static void cdns_dsi_bridge_post_disable(struct drm_bridge *bridge)
 	pm_runtime_put(dsi->base.dev);
 }
 
-static void cdns_dsi_hs_init(struct cdns_dsi *dsi)
+void cdns_dsi_hs_init(struct cdns_dsi *dsi)
 {
 	struct cdns_dsi_output *output = &dsi->output;
 	u32 status;

@@ -1026,6 +1034,14 @@ static ssize_t cdns_dsi_transfer(struct mipi_dsi_host *host,
 
 	cdns_dsi_init_link(dsi);
 
+	/*
+	 * on JH7110 SoC , when transfer dsi command ,
+	 * cdns_dsi_hs_init is needed.
+	 * or the final ret will be error value.
+	 */
+	if (dsi->platform_ops && dsi->platform_ops->transfer)
+		dsi->platform_ops->transfer(dsi);
+
 	ret = mipi_dsi_create_packet(&packet, msg);
 	if (ret)
 		goto out;

@@ -1142,6 +1158,9 @@ static int __maybe_unused cdns_dsi_resume(struct device *dev)
 	clk_prepare_enable(dsi->dsi_p_clk);
 	clk_prepare_enable(dsi->dsi_sys_clk);
 
+	if (dsi->platform_ops && dsi->platform_ops->resume)
+		dsi->platform_ops->resume(dsi);
+
 	return 0;
 }
 

@@ -1152,6 +1171,10 @@ static int __maybe_unused cdns_dsi_suspend(struct device *dev)
 	clk_disable_unprepare(dsi->dsi_sys_clk);
 	clk_disable_unprepare(dsi->dsi_p_clk);
 	reset_control_assert(dsi->dsi_p_rst);
+
+	if (dsi->platform_ops && dsi->platform_ops->suspend)
+		dsi->platform_ops->suspend(dsi);
+
 	dsi->link_initialized = false;
 	return 0;
 }

@@ -1294,6 +1317,10 @@ static const struct of_device_id cdns_dsi_of_match[] = {
 #ifdef CONFIG_DRM_CDNS_DSI_J721E
 	{ .compatible = "ti,j721e-dsi", .data = &dsi_ti_j721e_ops, },
 #endif
+#ifdef CONFIG_DRM_CDNS_DSI_JH7110
+	{ .compatible = "starfive,jh7110-dsi", .data = &dsi_ti_jh7110_ops, },
+#endif
+
 	{ },
 };
 MODULE_DEVICE_TABLE(of, cdns_dsi_of_match);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h +21 -0
index ca7ea2da635c..f4491009c977 100644
@@ -53,12 +53,22 @@ struct cdns_dsi;
  * @deinit: Called in the CDNS DSI remove
  * @enable: Called at the beginning of CDNS DSI bridge enable
  * @disable: Called at the end of CDNS DSI bridge disable
+ * @resume: Called at the resume of CDNS DSI
+ * @suspend: Called at the suspend of CDNS DSI
+ * @update: Called at the middle of CDNS DSI bridge enable
  */
 struct cdns_dsi_platform_ops {
 	int (*init)(struct cdns_dsi *dsi);
 	void (*deinit)(struct cdns_dsi *dsi);
 	void (*enable)(struct cdns_dsi *dsi);
 	void (*disable)(struct cdns_dsi *dsi);
+	void (*resume)(struct cdns_dsi *dsi);
+	void (*suspend)(struct cdns_dsi *dsi);
+	int (*update)(struct cdns_dsi *dsi, struct cdns_dsi_cfg *dsi_cfg,
+		      struct phy_configure_opts_mipi_dphy *phy_cfg,
+		      unsigned long dpi_hz, unsigned long dpi_htotal,
+		      unsigned long dsi_htotal);
+	void (*transfer)(struct cdns_dsi *dsi);
 };
 
 struct cdns_dsi {

@@ -79,6 +89,17 @@ struct cdns_dsi {
 	bool link_initialized;
 	bool phy_initialized;
 	struct phy *dphy;
+
+#ifdef CONFIG_DRM_CDNS_DSI_JH7110
+	struct clk *apb_clk;
+	struct clk *txesc_clk;
+	struct reset_control *dpi_rst;
+	struct reset_control *apb_rst;
+	struct reset_control *txesc_rst;
+	struct reset_control *txbytehs_rst;
+#endif
 };
 
+void cdns_dsi_hs_init(struct cdns_dsi *dsi);
+
 #endif /* !__CDNS_DSI_H__ */
drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.c new file +193 -0

193 lines not on this page · raw message

drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.h new file +16 -0
new file mode 100644
index 000000000000..15d6a766b502
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * JH7110 Cadence DSI
+ *
+ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
+ * Author: keith.zhao <[email protected]>
+ */
+
+#ifndef __CDNS_DSI_JH7110_H__
+#define __CDNS_DSI_JH7110_H__
+
+#include "cdns-dsi-core.h"
+
+extern const struct cdns_dsi_platform_ops dsi_ti_jh7110_ops;
+
+#endif /* !__CDNS_DSI_JH7110_H__ */
Signature · 1 line
2.17.1
#5 lore raw

Re: [PATCH v2 2/2] gpu: drm: bridge: cadence: Add a driver and platform ops for StarFive JH7110 SoC

drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.c line 107

Quoted 5 lines · Shengyang Chen
drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.c new file +5 -0
+static int cdns_dsi_get_reset(struct device *dev, struct cdns_dsi *dsi)
+{
+	dsi->dpi_rst = devm_reset_control_get(dev, "dpi");
+	if (IS_ERR(dsi->dpi_rst))
+		return PTR_ERR(dsi->dpi_rst);

Please use devm_reset_control_get_exclusive() directly.

Also, consider using devm_reset_control_bulk_get_exclusive() instead, to control "dpi"/"apb"/"txesc" resets together - if the hardware can handle deasserting in reversed order.

Quoted 5 lines
drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.c new file +5 -0
+
+	dsi->apb_rst = devm_reset_control_get(dev, "apb");
+	if (IS_ERR(dsi->apb_rst))
+		return PTR_ERR(dsi->apb_rst);
+

drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.c line 122

Quoted 10 lines
drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.c new file +10 -0
+	dsi->txesc_rst = devm_reset_control_get(dev, "txesc");
+	if (IS_ERR(dsi->txesc_rst))
+		return PTR_ERR(dsi->txesc_rst);
+
+	dsi->txbytehs_rst = devm_reset_control_get(dev, "txbytehs");
+	if (IS_ERR(dsi->txbytehs_rst))
+		return PTR_ERR(dsi->txbytehs_rst);
+
+	return 0;
+}

regards
Philipp

author
#6 lore raw

RE: [PATCH v2 2/2] gpu: drm: bridge: cadence: Add a driver and platform ops for StarFive JH7110 SoC

Hi, Philipp

Thanks for review and comment.

Quoted 28 lines

-----Original Message-----
From: Philipp Zabel <[email protected]>
Sent: 2024年1月9日 17:08
To: Shengyang Chen <[email protected]>; [email protected]; [email protected]
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Changhuang Liang <[email protected]>; Keith Zhao <[email protected]>; Jack Zhu <[email protected]>; [email protected]
Subject: Re: [PATCH v2 2/2] gpu: drm: bridge: cadence: Add a driver and platform ops for StarFive JH7110 SoC

drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.c line 107

Quoted 5 lines · Shengyang Chen
drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.c new file +5 -0
+static int cdns_dsi_get_reset(struct device *dev, struct cdns_dsi
+*dsi) {
+	dsi->dpi_rst = devm_reset_control_get(dev, "dpi");
+	if (IS_ERR(dsi->dpi_rst))
+		return PTR_ERR(dsi->dpi_rst);

Please use devm_reset_control_get_exclusive() directly.

Quoted 4 lines

Also, consider using devm_reset_control_bulk_get_exclusive() instead, to control "dpi"/"apb"/"txesc" resets together - if the hardware can handle deasserting in reversed order.

ok, will follow up this issue.

Quoted 10 lines
Quoted 10 lines
drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.c new file +10 -0
+
+	dsi->apb_rst = devm_reset_control_get(dev, "apb");
+	if (IS_ERR(dsi->apb_rst))
+		return PTR_ERR(dsi->apb_rst);
+
+	dsi->txesc_rst = devm_reset_control_get(dev, "txesc");
+	if (IS_ERR(dsi->txesc_rst))
+		return PTR_ERR(dsi->txesc_rst);
+
+	dsi->txbytehs_rst = devm_reset_control_get(dev, "txbytehs");
Quoted 8 lines

drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.c line 122

Quoted 5 lines
drivers/gpu/drm/bridge/cadence/cdns-dsi-jh7110.c new file +5 -0
+	if (IS_ERR(dsi->txbytehs_rst))
+		return PTR_ERR(dsi->txbytehs_rst);
+
+	return 0;
+}

regards
Philipp

thanks.

Best Regards,
Shengyang