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arm64: dts: ti: am62: Add USB support for k3-am62p

PATCH Superseded Roger Quadros 2 participants 5 messages Jan 30, 2024

Subsystems (3)
Device tree bindings Multifunction devices (MFD) Arm/Texas Instruments K3 architecture

v2 of 7 Superseded Latest is v7 →

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Roger Quadros

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#0 lore raw

v2 cover arm64: dts: ti: am62: Add USB support for k3-am62p

Hi,

This series first adds device nodes for USB0_PHY_CTRL and USB1_PHY_CTRL in the wkup_conf node and fixus up the USB nodes to use the newly added nodes.

Then it adds USB support for AM62P SoC and AM62P5-SK board.

Changelog in each patch.

cheers,
-roger

Roger Quadros (3):
dt-bindings: mfd: syscon: Add ti,am62-usb-phy-ctrl compatible
arm64: dts: ti: k3-am62/a: use sub-node for USB_PHY_CTRL registers
arm64: dts: ti: k3-am62p: add the USB sub-system

 .../devicetree/bindings/mfd/syscon.yaml       |  1 +
 arch/arm64/boot/dts/ti/k3-am62-main.dtsi      |  4 +-
 arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi    | 10 +++
 arch/arm64/boot/dts/ti/k3-am62a-main.dtsi     |  4 +-
 arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi   | 10 +++
 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi     | 46 +++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi   | 10 +++
 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts       | 67 +++++++++++++++++++
 8 files changed, 148 insertions(+), 4 deletions(-)

base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d

Signature · 1 line
2.34.1
author
#1 lore raw

PATCH v2 1/3 dt-bindings: mfd: syscon: Add ti,am62-usb-phy-ctrl compatible

Add the compatible for TI AM62 USB PHY Control register. This register is found in the TI AM62 WKUP_CTRL_MMR0 space [1]. It is used to indicate the USB PHY PLL reference clock rate and core voltage level to the USB controller.

[1] - https://www.ti.com/lit/pdf/spruiv7

Signed-off-by Roger Quadros <[email protected]>

---

Notes:
Changelog:

v2 - New patch

 Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/mfd/syscon.yaml +1 -0
index 084b5c2a2a3c..b5f27cc2917c 100644
@@ -73,6 +73,7 @@ properties:
               - rockchip,rv1126-qos
               - starfive,jh7100-sysmain
               - ti,am654-dss-oldi-io-ctrl
+              - ti,am62-usb-phy-ctrl
 
           - const: syscon
Signature · 1 line
2.34.1
#2 lore raw

Re: [PATCH v2 1/3] dt-bindings: mfd: syscon: Add ti,am62-usb-phy-ctrl compatible

Quoted 23 lines · Roger Quadros

Add the compatible for TI AM62 USB PHY Control register. This register is found in the TI AM62 WKUP_CTRL_MMR0 space [1]. It is used to indicate the USB PHY PLL reference clock rate and core voltage level to the USB controller.

[1] - https://www.ti.com/lit/pdf/spruiv7

Signed-off-by Roger Quadros <[email protected]>

---

Notes:
Changelog:

v2 - New patch

 Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/mfd/syscon.yaml +0 -0
index 084b5c2a2a3c..b5f27cc2917c 100644

Documentation/devicetree/bindings/mfd/syscon.yaml properties: · line 76

Quoted 4 lines
Documentation/devicetree/bindings/mfd/syscon.yaml +1 -0
@@ -73,6 +73,7 @@ properties:
               - rockchip,rv1126-qos
               - starfive,jh7100-sysmain
               - ti,am654-dss-oldi-io-ctrl
+              - ti,am62-usb-phy-ctrl

Please keep order of entries (so 654 after 62).

Best regards,
Krzysztof

author
#3 lore raw

PATCH v2 2/3 arm64: dts: ti: k3-am62/a: use sub-node for USB_PHY_CTRL registers

In reply to Roger Quadros

Exposing the entire CTRL_MMR space to syscon is not a good idea. Add sub-nodes for USB0_PHY_CTRL and USB1_PHY_CTRL and use them in the USB0/USB1 nodes.

Signed-off-by Roger Quadros <[email protected]>

---

Notes:
Changelog:

v2:
- moved am62p changes to next patch
- use new compatible for USB PHY CTRL node

 arch/arm64/boot/dts/ti/k3-am62-main.dtsi    |  4 ++--
 arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi  | 10 ++++++++++
 arch/arm64/boot/dts/ti/k3-am62a-main.dtsi   |  4 ++--
 arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 10 ++++++++++
 4 files changed, 24 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/ti/k3-am62-main.dtsi +2 -2
index 464b7565d085..9432ed344d52 100644
@@ -625,7 +625,7 @@ usbss0: dwc3-usb@f900000 {
 		reg = <0x00 0x0f900000 0x00 0x800>;
 		clocks = <&k3_clks 161 3>;
 		clock-names = "ref";
-		ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
+		ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 		power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;

@@ -648,7 +648,7 @@ usbss1: dwc3-usb@f910000 {
 		reg = <0x00 0x0f910000 0x00 0x800>;
 		clocks = <&k3_clks 162 3>;
 		clock-names = "ref";
-		ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
+		ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +10 -0
index fef76f52a52e..817700b2eacf 100644
@@ -19,6 +19,16 @@ chipid: chipid@14 {
 			compatible = "ti,am654-chipid";
 			reg = <0x14 0x4>;
 		};
+
+		usb0_phy_ctrl: syscon@4008 {
+			compatible = "ti,am62-usb-phy-ctrl", "syscon";
+			reg = <0x4008 0x4>;
+		};
+
+		usb1_phy_ctrl: syscon@4018 {
+			compatible = "ti,am62-usb-phy-ctrl", "syscon";
+			reg = <0x4018 0x4>;
+		};
 	};
 
 	wkup_uart0: serial@2b300000 {
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +2 -2
index f0b8c9ab1459..8311c7c44cd3 100644
@@ -566,7 +566,7 @@ usbss0: dwc3-usb@f900000 {
 		reg = <0x00 0x0f900000 0x00 0x800>;
 		clocks = <&k3_clks 161 3>;
 		clock-names = "ref";
-		ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
+		ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 		power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;

@@ -589,7 +589,7 @@ usbss1: dwc3-usb@f910000 {
 		reg = <0x00 0x0f910000 0x00 0x800>;
 		clocks = <&k3_clks 162 3>;
 		clock-names = "ref";
-		ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
+		ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +10 -0
index 4e8279fa01e1..4a375f5e0c19 100644
@@ -17,6 +17,16 @@ chipid: chipid@14 {
 			compatible = "ti,am654-chipid";
 			reg = <0x14 0x4>;
 		};
+
+		usb0_phy_ctrl: syscon@4008 {
+			compatible = "ti,am62-usb-phy-ctrl", "syscon";
+			reg = <0x4008 0x4>;
+		};
+
+		usb1_phy_ctrl: syscon@4018 {
+			compatible = "ti,am62-usb-phy-ctrl", "syscon";
+			reg = <0x4018 0x4>;
+		};
 	};
 
 	wkup_uart0: serial@2b300000 {
Signature · 1 line
2.34.1
author
#4 lore raw

PATCH v2 3/3 arm64: dts: ti: k3-am62p: add the USB sub-system

In reply to Roger Quadros

There are two USB instances available on the am62p5 starter kit. Include and enable them for use on the board.

Signed-off-by Vignesh Raghavendra <[email protected]>
Signed-off-by Roger Quadros <[email protected]>

---

Notes:
Changelog:

v2:
- added USB PHY CTRL node changes here
- changed USB wrapper node names to usb@
- changed Type-C chip node name to usb-power-control@

 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi   | 46 ++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 10 +++
 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts     | 67 +++++++++++++++++++++
 3 files changed, 123 insertions(+)
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +46 -0
index 4c51bae06b57..17d28390d587 100644
@@ -560,6 +560,52 @@ sdhci2: mmc@fa20000 {
 		status = "disabled";
 	};
 
+	usbss0: usb@f900000 {
+		compatible = "ti,am62-usb";
+		reg = <0x00 0x0f900000 0x00 0x800>;
+		clocks = <&k3_clks 161 3>;
+		clock-names = "ref";
+		ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
+		ranges;
+		status = "disabled";
+
+		usb0: usb@31000000 {
+			compatible = "snps,dwc3";
+			reg = <0x00 0x31000000 0x00 0x50000>;
+			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+			<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+			interrupt-names = "host", "peripheral";
+			maximum-speed = "high-speed";
+			dr_mode = "otg";
+		};
+	};
+
+	usbss1: usb@f910000 {
+		compatible = "ti,am62-usb";
+		reg = <0x00 0x0f910000 0x00 0x800>;
+		clocks = <&k3_clks 162 3>;
+		clock-names = "ref";
+		ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+		ranges;
+		status = "disabled";
+
+		usb1: usb@31100000 {
+			compatible = "snps,dwc3";
+			reg = <0x00 0x31100000 0x00 0x50000>;
+			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+			<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+			interrupt-names = "host", "peripheral";
+			maximum-speed = "high-speed";
+			dr_mode = "otg";
+		};
+	};
+
 	fss: bus@fc00000 {
 		compatible = "simple-bus";
 		reg = <0x00 0x0fc00000 0x00 0x70000>;
arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi +10 -0
index 19f42b39394e..00dd38b02a52 100644
@@ -18,6 +18,16 @@ chipid: chipid@14 {
 			reg = <0x14 0x4>;
 			bootph-all;
 		};
+
+		usb0_phy_ctrl: syscon@4008 {
+			compatible = "ti,am62-usb-phy-ctrl", "syscon";
+			reg = <0x4008 0x4>;
+		};
+
+		usb1_phy_ctrl: syscon@4018 {
+			compatible = "ti,am62-usb-phy-ctrl", "syscon";
+			reg = <0x4018 0x4>;
+		};
 	};
 
 	wkup_uart0: serial@2b300000 {
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +67 -0

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Signature · 1 line
2.34.1