dt-bindings: spi: Convert spi-davinci.txt to YAML

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index f012888656eca..0000000000000
@@ -1,100 +0,0 @@
-Davinci SPI controller device bindings
-
-Links on DM:
-Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
-dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
-OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
-
-Required properties:
-- #address-cells: number of cells required to define a chip select
-	address on the SPI bus. Should be set to 1.
-- #size-cells: should be zero.
-- compatible:
-	- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
-	- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
-	- "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
-		family
-- reg: Offset and length of SPI controller register space
-- num-cs: Number of chip selects. This includes internal as well as
-	GPIO chip selects.
-- ti,davinci-spi-intr-line: interrupt line used to connect the SPI
-	IP to the interrupt controller within the SoC. Possible values
-	are 0 and 1. Manual says one of the two possible interrupt
-	lines can be tied to the interrupt controller. Set this
-	based on a specific SoC configuration.
-- interrupts: interrupt number mapped to CPU.
-- clocks: spi clk phandle
-          For 66AK2G this property should be set per binding,
-          Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
-
-SoC-specific Required Properties:
-
-The following are mandatory properties for Keystone 2 66AK2G SoCs only:
-
-- power-domains:	Should contain a phandle to a PM domain provider node
-			and an args specifier containing the SPI device id
-			value. This property is as per the binding,
-
-Optional:
-- cs-gpios: gpio chip selects
-	For example to have 3 internal CS and 2 GPIO CS, user could define
-	cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
-	where first three are internal CS and last two are GPIO CS.
-
-Optional properties for slave devices:
-SPI slave nodes can contain the following properties.
-Not all SPI Peripherals from Texas Instruments support this.
-Please check SPI peripheral documentation for a device before using these.
-
-- ti,spi-wdelay : delay between transmission of words
-	(SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module
-	clock periods.
-
-	delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period
-
-Below is timing diagram which shows functional meaning of
-"ti,spi-wdelay" parameter.
-
-             +-+ +-+ +-+ +-+ +-+                           +-+ +-+ +-+
-SPI_CLK      | | | | | | | | | |                           | | | | | |
-  +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +-
-
-SPI_SOMI/SIMO+-----------------+                           +-----------
-  +----------+ word1           +---------------------------+word2
-             +-----------------+                           +-----------
-                                          WDELAY
-                                <-------------------------->
-
-Example of a NOR flash slave device (n25q032) connected to DaVinci
-SPI controller device over the SPI bus.
-
-spi0:spi@20bf0000 {
-	#address-cells			= <1>;
-	#size-cells			= <0>;
-	compatible			= "ti,dm6446-spi";
-	reg				= <0x20BF0000 0x1000>;
-	num-cs				= <4>;
-	ti,davinci-spi-intr-line	= <0>;
-	interrupts			= <338>;
-	clocks				= <&clkspi>;
-
-	flash: flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "st,m25p32";
-		spi-max-frequency = <25000000>;
-		reg = <0>;
-		ti,spi-wdelay = <8>;
-
-		partition@0 {
-			label = "u-boot-spl";
-			reg = <0x0 0x80000>;
-			read-only;
-		};
-
-		partition@1 {
-			label = "test";
-			reg = <0x80000 0x380000>;
-		};
-	};
-};

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-Status: Unstable - ABI compatibility may be broken in the future
-
-Binding for Keystone gate control driver which uses PSC controller IP.
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be "ti,keystone,psc-clock".
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : parent clock phandle
-- reg :	psc control and domain address address space
-- reg-names : psc control and domain registers
-- domain-id : psc domain id needed to check the transition state register
-
-Optional properties:
-- clock-output-names : From common clock binding to override the
-			default output clock name
-Example:
-	clkusb: clkusb {
-		#clock-cells = <0>;
-		compatible = "ti,keystone,psc-clock";
-		clocks = <&chipclk16>;
-		clock-output-names = "usb";
-		reg = <0x02350008 0xb00>, <0x02350000 0x400>;
-		reg-names = "control", "domain";
-		domain-id = <0>;
-	};

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index 463a97c11eff3..08bc83ecfd3f9 100644
@@ -75,7 +75,7 @@ SoCs only:
 
 - clocks: 		Should contain the device's input clock, and should be
 			defined as per the bindings in,
-			Documentation/devicetree/bindings/clock/keystone-gate.txt
+			Documentation/devicetree/bindings/clock/ti,keystone,psc-clock.yaml
 
 The following are mandatory properties for Keystone 2 66AK2G SoCs only:
 

index cd90298c493c7..6d8896ba9a6e2 100644
@@ -65,7 +65,7 @@ specified through DTS. Following are the DTS used:
 
 The device tree documentation for the keystone machines are located at
 
-        Documentation/devicetree/bindings/arm/keystone/keystone.txt
+        Documentation/devicetree/bindings/arm/keystone/ti,keystone.yaml
 
 Document Author
 ---------------

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-Texas Instruments eDMA
-
-The eDMA3 consists of two components: Channel controller (CC) and Transfer
-Controller(s) (TC). The CC is the main entry for DMA users since it is
-responsible for the DMA channel handling, while the TCs are responsible to
-execute the actual DMA tansfer.
-
-------------------------------------------------------------------------------
-eDMA3 Channel Controller
-
-Required properties:
---------------------
-- compatible:	Should be:
-		- "ti,edma3-tpcc" for the channel controller(s) on OMAP,
-		  AM33xx and AM43xx SoCs.
-		- "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
-		  channel controller(s) on 66AK2G.
-- #dma-cells:	Should be set to <2>. The first number is the DMA request
-		number and the second is the TC the channel is serviced on.
-- reg:		Memory map of eDMA CC
-- reg-names:	"edma3_cc"
-- interrupts:	Interrupt lines for CCINT, MPERR and CCERRINT.
-- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
-- ti,tptcs:	List of TPTCs associated with the eDMA in the following form:
-		<&tptc_phandle TC_priority_number>. The highest priority is 0.
-
-SoC-specific Required properties:
---------------------------------
-The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
-- ti,hwmods:	Name of the hwmods associated to the eDMA CC.
-
-The following are mandatory properties for 66AK2G SoCs only:
-- power-domains:Should contain a phandle to a PM domain provider node
-		and an args specifier containing the device id
-		value. This property is as per the binding,
-		Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
-
-Optional properties:
--------------------
-- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
-		these channels will be SW triggered channels. See example.
-- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
-		the driver, they are allocated to be used by for example the
-		DSP. See example.
-- dma-channel-mask: Mask of usable channels.
-		Single uint32 for EDMA with 32 channels, array of two uint32 for
-		EDMA with 64 channels. See example and
-		Documentation/devicetree/bindings/dma/dma-common.yaml
-
-
-------------------------------------------------------------------------------
-eDMA3 Transfer Controller
-
-Required properties:
---------------------
-- compatible:	Should be:
-		- "ti,edma3-tptc" for the transfer controller(s) on OMAP,
-		  AM33xx and AM43xx SoCs.
-		- "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the
-		  transfer controller(s) on 66AK2G.
-- reg:		Memory map of eDMA TC
-- interrupts:	Interrupt number for TCerrint.
-
-SoC-specific Required properties:
---------------------------------
-The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
-- ti,hwmods:	Name of the hwmods associated to the eDMA TC.
-
-The following are mandatory properties for 66AK2G SoCs only:
-- power-domains:Should contain a phandle to a PM domain provider node
-		and an args specifier containing the device id
-		value. This property is as per the binding,
-		Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
-
-Optional properties:
--------------------
-- interrupt-names: "edma3_tcerrint"
-
-------------------------------------------------------------------------------
-Examples:
-
-1.
-edma: edma@49000000 {
-	compatible = "ti,edma3-tpcc";
-	ti,hwmods = "tpcc";
-	reg =	<0x49000000 0x10000>;
-	reg-names = "edma3_cc";
-	interrupts = <12 13 14>;
-	interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
-	dma-requests = <64>;
-	#dma-cells = <2>;
-
-	ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;
-
-	/* Channel 20 and 21 is allocated for memcpy */
-	ti,edma-memcpy-channels = <20 21>;
-	/* The following PaRAM slots are reserved: 35-44 and 100-109 */
-	ti,edma-reserved-slot-ranges = <35 10>, <100 10>;
-	/* The following channels are reserved: 35-44 */
-	dma-channel-mask = <0xffffffff /* Channel 0-31 */
-			    0xffffe007>; /* Channel 32-63 */
-};
-
-edma_tptc0: tptc@49800000 {
-	compatible = "ti,edma3-tptc";
-	ti,hwmods = "tptc0";
-	reg =	<0x49800000 0x100000>;
-	interrupts = <112>;
-	interrupt-names = "edm3_tcerrint";
-};
-
-edma_tptc1: tptc@49900000 {
-	compatible = "ti,edma3-tptc";
-	ti,hwmods = "tptc1";
-	reg =	<0x49900000 0x100000>;
-	interrupts = <113>;
-	interrupt-names = "edm3_tcerrint";
-};
-
-edma_tptc2: tptc@49a00000 {
-	compatible = "ti,edma3-tptc";
-	ti,hwmods = "tptc2";
-	reg =	<0x49a00000 0x100000>;
-	interrupts = <114>;
-	interrupt-names = "edm3_tcerrint";
-};
-
-sham: sham@53100000 {
-	compatible = "ti,omap4-sham";
-	ti,hwmods = "sham";
-	reg = <0x53100000 0x200>;
-	interrupts = <109>;
-	/* DMA channel 36 executed on eDMA TC0 - low priority queue */
-	dmas = <&edma 36 0>;
-	dma-names = "rx";
-};
-
-mcasp0: mcasp@48038000 {
-	compatible = "ti,am33xx-mcasp-audio";
-	ti,hwmods = "mcasp0";
-	reg = <0x48038000 0x2000>,
-		<0x46000000 0x400000>;
-	reg-names = "mpu", "dat";
-	interrupts = <80>, <81>;
-	interrupt-names = "tx", "rx";
-	/* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
-	dmas = <&edma 8 2>,
-	       <&edma 9 2>;
-	dma-names = "tx", "rx";
-};
-
-2.
-edma1: edma@2728000 {
-	compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
-	reg =	<0x02728000 0x8000>;
-	reg-names = "edma3_cc";
-	interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
-			<GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
-			<GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
-	interrupt-names = "edma3_ccint", "emda3_mperr",
-			  "edma3_ccerrint";
-	dma-requests = <64>;
-	#dma-cells = <2>;
-
-	ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
-
-	/*
-	 * memcpy is disabled, can be enabled with:
-	 * ti,edma-memcpy-channels = <12 13 14 15>;
-	 * for example.
-	 */
-
-	power-domains = <&k2g_pds 0x4f>;
-};
-
-edma1_tptc0: tptc@27b0000 {
-	compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
-	reg =	<0x027b0000 0x400>;
-	power-domains = <&k2g_pds 0x4f>;
-};
-
-edma1_tptc1: tptc@27b8000 {
-	compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
-	reg =	<0x027b8000 0x400>;
-	power-domains = <&k2g_pds 0x4f>;
-};
-
-mmc0: mmc@23000000 {
-	compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
-	reg = <0x23000000 0x400>;
-	interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
-	dmas = <&edma1 24 0>, <&edma1 25 0>;
-	dma-names = "tx", "rx";
-	bus-width = <4>;
-	ti,needs-special-reset;
-	no-1-8-v;
-	max-frequency = <96000000>;
-	power-domains = <&k2g_pds 0xb>;
-	clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
-	clock-names = "fck", "mmchsdb_fck";
-};
-
-------------------------------------------------------------------------------
-DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
-binding.
-
-Required properties:
-- compatible : "ti,edma3"
-- #dma-cells: Should be set to <1>
-              Clients should use a single channel number per DMA request.
-- reg: Memory map for accessing module
-- interrupts: Exactly 3 interrupts need to be specified in the order:
-              1. Transfer completion interrupt.
-              2. Memory protection interrupt.
-              3. Error interrupt.
-Optional properties:
-- ti,hwmods: Name of the hwmods associated to the EDMA
-- ti,edma-xbar-event-map: Crossbar event to channel map
-
-Deprecated properties:
-Listed here in case one wants to boot an old kernel with new DTB. These
-properties might need to be added to the new DTS files.
-- ti,edma-regions: Number of regions
-- ti,edma-slots: Number of slots
-- dma-channels: Specify total DMA channels per CC
-
-Example:
-
-edma: edma@49000000 {
-	reg = <0x49000000 0x10000>;
-	interrupt-parent = <&intc>;
-	interrupts = <12 13 14>;
-	compatible = "ti,edma3";
-	ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
-	#dma-cells = <1>;
-	ti,edma-xbar-event-map = /bits/ 16 <1 12
-					    2 13>;
-};

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index 8999497011a26..9dfa6814681ff 100644
@@ -21716,7 +21716,6 @@ M:	Peter Ujfalusi <[email protected]>
 L:	[email protected]
 S:	Maintained
 F:	Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt
-F:	Documentation/devicetree/bindings/dma/ti-edma.txt
 F:	Documentation/devicetree/bindings/dma/ti/
 F:	drivers/dma/ti/
 F:	include/linux/dma/k3-psil.h