Disable automatic load CCS load balancing
Subsystems (3)
cover Disable automatic load CCS load balancing
Hi,
this series does basically two things:
1. Disables automatic load balancing as adviced by the hardware workaround.
2. Forces the sharing of the load submitted to CCS among all the CCS available (as of now only DG2 has more than one CCS). This way the user, when sending a query, will see only one CCS available.
Andi
Andi Shyti (2):
drm/i915/gt: Disable HW load balancing for CCS
drm/i915/gt: Set default CCS mode '1'
drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 5 files changed, 40 insertions(+), 2 deletions(-)
Signature · 1 line
2.43.0
PATCH 1/2 drm/i915/gt: Disable HW load balancing for CCS
The hardware should not dynamically balance the load between CCS engines. Wa_16016805146 recommends disabling it across all platforms.
--- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ 2 files changed, 7 insertions(+)
drivers/gpu/drm/i915/gt/intel_gt_regs.h +1 -0
@@ -1478,6 +1478,7 @@#define GEN12_RCU_MODE _MMIO(0x14800)#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)#define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)#define CHV_FGT_DISABLE_SS0 (1 << 10)
drivers/gpu/drm/i915/gt/intel_workarounds.c +6 -0
@@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_liwa_mcr_masked_en (wal,GEN8_HALF_SLICE_CHICKEN1 ,GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE ); } + +/* +* Wa_16016805146: disable the CCS load balancing +* indiscriminately for all the platforms +*/ +wa_masked_en (wal,GEN12_RCU_MODE ,XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE ); } static void
Signature · 1 line
2.43.0
Re: [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS
Quoted 2 lines · Andi Shyti
The hardware should not dynamically balance the load between CCS engines.
Wa_16016805146recommends disabling it across all
Is this the right workaround number? When I check the database, this workaround was rejected on both DG2-G10 and DG2-G11, and doesn't even have an entry for DG2-G12.
There are other workarounds that sound somewhat related to load balancing (e.g., part 3 of Wa_14019159160), but what's asked there is more involved than just setting one register bit and conflicts a bit with the second patch of this series.
Matt
Quoted 45 lines
platforms.
Fixes d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")Signed-off-by Andi Shyti <[email protected]>Cc Chris Wilson <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Matt Roper <[email protected]>Cc <[email protected]> # v6.2+--- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ 2 files changed, 7 insertions(+)drivers/gpu/drm/i915/gt/intel_gt_regs.h +1
-0@@ -1478,6 +1478,7 @@#define GEN12_RCU_MODE _MMIO(0x14800)#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)#define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)#define CHV_FGT_DISABLE_SS0 (1 << 10)drivers/gpu/drm/i915/gt/intel_workarounds.c +6
-0@@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_liwa_mcr_masked_en (wal,GEN8_HALF_SLICE_CHICKEN1 ,GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE ); } + +/* +* Wa_16016805146: disable the CCS load balancing +* indiscriminately for all the platforms +*/ +wa_masked_en (wal,GEN12_RCU_MODE ,XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE ); } static voidSignature · 1 line
2.43.0
Signature · 4 lines
Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
Re: [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS
Hi Matt,
Quoted 4 lines · Matt Roper
Quoted 2 lines · Andi Shyti
The hardware should not dynamically balance the load between CCS engines.
Wa_16016805146recommends disabling it across all
Quoted 8 lines
Is this the right workaround number? When I check the database, this workaround was rejected on both DG2-G10 and DG2-G11, and doesn't even have an entry for DG2-G12.
There are other workarounds that sound somewhat related to load balancing (e.g., part 3 of
Wa_14019159160), but what's asked there is more involved than just setting one register bit and conflicts a bit with the second patch of this series.
thanks for checking it. Indeed the WA I mentioned is limited to a specific platform. This recommendation comes in different WA, e.g. this one: Wa_14019186972 (3rd point). Will start using that as a reference.
Thank you.
Andi
Quoted 55 lines
Matt
Quoted 45 lines
platforms.
Fixes d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")Signed-off-by Andi Shyti <[email protected]>Cc Chris Wilson <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Matt Roper <[email protected]>Cc <[email protected]> # v6.2+--- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ 2 files changed, 7 insertions(+)drivers/gpu/drm/i915/gt/intel_gt_regs.h +1
-0@@ -1478,6 +1478,7 @@#define GEN12_RCU_MODE _MMIO(0x14800)#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)#define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)#define CHV_FGT_DISABLE_SS0 (1 << 10)drivers/gpu/drm/i915/gt/intel_workarounds.c +6
-0@@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_liwa_mcr_masked_en (wal,GEN8_HALF_SLICE_CHICKEN1 ,GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE ); } + +/* +* Wa_16016805146: disable the CCS load balancing +* indiscriminately for all the platforms +*/ +wa_masked_en (wal,GEN12_RCU_MODE ,XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE ); } static voidSignature · 1 line
2.43.0Signature · 4 lines
Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
Re: [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS
Quoted 14 lines · Andi Shyti
Quoted 4 lines · Matt Roper
Quoted 2 lines · Andi Shyti
The hardware should not dynamically balance the load between CCS engines.
Wa_16016805146recommends disabling it across allQuoted 8 lines
Is this the right workaround number? When I check the database, this workaround was rejected on both DG2-G10 and DG2-G11, and doesn't even have an entry for DG2-G12.
There are other workarounds that sound somewhat related to load balancing (e.g., part 3 of
Wa_14019159160), but what's asked there is more involved than just setting one register bit and conflicts a bit with the second patch of this series.
Quoted 4 lines
thanks for checking it. Indeed the WA I mentioned is limited to a specific platform. This recommendation comes in different WA, e.g. this one:
Wa_14019186972(3rd point). Will start using that as a reference.
actually you are right, I checked with Joonas and I will use Wa_14019159160.
Thanks,
Andi
PATCH 2/2 drm/i915/gt: Set default CCS mode '1'
In reply to Andi ShytiSince CCS automatic load balancing is disabled, we will impose a fixed balancing policy that involves setting all the CCS engines to work together on the same load.
Simultaneously, the user will see only 1 CCS rather than the actual number. As of now, this change affects only DG2.
--- drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 4 files changed, 33 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/gt/intel_gt.c +11 -0
@@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt) } } +static void intel_gt_apply_ccs_mode (struct intel_gt *gt) +{ +if (!IS_DG2 (gt->i915)) +return ; + +intel_uncore_write (gt->uncore,XEHP_CCS_MODE ,0 ); +} +int intel_gt_init_hw (struct intel_gt *gt) {struct drm_i915_private *i915 = gt->i915;
@@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)intel_gt_init_swizzling (gt); +/* Configure CCS mode */ +intel_gt_apply_ccs_mode (gt); +/* * At least 830 can leave some of the unused rings * "active" (ie. head != tail) after resume which
drivers/gpu/drm/i915/gt/intel_gt_regs.h +2 -0
@@ -1605,6 +1605,8 @@#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)#define GEN12_CAGF_MASK REG_GENMASK(19, 11) +#define XEHP_CCS_MODE _MMIO(0x14804) +#define GEN11_GT_INTR_DW (x) _MMIO(0x190018 + ((x) * 4))#define GEN11_CSME (31)#define GEN12_HECI_2 (30)
drivers/gpu/drm/i915/i915_drv.h +17 -0
@@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) (engine__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) +/* +* Exclude unavailable engines. +* +* Only the first CCS engine is utilized due to the disabling of CCS auto load +* balancing. As a result, all CCS engines operate collectively, functioning +* essentially as a single CCS engine, hence the count of active CCS engines is +* considered '1'. +* Currently, this applies to platforms with more than one CCS engine, +* specifically DG2. +*/ +#define for_each_available_uabi_engine (engine__, i915__) \ + for_each_uabi_engine(engine__, i915__) \ + if ((IS_DG2(i915__)) && \ + ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \ + ((engine__)->uabi_instance)) { } \ + else +#define INTEL_INFO (i915) ((i915)->__info)#define RUNTIME_INFO (i915) (&(i915)->__runtime)#define DRIVER_CAPS (i915) (&(i915)->caps)
drivers/gpu/drm/i915/i915_query.c +3 -2
@@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,return fill_topology_info (sseu, query_item, sseu->geometry_subslice_mask); } +static int query_engine_info (struct drm_i915_private *i915,struct drm_i915_query_item *query_item)
@@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,if (query_item->flags)return -EINVAL ; -for_each_uabi_engine (engine, i915) +for_each_available_uabi_engine (engine, i915) num_uabi_engines++; len =struct_size (query_ptr, engines, num_uabi_engines);
@@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915, info_ptr = &query_ptr->engines[0 ]; -for_each_uabi_engine (engine, i915) { +for_each_available_uabi_engine (engine, i915) { info.engine.engine_class = engine->uabi_class; info.engine.engine_instance = engine->uabi_instance; info.flags =I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE ;
Signature · 1 line
2.43.0
Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
Quoted 6 lines · Andi Shyti
Since CCS automatic load balancing is disabled, we will impose a fixed balancing policy that involves setting all the CCS engines to work together on the same load.
Simultaneously, the user will see only 1 CCS rather than the actual number. As of now, this change affects only DG2.
These two paragraphs are mutually exclusive. You can't have four CCS engines 'working together' if only one engine exists. I think you are meaning that we only export 1 CCS engine and that single engine is configured to control all the EUs. As opposed to running in 4 CCS engine mode where the EUs are (dynamically or statically) divided amongst those four engines.
John.
Quoted 114 lines
Fixes d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")Signed-off-by Andi Shyti <[email protected]>Cc Chris Wilson <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Matt Roper <[email protected]>Cc <[email protected]> # v6.2+--- drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 4 files changed, 33 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/gt/intel_gt.c +11
-0@@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt) } } +static void intel_gt_apply_ccs_mode (struct intel_gt *gt) +{ +if (!IS_DG2 (gt->i915)) +return ; + +intel_uncore_write (gt->uncore,XEHP_CCS_MODE ,0 ); +} +int intel_gt_init_hw (struct intel_gt *gt) {struct drm_i915_private *i915 = gt->i915;@@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)intel_gt_init_swizzling (gt); +/* Configure CCS mode */ +intel_gt_apply_ccs_mode (gt); +/* * At least 830 can leave some of the unused rings * "active" (ie. head != tail) after resume which drivers/gpu/drm/i915/gt/intel_gt_regs.h +2
-0@@ -1605,6 +1605,8 @@#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)#define GEN12_CAGF_MASK REG_GENMASK(19, 11) +#define XEHP_CCS_MODE _MMIO(0x14804) +#define GEN11_GT_INTR_DW (x) _MMIO(0x190018 + ((x) * 4))#define GEN11_CSME (31)#define GEN12_HECI_2 (30)drivers/gpu/drm/i915/i915_drv.h +17
-0@@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) (engine__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) +/* +* Exclude unavailable engines. +* +* Only the first CCS engine is utilized due to the disabling of CCS auto load +* balancing. As a result, all CCS engines operate collectively, functioning +* essentially as a single CCS engine, hence the count of active CCS engines is +* considered '1'. +* Currently, this applies to platforms with more than one CCS engine, +* specifically DG2. +*/ +#define for_each_available_uabi_engine (engine__, i915__) \ + for_each_uabi_engine(engine__, i915__) \ + if ((IS_DG2(i915__)) && \ + ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \ + ((engine__)->uabi_instance)) { } \ + else +#define INTEL_INFO (i915) ((i915)->__info)#define RUNTIME_INFO (i915) (&(i915)->__runtime)#define DRIVER_CAPS (i915) (&(i915)->caps)drivers/gpu/drm/i915/i915_query.c +3
-2@@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,return fill_topology_info (sseu, query_item, sseu->geometry_subslice_mask); } +static int query_engine_info (struct drm_i915_private *i915,struct drm_i915_query_item *query_item)@@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,if (query_item->flags)return -EINVAL ; -for_each_uabi_engine (engine, i915) +for_each_available_uabi_engine (engine, i915) num_uabi_engines++; len =struct_size (query_ptr, engines, num_uabi_engines);@@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915, info_ptr = &query_ptr->engines[0 ]; -for_each_uabi_engine (engine, i915) { +for_each_available_uabi_engine (engine, i915) { info.engine.engine_class = engine->uabi_class; info.engine.engine_instance = engine->uabi_instance; info.flags =I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE ;
Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
Hi John,
Quoted 5 lines · John Harrison
Quoted 4 lines · Andi Shyti
Since CCS automatic load balancing is disabled, we will impose a fixed balancing policy that involves setting all the CCS engines to work together on the same load.
Quoted 7 lines
Quoted 2 lines
Simultaneously, the user will see only 1 CCS rather than the actual number. As of now, this change affects only DG2.
These two paragraphs are mutually exclusive. You can't have four CCS engines 'working together' if only one engine exists. I think you are meaning that we only export 1 CCS engine and that single engine is configured to control all the EUs. As opposed to running in 4 CCS engine mode where the EUs are (dynamically or statically) divided amongst those four engines.
The balancing is done statically. The dynamic balancing is disabled in patch 1.
The 2 or 4 CCS engines will share the same workload.
Because the user won't be able anymore to select the CCS engine he wants to use, he will see only one CCS.
I think we are saying the same thing using different words :) I can try in v2 to reword the commit better.
Thanks for looking into this.
Andi
Quoted 106 lines
John.
Quoted 104 lines
Fixes d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")Signed-off-by Andi Shyti <[email protected]>Cc Chris Wilson <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Matt Roper <[email protected]>Cc <[email protected]> # v6.2+--- drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 4 files changed, 33 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/gt/intel_gt.c +11
-0@@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt) } } +static void intel_gt_apply_ccs_mode (struct intel_gt *gt) +{ +if (!IS_DG2 (gt->i915)) +return ; + +intel_uncore_write (gt->uncore,XEHP_CCS_MODE ,0 ); +} +int intel_gt_init_hw (struct intel_gt *gt) {struct drm_i915_private *i915 = gt->i915;@@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)intel_gt_init_swizzling (gt); +/* Configure CCS mode */ +intel_gt_apply_ccs_mode (gt); +/* * At least 830 can leave some of the unused rings * "active" (ie. head != tail) after resume which drivers/gpu/drm/i915/gt/intel_gt_regs.h +2
-0@@ -1605,6 +1605,8 @@#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)#define GEN12_CAGF_MASK REG_GENMASK(19, 11) +#define XEHP_CCS_MODE _MMIO(0x14804) +#define GEN11_GT_INTR_DW (x) _MMIO(0x190018 + ((x) * 4))#define GEN11_CSME (31)#define GEN12_HECI_2 (30)drivers/gpu/drm/i915/i915_drv.h +17
-0@@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) (engine__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) +/* +* Exclude unavailable engines. +* +* Only the first CCS engine is utilized due to the disabling of CCS auto load +* balancing. As a result, all CCS engines operate collectively, functioning +* essentially as a single CCS engine, hence the count of active CCS engines is +* considered '1'. +* Currently, this applies to platforms with more than one CCS engine, +* specifically DG2. +*/ +#define for_each_available_uabi_engine (engine__, i915__) \ + for_each_uabi_engine(engine__, i915__) \ + if ((IS_DG2(i915__)) && \ + ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \ + ((engine__)->uabi_instance)) { } \ + else +#define INTEL_INFO (i915) ((i915)->__info)#define RUNTIME_INFO (i915) (&(i915)->__runtime)#define DRIVER_CAPS (i915) (&(i915)->caps)drivers/gpu/drm/i915/i915_query.c +3
-2@@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,return fill_topology_info (sseu, query_item, sseu->geometry_subslice_mask); } +static int query_engine_info (struct drm_i915_private *i915,struct drm_i915_query_item *query_item)@@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,if (query_item->flags)return -EINVAL ; -for_each_uabi_engine (engine, i915) +for_each_available_uabi_engine (engine, i915) num_uabi_engines++; len =struct_size (query_ptr, engines, num_uabi_engines);@@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915, info_ptr = &query_ptr->engines[0 ]; -for_each_uabi_engine (engine, i915) { +for_each_available_uabi_engine (engine, i915) { info.engine.engine_class = engine->uabi_class; info.engine.engine_instance = engine->uabi_instance; info.flags =I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE ;
Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
Quoted 15 lines · Andi Shyti
Hi John,
Quoted 5 lines · John Harrison
Quoted 4 lines · Andi Shyti
Since CCS automatic load balancing is disabled, we will impose a fixed balancing policy that involves setting all the CCS engines to work together on the same load.
Quoted 7 lines
Quoted 2 lines
Simultaneously, the user will see only 1 CCS rather than the actual number. As of now, this change affects only DG2.
These two paragraphs are mutually exclusive. You can't have four CCS engines 'working together' if only one engine exists. I think you are meaning that we only export 1 CCS engine and that single engine is configured to control all the EUs. As opposed to running in 4 CCS engine mode where the EUs are (dynamically or statically) divided amongst those four engines.
Quoted 4 lines
The balancing is done statically. The dynamic balancing is disabled in patch 1.
The 2 or 4 CCS engines will share the same workload.
But they don't.
In i915, we use 'engine' to refer to a command streamer and all the associated hardware. This is distinct from the EUs which sit behind and can be driven by one or more command streamers. Saying that multiple engines are sharing a workload implies that you are submitting the context to multiple command streamers in parallel. I.e. a similar process to media frame split where they have a set of LRCA contexts bound together which are submitted in parallel to two or more video decode engines (VCS0, VCS1, etc.). That is not what is happening here.
Here, you are submitting a single context with a singe ring buffer to a single engine - CCS0. That engine is configured to own all EUs. Which actually means that submitting a compute task to another CCS engine will achieve nothing because there are no EUs available to those other engines. They will simply hang when waiting for the walker instruction to complete.
Quoted 5 lines
Because the user won't be able anymore to select the CCS engine he wants to use, he will see only one CCS.
I think we are saying the same thing using different words :)
But words are important.
John.
Quoted 110 lines
I can try in v2 to reword the commit better.
Thanks for looking into this.
AndiQuoted 105 lines
John.
Quoted 103 lines
Fixes d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")Signed-off-by Andi Shyti <[email protected]>Cc Chris Wilson <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Matt Roper <[email protected]>Cc <[email protected]> # v6.2+--- drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 4 files changed, 33 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/gt/intel_gt.c +11
-0@@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt) } } +static void intel_gt_apply_ccs_mode (struct intel_gt *gt) +{ +if (!IS_DG2 (gt->i915)) +return ; + +intel_uncore_write (gt->uncore,XEHP_CCS_MODE ,0 ); +} +int intel_gt_init_hw (struct intel_gt *gt) {struct drm_i915_private *i915 = gt->i915;@@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)intel_gt_init_swizzling (gt); +/* Configure CCS mode */ +intel_gt_apply_ccs_mode (gt); +/* * At least 830 can leave some of the unused rings * "active" (ie. head != tail) after resume which drivers/gpu/drm/i915/gt/intel_gt_regs.h +2
-0@@ -1605,6 +1605,8 @@#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)#define GEN12_CAGF_MASK REG_GENMASK(19, 11) +#define XEHP_CCS_MODE _MMIO(0x14804) +#define GEN11_GT_INTR_DW (x) _MMIO(0x190018 + ((x) * 4))#define GEN11_CSME (31)#define GEN12_HECI_2 (30)drivers/gpu/drm/i915/i915_drv.h +17
-0@@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) (engine__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) +/* +* Exclude unavailable engines. +* +* Only the first CCS engine is utilized due to the disabling of CCS auto load +* balancing. As a result, all CCS engines operate collectively, functioning +* essentially as a single CCS engine, hence the count of active CCS engines is +* considered '1'. +* Currently, this applies to platforms with more than one CCS engine, +* specifically DG2. +*/ +#define for_each_available_uabi_engine (engine__, i915__) \ + for_each_uabi_engine(engine__, i915__) \ + if ((IS_DG2(i915__)) && \ + ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \ + ((engine__)->uabi_instance)) { } \ + else +#define INTEL_INFO (i915) ((i915)->__info)#define RUNTIME_INFO (i915) (&(i915)->__runtime)#define DRIVER_CAPS (i915) (&(i915)->caps)drivers/gpu/drm/i915/i915_query.c +3
-2@@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,return fill_topology_info (sseu, query_item, sseu->geometry_subslice_mask); } +static int query_engine_info (struct drm_i915_private *i915,struct drm_i915_query_item *query_item)@@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,if (query_item->flags)return -EINVAL ; -for_each_uabi_engine (engine, i915) +for_each_available_uabi_engine (engine, i915) num_uabi_engines++; len =struct_size (query_ptr, engines, num_uabi_engines);@@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915, info_ptr = &query_ptr->engines[0 ]; -for_each_uabi_engine (engine, i915) { +for_each_available_uabi_engine (engine, i915) { info.engine.engine_class = engine->uabi_class; info.engine.engine_instance = engine->uabi_instance; info.flags =I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE ;
Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
In reply to Andi ShytiQuoted 77 lines · Andi Shyti
Since CCS automatic load balancing is disabled, we will impose a fixed balancing policy that involves setting all the CCS engines to work together on the same load.
Simultaneously, the user will see only 1 CCS rather than the actual number. As of now, this change affects only DG2.
Fixes d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")Signed-off-by Andi Shyti <[email protected]>Cc Chris Wilson <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Matt Roper <[email protected]>Cc <[email protected]> # v6.2+--- drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 4 files changed, 33 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/gt/intel_gt.c +11
-0@@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt) } } +static void intel_gt_apply_ccs_mode (struct intel_gt *gt) +{ +if (!IS_DG2 (gt->i915)) +return ; + +intel_uncore_write (gt->uncore,XEHP_CCS_MODE ,0 ); +} +int intel_gt_init_hw (struct intel_gt *gt) {struct drm_i915_private *i915 = gt->i915;@@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)intel_gt_init_swizzling (gt); +/* Configure CCS mode */ +intel_gt_apply_ccs_mode (gt); +/* * At least 830 can leave some of the unused rings * "active" (ie. head != tail) after resume which drivers/gpu/drm/i915/gt/intel_gt_regs.h +2
-0@@ -1605,6 +1605,8 @@#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)#define GEN12_CAGF_MASK REG_GENMASK(19, 11) +#define XEHP_CCS_MODE _MMIO(0x14804) +#define GEN11_GT_INTR_DW (x) _MMIO(0x190018 + ((x) * 4))#define GEN11_CSME (31)#define GEN12_HECI_2 (30)drivers/gpu/drm/i915/i915_drv.h +7
-0@@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) (engine__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) +/* +* Exclude unavailable engines. +* +* Only the first CCS engine is utilized due to the disabling of CCS auto load +* balancing. As a result, all CCS engines operate collectively, functioning +* essentially as a single CCS engine, hence the count of active CCS engines is +* considered '1'.
drivers/gpu/drm/i915/i915_drv.h static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) · line 415
Quoted 10 lines
drivers/gpu/drm/i915/i915_drv.h +10
-0+* Currently, this applies to platforms with more than one CCS engine, +* specifically DG2. +*/ +#define for_each_available_uabi_engine (engine__, i915__) \ + for_each_uabi_engine(engine__, i915__) \ + if ((IS_DG2(i915__)) && \ + ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \ + ((engine__)->uabi_instance)) { } \ + else +
If you don't want userspace to see some engines, just don't add them to the uabi list in intel_engines_driver_register or thereabouts?
Similar as we do for gsc which uses I915_NO_UABI_CLASS, although for ccs you can choose a different approach, whatever is more elegant.
That is also needed for i915->engine_uabi_class_count to be right, so userspace stats which rely on it are correct.
Regards,
Tvrtko
Quoted 33 lines
drivers/gpu/drm/i915/i915_drv.h +0
-0#define INTEL_INFO (i915) ((i915)->__info)#define RUNTIME_INFO (i915) (&(i915)->__runtime)#define DRIVER_CAPS (i915) (&(i915)->caps)drivers/gpu/drm/i915/i915_query.c +3
-2@@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,return fill_topology_info (sseu, query_item, sseu->geometry_subslice_mask); } +static int query_engine_info (struct drm_i915_private *i915,struct drm_i915_query_item *query_item)@@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,if (query_item->flags)return -EINVAL ; -for_each_uabi_engine (engine, i915) +for_each_available_uabi_engine (engine, i915) num_uabi_engines++; len =struct_size (query_ptr, engines, num_uabi_engines);@@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915, info_ptr = &query_ptr->engines[0 ]; -for_each_uabi_engine (engine, i915) { +for_each_available_uabi_engine (engine, i915) { info.engine.engine_class = engine->uabi_class; info.engine.engine_instance = engine->uabi_instance; info.flags =I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE ;
Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
Quoted 91 lines · Tvrtko Ursulin
Quoted 79 lines · Andi Shyti
Since CCS automatic load balancing is disabled, we will impose a fixed balancing policy that involves setting all the CCS engines to work together on the same load.
Simultaneously, the user will see only 1 CCS rather than the actual number. As of now, this change affects only DG2.
Fixes d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")Signed-off-by Andi Shyti <[email protected]>Cc Chris Wilson <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Matt Roper <[email protected]>Cc <[email protected]> # v6.2+---
drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++drivers/gpu/drm/i915/gt/intel_gt_regs.h| 2 ++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++--4 files changed, 33 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/gt/intel_gt.c +11
-0@@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt) } } +static void intel_gt_apply_ccs_mode (struct intel_gt *gt) +{ + if (!IS_DG2(gt->i915)) + return; + + intel_uncore_write(gt->uncore, XEHP_CCS_MODE, 0); +} + int intel_gt_init_hw(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915;@@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt) intel_gt_init_swizzling(gt); + /* Configure CCS mode */ + intel_gt_apply_ccs_mode(gt); + /** At least 830 can leave some of the unused rings * "active" (ie. head != tail) after resume which drivers/gpu/drm/i915/gt/intel_gt_regs.h +2
-0@@ -1605,6 +1605,8 @@ #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) #define GEN12_CAGF_MASK REG_GENMASK(19, 11) +#define XEHP_CCS_MODE _MMIO(0x14804) + #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) #define GEN11_CSME (31) #define GEN12_HECI_2 (30)drivers/gpu/drm/i915/i915_drv.h +4
-0@@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) (engine__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) +/* +* Exclude unavailable engines. +* +* Only the first CCS engine is utilized due to the disabling of CCS auto load
+ * balancing. As a result, all CCS engines operate collectively, functioning
+ * essentially as a single CCS engine, hence the count of active CCS engines is
+ * considered '1'.
+ * Currently, this applies to platforms with more than one CCS engine,
+ * specifically DG2.
+ */drivers/gpu/drm/i915/i915_drv.h static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) · line 415
Quoted 7 lines
drivers/gpu/drm/i915/i915_drv.h +7
-0+#define for_each_available_uabi_engine (engine__, i915__) \ + for_each_uabi_engine(engine__, i915__) \ + if ((IS_DG2(i915__)) && \ + ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \ + ((engine__)->uabi_instance)) { } \ + else +If you don't want userspace to see some engines, just don't add them to the uabi list in
intel_engines_driver_registeror thereabouts?
Quoted 3 lines
Similar as we do for gsc which uses
I915_NO_UABI_CLASS, although for ccs you can choose a different approach, whatever is more elegant.That is also needed for
i915->engine_uabi_class_countto be right, so userspace stats which rely on it are correct.
I later realized it is more than that - everything that uses intel_engine_lookup_user to look up class instance passed in from userspace relies on the engine not being on the user list otherwise userspace could bypass the fact engine query does not list it. Like PMU, Perf/POA, context engine map and SSEU context query.
Regards,
Tvrtko
Quoted 34 lines
Regards,
Tvrtko
Quoted 29 lines
#define INTEL_INFO(i915) ((i915)->__info) #define RUNTIME_INFO(i915) (&(i915)->__runtime) #define DRIVER_CAPS(i915) (&(i915)->caps)
drivers/gpu/drm/i915/i915_query.c +1
-0@@ -124,6 +124,7 @@ static int query_geometry_subslices(structdrm_i915_private *i915, return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask); } +static int
query_engine_info(struct drm_i915_private *i915, struct drm_i915_query_item *query_item)drivers/gpu/drm/i915/i915_query.c +2
-2@@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915, if (query_item->flags) return -EINVAL; - for_each_uabi_engine(engine, i915) + for_each_available_uabi_engine(engine, i915) num_uabi_engines++; len = struct_size(query_ptr, engines, num_uabi_engines);@@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915, info_ptr = &query_ptr->engines[0]; - for_each_uabi_engine(engine, i915) { + for_each_available_uabi_engine(engine, i915) { info.engine.engine_class = engine->uabi_class; info.engine.engine_instance = engine->uabi_instance; info.flags = I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE;
Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
Hi Tvrtko,
Quoted 2 lines · Tvrtko Ursulin
Quoted 1 line · Tvrtko Ursulin
On 15/02/2024 13:59, Andi Shyti wrote:
...
Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
+/*
+ * Exclude unavailable engines.
+ *
+ * Only the first CCS engine is utilized due to the disabling of CCS auto load
+ * balancing. As a result, all CCS engines operate collectively, functioning
+ * essentially as a single CCS engine, hence the count of active CCS engines is
+ * considered '1'.
+ * Currently, this applies to platforms with more than one CCS engine,
+ * specifically DG2.
+ */
+#definefor_each_available_uabi_engine(engine__, i915__)\
+for_each_uabi_engine(engine__, i915__)\
Quoted 8 lines
Quoted 8 lines
Quoted 5 lines
+ if ((
IS_DG2(i915__)) && \
+ ((engine__)->uabi_class ==I915_ENGINE_CLASS_COMPUTE) && \
+ ((engine__)->uabi_instance)) { } \
+ else
+If you don't want userspace to see some engines, just don't add them to the uabi list in
intel_engines_driver_registeror thereabouts?
It will be dynamic. In next series I am preparing the user will be able to increase the number of CCS engines he wants to use.
Quoted 5 lines
Quoted 5 lines
Similar as we do for gsc which uses
I915_NO_UABI_CLASS, although for ccs you can choose a different approach, whatever is more elegant.That is also needed for
i915->engine_uabi_class_countto be right, so userspace stats which rely on it are correct.
Oh yes. Will update it.
Quoted 5 lines
I later realized it is more than that - everything that uses
intel_engine_lookup_userto look up class instance passed in from userspace relies on the engine not being on the user list otherwise userspace could bypass the fact engine query does not list it. Like PMU, Perf/POA, context engine map and SSEU context query.
Correct, will look into that, thank you!
Andi
Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
Quoted 32 lines · Andi Shyti
Hi Tvrtko,
Quoted 2 lines · Tvrtko Ursulin
Quoted 1 line · Tvrtko Ursulin
On 15/02/2024 13:59, Andi Shyti wrote:
...
Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
+/*
+ * Exclude unavailable engines.
+ *
+ * Only the first CCS engine is utilized due to the disabling of CCS auto load
+ * balancing. As a result, all CCS engines operate collectively, functioning
+ * essentially as a single CCS engine, hence the count of active CCS engines is
+ * considered '1'.
+ * Currently, this applies to platforms with more than one CCS engine,
+ * specifically DG2.
+ */
+#definefor_each_available_uabi_engine(engine__, i915__)\
+for_each_uabi_engine(engine__, i915__)\Quoted 8 lines
Quoted 8 lines
Quoted 5 lines
+ if ((
IS_DG2(i915__)) && \
+ ((engine__)->uabi_class ==I915_ENGINE_CLASS_COMPUTE) && \
+ ((engine__)->uabi_instance)) { } \
+ else
+If you don't want userspace to see some engines, just don't add them to the uabi list in
intel_engines_driver_registeror thereabouts?
Quoted 2 lines
It will be dynamic. In next series I am preparing the user will be able to increase the number of CCS engines he wants to use.
Oh tricky and new. Does it need to be at runtime or could be boot time?
If you are aiming to make the static single CCS only into the 6.9 release, and you feel running out of time, you could always do a simple solution for now. The one I mentioned of simply not registering on the uabi list. Then you can refine more leisurely for the next release.
Regards,
Tvrtko
Quoted 18 lines
Quoted 6 lines
Quoted 6 lines
Similar as we do for gsc which uses
I915_NO_UABI_CLASS, although for ccs you can choose a different approach, whatever is more elegant.That is also needed for
i915->engine_uabi_class_countto be right, so userspace stats which rely on it are correct.Oh yes. Will update it.
Quoted 5 lines
I later realized it is more than that - everything that uses
intel_engine_lookup_userto look up class instance passed in from userspace relies on the engine not being on the user list otherwise userspace could bypass the fact engine query does not list it. Like PMU, Perf/POA, context engine map and SSEU context query.Correct, will look into that, thank you!
Andi
Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
Quoted 31 lines · Tvrtko Ursulin
Quoted 30 lines · Andi Shyti
Quoted 2 lines · Tvrtko Ursulin
Quoted 1 line · Tvrtko Ursulin
On 15/02/2024 13:59, Andi Shyti wrote:
...
Quoted 23 lines
Quoted 23 lines
Quoted 13 lines
+/*
+ * Exclude unavailable engines.
+ *
+ * Only the first CCS engine is utilized due to the disabling of CCS auto load
+ * balancing. As a result, all CCS engines operate collectively, functioning
+ * essentially as a single CCS engine, hence the count of active CCS engines is
+ * considered '1'.
+ * Currently, this applies to platforms with more than one CCS engine,
+ * specifically DG2.
+ */drivers/gpu/drm/i915/i915_drv.h static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) · line 415
Quoted 7 lines
drivers/gpu/drm/i915/i915_drv.h +7
-0+#define for_each_available_uabi_engine (engine__, i915__) \ + for_each_uabi_engine(engine__, i915__) \ + if ((IS_DG2(i915__)) && \ + ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \ + ((engine__)->uabi_instance)) { } \ + else +If you don't want userspace to see some engines, just don't add them to the uabi list in
intel_engines_driver_registeror thereabouts?
Quoted 4 lines
Quoted 2 lines
It will be dynamic. In next series I am preparing the user will be able to increase the number of CCS engines he wants to use.
Oh tricky and new. Does it need to be at runtime or could be boot time?
At boot time the CCS mode has to be set to '1', i.e. only one CCS will be visible to the user. Then, during the normal execution of the driver, the user can decide to change the mode and therefore we would need to expose more than one CCS engine.
Quoted 4 lines
If you are aiming to make the static single CCS only into the 6.9 release, and you feel running out of time, you could always do a simple solution for now. The one I mentioned of simply not registering on the uabi list. Then you can refine more leisurely for the next release.
Thanks. I started working on a dynamic rebuilt of the uabi_engines, but in this series it wouldn't fit.
I will add the limitation during the list creation.
Thanks a lot,
Andi
Patchwork
CI✗ Fi.CI.CHECKPATCH: warning for Disable automatic load CCS load balancing
In reply to Andi Shyti== Series Details ==
== Series Details ==
Series: Disable automatic load CCS load balancing
URL : https://patchwork.freedesktop.org/series/129951/
State : warning
== Summary ==
Error: dim checkpatch failed36e5f8a455e7 drm/i915/gt: Disable HW load balancing for CCSf1bfa29b3219 drm/i915/gt: Set default CCS mode '1'
-:80: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #80: FILE: drivers/gpu/drm/i915/i915_drv.h:409:
+#define for_each_available_uabi_engine(engine__, i915__) \
+ for_each_uabi_engine(engine__, i915__) \
+ if ((IS_DG2(i915__)) && \
+ ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \
+ ((engine__)->uabi_instance)) { } \
+ else
-:80: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects? #80: FILE: drivers/gpu/drm/i915/i915_drv.h:409:
+#define for_each_available_uabi_engine(engine__, i915__) \
+ for_each_uabi_engine(engine__, i915__) \
+ if ((IS_DG2(i915__)) && \
+ ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \
+ ((engine__)->uabi_instance)) { } \
+ else
-:80: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915__' - possible side-effects? #80: FILE: drivers/gpu/drm/i915/i915_drv.h:409:
+#define for_each_available_uabi_engine(engine__, i915__) \
+ for_each_uabi_engine(engine__, i915__) \
+ if ((IS_DG2(i915__)) && \
+ ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \
+ ((engine__)->uabi_instance)) { } \
+ else
-:82: ERROR:TRAILING_STATEMENTS: trailing statements should be on next line #82: FILE: drivers/gpu/drm/i915/i915_drv.h:411:
+ if ((IS_DG2(i915__)) && \
[...]
+ ((engine__)->uabi_instance)) { } \
-:98: CHECK:LINE_SPACING: Please don't use multiple blank lines #98: FILE: drivers/gpu/drm/i915/i915_query.c:127:
+
total: 2 errors, 0 warnings, 3 checks, 77 lines checked
Patchwork
CI✗ Fi.CI.SPARSE: warning for Disable automatic load CCS load balancing
In reply to Andi Shyti== Series Details ==
== Series Details ==
Series: Disable automatic load CCS load balancing
URL : https://patchwork.freedesktop.org/series/129951/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Patchwork
CI✗ Fi.CI.BAT: failure for Disable automatic load CCS load balancing
In reply to Andi Shyti== Series Details ==
== Series Details ==
Series: Disable automatic load CCS load balancing
URL : https://patchwork.freedesktop.org/series/129951/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14278 -> Patchwork_129951v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_129951v1 absolutely need to be verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_129951v1, please notify your bug team ([email protected]) to allow them to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/index.html
Participating hosts (36 -> 35)
------------------------------
Additional (1): bat-mtlp-8
Missing (2): bat-kbl-2 fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_129951v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@load:
- fi-skl-6600u: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-skl-6600u/igt@[email protected]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-skl-6600u/igt@[email protected]
- fi-glk-j4005: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-glk-j4005/igt@[email protected]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-glk-j4005/igt@[email protected]
- fi-skl-guc: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-skl-guc/igt@[email protected]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-skl-guc/igt@[email protected]
- fi-kbl-7567u: [PASS][7] -> [ABORT][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-kbl-7567u/igt@[email protected]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-kbl-7567u/igt@[email protected]
- fi-cfl-8700k: [PASS][9] -> [ABORT][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-cfl-8700k/igt@[email protected]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-cfl-8700k/igt@[email protected]
- fi-bsw-nick: [PASS][11] -> [ABORT][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-bsw-nick/igt@[email protected]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-bsw-nick/igt@[email protected]
- fi-cfl-guc: [PASS][13] -> [ABORT][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-cfl-guc/igt@[email protected]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-cfl-guc/igt@[email protected]
- fi-kbl-x1275: [PASS][15] -> [ABORT][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-kbl-x1275/igt@[email protected]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-kbl-x1275/igt@[email protected]
- fi-cfl-8109u: [PASS][17] -> [ABORT][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-cfl-8109u/igt@[email protected]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-cfl-8109u/igt@[email protected]
- fi-ivb-3770: [PASS][19] -> [ABORT][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-ivb-3770/igt@[email protected]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-ivb-3770/igt@[email protected]
- fi-kbl-guc: [PASS][21] -> [ABORT][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-kbl-guc/igt@[email protected]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-kbl-guc/igt@[email protected]
* igt@i915_selftest@live@client:
- fi-elk-e7500: [PASS][23] -> [DMESG-WARN][24] +42 other tests dmesg-warn
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-elk-e7500/igt@i915_selftest@[email protected]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-elk-e7500/igt@i915_selftest@[email protected]
* igt@i915_selftest@live@coherency:
- bat-jsl-3: [PASS][25] -> [DMESG-WARN][26] +41 other tests dmesg-warn
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/bat-jsl-3/igt@i915_selftest@[email protected]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-jsl-3/igt@i915_selftest@[email protected]
* igt@i915_selftest@live@gt_contexts:
- fi-ilk-650: [PASS][27] -> [DMESG-WARN][28] +42 other tests dmesg-warn
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-ilk-650/igt@i915_selftest@live@gt_contexts.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-ilk-650/igt@i915_selftest@live@gt_contexts.html
* igt@i915_selftest@live@gt_pm:
- bat-jsl-1: [PASS][29] -> [DMESG-WARN][30] +41 other tests dmesg-warn
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/bat-jsl-1/igt@i915_selftest@live@gt_pm.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-jsl-1/igt@i915_selftest@live@gt_pm.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses. They do not affect the overall result.
* igt@gem_exec_fence@basic-busy@rcs0:
- {bat-arls-1}: [PASS][31] -> [DMESG-WARN][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/bat-arls-1/igt@gem_exec_fence@[email protected]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-arls-1/igt@gem_exec_fence@[email protected]
Known issues
------------
Here are the changes found in Patchwork_129951v1 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- fi-apl-guc: [PASS][33] -> [FAIL][34] ([i915#8293])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/fi-apl-guc/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/fi-apl-guc/boot.html
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][35] ([i915#9318])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][36] ([i915#4613]) +3 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@gem_mmap@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][37] ([i915#4083])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@gem_mmap_gtt@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][38] ([i915#4077]) +2 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][39] ([i915#4079]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][40] ([i915#6621])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][41] ([i915#5190])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][42] ([i915#4212]) +8 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][43] ([i915#4213]) +1 other test skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][44] ([i915#3555] / [i915#3840] / [i915#9159])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@kms_force_connector_basic@force-load-detect:
- bat-mtlp-8: NOTRUN -> [SKIP][45] ([fdo#109285])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-8: NOTRUN -> [SKIP][46] ([i915#5274])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@kms_setmode@basic-clone-single-crtc:
- bat-mtlp-8: NOTRUN -> [SKIP][47] ([i915#3555] / [i915#8809])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@prime_vgem@basic-fence-mmap:
- bat-mtlp-8: NOTRUN -> [SKIP][48] ([i915#3708] / [i915#4077]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][49] ([i915#3708]) +2 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-mtlp-8/igt@[email protected]
#### Possible fixes ####
* igt@gem_exec_create@basic@smem:
- {bat-arls-1}: [DMESG-WARN][50] ([i915#10194]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14278/bat-arls-1/igt@gem_exec_create@[email protected]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/bat-arls-1/igt@gem_exec_create@[email protected]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#10194]: https://gitlab.freedesktop.org/drm/intel/issues/10194
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
Build changes
-------------
* Linux: CI_DRM_14278 -> Patchwork_129951v1
CI-20190529: 20190529
CI_DRM_14278: 000df4b23820dc3866d8c92c228c778ef33bf396 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7714: 7714
Patchwork_129951v1: 000df4b23820dc3866d8c92c228c778ef33bf396 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
08e0f187cab5 drm/i915/gt: Set default CCS mode '1' c21b8eb46264 drm/i915/gt: Disable HW load balancing for CCS
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v1/index.html